Monday, March 10, 2025 11:18 PM

Let us try to understand the fundamental cause of Metastability using the most
basic CMOS Gate i.e. an Inverter.

If for the given CMOS Gate Vin = 0V (Logic 0) then Vout = 5V (logic 1) as in this case
PMOS is turned on (in linear region) pulling up the output close to VDD = 5V.

On the other hand if Vin = 5V (Logic 1) then Vout = 0V (logic 0) as in this case NMOS
is turned on (in linear region) pulling down the output close to ground (0V).

So as you can see above, the given CMOS inverter acts like a perfect NOT gate for
the given set of inputs i.e. Vin = 0V or 5V (logic 0 and logic 1)

So far so good right?

But what if by any chance intentionally or unintentionally Vin is a value which is
neither a logic 1 (5V) or logic 0 (0V). Let's say Vin is the mid-point of the two
supplies (i.e. 5V and 0V) in other words Vin = 2.5V. How this so called CMOS
inverter behaves in this case? Is the output equal to 5V or 0V in this case?

This is the most favorite case for Metastability to come into the picture!!!
In this case since the Vin is neither logic 0 nor logic 1, the digital gate will not be
able to decide how to respond to this input digitally.

Remember here, we are trying to find the answer to the question that why a flip flop goes into the
metastable state when a signal violates the setup and hold time requirement of the flip flop.

In the above circuit, since Vin = 2.5V, both NMOS and PMOS will get turned ON but not in the linear region.
In fact both will get turned ON in saturation region!!! Since you might know that if a MOS is in saturation region,
it acts like a constant current source with a given Vin ( a case where it can be used as an Amplifier).

So both NMOS and PMOS will act like a current source and since both NMOS and PMOS are connected in series
here ( See the same current that flows in PMOS from VDD, the same current flows in NMOS to ground), this is a
typical case in the world of Analog circuits, where two exactly same current sources carrying equal currents are
connected in series as shown below!!!

You consider it as two identical resistors carrying equal current.

The Concept of MetaStability in digital Circuits Page 1

 Okay very nice!!!!
So far we have proved that the inverter circuit produces Vout = Vdd/2 = 2.5V when its input = 2.5V !!!
i.e. the output of the inverter get stuck at 2.5V!
What does it signify??? It tells us that this inverter circuit has one more stable state (called meta stable
state) other than the two stable states (Logic 0 and Logic 1).
This new stable state, known as the meta stable state, is usually very dangerous and unwanted in Digital
Circuits and Systems. But it’s a very favorable state in Analog circuits!!! A devil at one place is an angel at
another place lol

But in practical circuits, even a very low noise in the inverter can cause the inverter to come out of this
meta stable state and the output can be settled to either Logic 1 (5V) or Logic 0 (0V) depending upon the
nature of the noise and since noise is random, the logic state of the inverter circuit is also random after
it come out of the meta stable state.

Also, even If we consider that there is no noise in the inverter or in the environment, still if we consider
a practical scenario, then it's impossible to make exactly identical current sources!! If there is a
mismatch between the 2 current sources then the one which is having larger current ( i.e. stronger
current source) will pull the output towards it. For example, if the PMOS is stronger than NMOS in the
above inverter circuit, then it will pull the output towards it i.e. towards VDD and Vout = VDD = 5V.
On the hand, if the NMOS is stronger than the PMOS in the above inverter circuit, then it will pull the
output towards it i.e. towards GND and Vout = 0V. And if either of the NMOS or PMOS is stronger
randomly then in this case also the logic state of the inverter circuit is random after it comes out of the
meta stable state.

So in any of the above two cases, the state (output) of the inverter is random i.e. Logic 0 or Logic 1, we
can't say for sure!!!

I hope by now you have understood the basic cause of metastability at a very fundamental level.

I again want to remind you that here we are trying to find the answer to the question that why a flip flop
goes into the metastable state when a signal violates the setup and hold time requirement of the flip flop.

Now let us make a very simple and fundamental memory element from inverter, i.e. A cross coupled
inverter latch which is the fundamental building block of storing elements including Flip Flops.

Let's assume that the initial state of the latch is 'a' = 0V (logic 0) hence 'b' = 5V (logic 1) and 'c' = 0V (logic
0), and let's connect a switch at 'a'

Let us close the switch at 'a' which will start charging the node 'a' from 0V to 5V. But what will happen if we
make the switch back to open before the node 'a' charges to 5V. It might get charged to only 2.5V which is the
input of inverter 1. Do you remember which is this case?? Yes you are right! It's exactly the case that we
discussed just a while ago for an inverter to go into meta stable state, and hence the inverter 1 will go into
meta stable state. Since the output of inverter 1 is the input to inverter 2, the inverter 2 will also be in meta
stable state. Hence the above latch will go into meta stable state.

The Concept of MetaStability in digital Circuits Page 2

Now depending upon the disturbance (noise) or depending upon whether the pull-up or pull-down transistor
network is strong, the state of the latch after it comes out of the meta stable state is random or unpredictable.
It can be Logic 0 or Logic 1.

Here I have tried to explain how a latch can go into meta stable state in the simplest way as possible through a
simple yet powerful example. You might be thinking that how to close and open the switch so fast! But that’s
not a topic of discussion here! I just wanted to explain what can be the scenario when the basic cross coupled
latch goes into metastable state.

To summarise:
If by any means the cross coupled latch element samples a value which cannot be considered as Logic 0 or Logic
1 ( as in the above cross coupled latch) then the latch will go into meta stable state and the state after it comes
out of the meta stable state is unpredictable, it can be Logic 0 or Logic 1.

Now remember this kind of cross coupled latch element is the heart of Flip-Flops. So does it mean if the flip-
flop samples a value which cannot be considered as Logic 0 or Logic 1 then the flip-flop will also go into
Metastable state? The Answer you can guess is YES INDEED.

Now the question arises when will a flip-flop sample a value which cannot be considered as Logic 0 or Logic 1?
It is when the signal at the flip-flop input violates the setup and hold time requirements. So you see every dot is
getting connected here and we finally get our answer of why a flip-flop goes into the metastable state when a
signal violates the setup and hold time requirement of the flip flop.

I am sharing here some more diagrams from which you can easily interpret and see what happens when a
signal violates setup and hold time requirement at the input of a flip-flop.

The Concept of MetaStability in digital Circuits Page 3

Do you want a real life example where you can experience Metastability in action? Here you go!!!

Metastability and the Elevator Button Dilemma

Imagine you're in an office/College building waiting for an elevator. You press the up button, and at the
same exact moment, someone else presses the down button.
The elevator "gets confused" for a moment—should it go up or down? It can’t decide instantly, so
there’s a brief delay before it finally picks a direction.

This is just like metastability in digital circuits:

• If the elevator had only one clear request, it would move immediately (like a flip-flop capturing a
stable '0' or '1').
• But because two conflicting requests happened at the same time, the system takes a moment to
resolve the situation—just like a flip-flop entering a metastable state before stabilizing.
This brief "undecided" moment in the elevator is similar to how a flip-flop struggles to decide between 0
and 1 when setup and hold times are violated. Eventually, both the elevator and the flip-flop settle on
an outcome, but the delay can disrupt smooth operation.

The Concept of MetaStability in digital Circuits Page 4