RTu2E-4

A 28 GHz Optically Synchronized CMOS Phased Array with an

Integrated Photodetector
Matan Gal-Katziri 1 , Craig Ives, Armina Khakpour and Ali Hajimiri
California Institute of Technology, Pasadena, CA 91125, USA
1
[email protected]

Optical Large/ sparse array

Abstract — This paper presents a modular 28 GHz phased
array. Each of its 2×4-modules is driven by a CMOS RFIC, timing
whose RF output is optically synchronized using a fully integrated signal
Multi-element module
silicon photodiode. The photocurrent is amplified using a tuned
injection-locked TIA to serve as the reference for an on-chip A Fully integrated optically synchronized RFIC
synthesizer, which generates and distributes the RF signal to the An optical interface to IC surface
X8 TX channels
PAs that drive the antennas. We demonstrate beam steering, data Aux. pad 28 GHz PLL
transmission, and synchronization of array modules up to 25m
away from the clock source. +-
Keywords — phased arrays, CMOS, injection-locked φφ
÷N
CMOS PD TIA chain Signal Split
oscillators, optoelectronics, photodiodes, silicon photonics.
Fig. 1. System diagram of the optically synchronized phased array transmitter.

I. I NTRODUCTION
Phased array beamforming and beam steering capabilities frequency range and allows the construction of large and/or
scale favorably with increasing array size. This has led to their sparse arrays, while synchronizing to a 7 GHz optical clock
proliferation in various fields from cellular communication to reference. A front-end receiver with a fully-integrated CMOS
automotive radar. As the operation frequency and number of photodiode (PD), operating near the visible regime, receives,
elements increase, conventional distribution and amplification conditions, and amplifies the optical signal to the 1V supply
of the RF signal across the array becomes more challenging. digital levels. The high frequency reference enables the use of
This has led to local signal synthesis architectures that are a low-noise, fully integrated synthesizer (PLL) to generate the
more compatible with low-cost CMOS integration and rely on desired output RF frequency and to distribute it to eight TX
the electrical distribution of timing information [1][2]. Despite channels with independently controlled phase and amplitude.
its many advantages, the electrical distribution of a frequency This paper demonstrates beamforming and data transfer using
reference either suffers from synthesizer noise multiplication if an OTS phased array. The RFIC was designed and fabricated
the reference frequency is too low, or becomes expensive and in a standard 65nm bulk-CMOS process, and assembled onto
power hungry if it is too high, due to the necessary splitting and a 2×4 phased-array module (Fig. 2a,2b). The module utilizes
buffering. Neither scales well with the size, span, or operation on-board patch antennas 0.6λ apart to accommodate signal
frequency of the array. This scaling becomes more critical with routing with a minimal effect on grating lobe generation. The
the rapidly increasing relevance of large and/or sparse arrays. optical clock interfaces with the CMOS-PD by threading an
Optical timing synchronization (OTS) can overcome some optical fiber through a via opening in the phased-array module,
of these challenges. It has been used mostly in scientific as shown in Fig. 2c. The signal headers on the back side of the
and precision instruments, such as radio telescopes. Table module are fanned out using a secondary PCB, which is also
1 compares the performance of common RF materials to used to support the fiber mount. This modular design enables
optical fibers, and shows that optical infrastructure provides scalability to large arrays.
more than an order of magnitude of improvement in the
A. Front-end design
cost, line loss, and mass of the synchronization network. A
major challenge with this approach is that existing realizations Fully integrated bulk CMOS photodiodes enable complete
[3][4] use a complex mix of bulky and expensive off-the-shelf, integration of the optical receiver with the rest of the RF
discrete components. In this paper, we demonstrate a phased circuitry on the same low cost substrate. The integrated PD
array using CMOS chips with integrated silicon photodetectors
that synchronize the array, enabling optical synchronization Table 1. Comparison of available RF and optic-fiber materials in terms of
schemes in a wide range of applications. mass, signal attenuation and cost (*small quantities).

II. S YSTEM OVERVIEW Material Mass density Loss Cost

RG58 coax 170 g/m 2.3 dB/m ∼$15/m∗
This work presents an optically synchronized, 8-element 20 mil RO4350B 1.83 g/cm3 6.3 dB/m ∼$30/cm2∗
phased array CMOS RFIC as the building block of an OTS SMF-28 jacketed 17.4 g/m 0.5 dB/km ∼$3/m∗
array, as illustrated in Fig. 1. It operates in the 28 GHz SMF-28 bare 2.9 g/m 0.5 dB/km ∼$3/m∗

978-1-6654-2549-0/21/$31.00 © 2021 IEEE 111 2021 IEEE Radio Frequency Integrated Circuits Symposium
 VDD

Buffer PA
PLL PS

2.1mm
÷2

TIA
On-chip CMOS PD 45μm x 45μm
RFIC Die
(a) (b) 2.1mm
RFIC Die
RFIC Die Antenna Board
Fiber Holder
Headers
Vr
Fan-out and
fiber
support Fig. 4. Schematic of the TILTIA, where Vr is the reverse bias.
Fiber Via Hole
(c)
VCO
Fig. 2. The phased array building block: (a) the fully assembled PCB, (b) REFin
3.5GHz 28 GHz REFout
die photo, and (c) structure of the fiber mount. CP
R
PD
R
C C
780 nm STI guard ring C R2R
With index matching fluid
N++ 120 DAC
Without index
P-well
matching fluid*
mA/W

80 *Measured to 8 V only
Deep N-well
3.5GHz 7GHz 14GHz
40 ÷2 TSPC ÷2 CML
P-sub
ILFD
2 4 6 8
Optical intensity (a) Doping profile (b) Reverse bias (V)
Fig. 5. Top schematic of the PLL.
Fig. 3. (a) Simulation of optical intensity in the photodiode (left), and diagram
of the doping profile (right). (b) Measured photodiode responsivity.
while keeping the VCO noise sufficiently low. Using a small
multiplication ratio provides low jitter performance of 147 fs,
here is an n++/p-well diode with a shallow-trench isolation as shown in Fig. 8a. The smaller harmonic content in the VCO
(STI) guard ring and deep n-well diffusion current block voltage control node reduces the risk of harmonic locking.
[5], as shown in Fig. 3a. Intensity modulated 780nm light Lastly, a high frequency reference results in far-out spurs that
is supplied by an optical fiber passing through a 140µm via are further suppressed by the loop, the tuned RF path, and
from the backside of the PCB. The fiber interfaces with the the antennas’ bandwidths. This eases the system compliance
bulk CMOS-PD through index-matching material, producing with spectral disturbance level requirements. The PLL core is
a responsivity over 120 mA/W at 9V reverse bias (Fig. 3b). further buffered to drive the eight output channels.
A tuned injection-locked TIA (TILTIA) is used to receive
and amplify the photocurrent from the integrated PD. The C. TX channel
500 fF PD capacitance is resonated at 7 GHz with an inductor, The TX architecture enables a broad range of applications,
which also biases the cathode (Fig. 4). The PD anode is reverse irrespective of the detailed specifications of the RF chain.
biased by the voltage Vr , which can typically drop as low as For this phased array transmitter, we divided the chip into
-9V before breakdown occurs. The PD signal is fed into one four quadrants, each of which is buffered by an independently
gate of a differential pair, which facilitates injection locking programmable VGA that drives a pair of TX channels. Each
and doubles as a single-ended-to-differential converter. The channel is composed of a first-order RC polyphase filter
differential pair is in parallel with a cross-coupled pair that (PPF), a vector modulator and a PA that can operate both
has a digitally-tunable negative conductance, producing an in linear and switching modes, as illustrated in Figs. 6 and
LC-oscillator that can be injection-locked by the PD signal. 7. Although the PPFs are not buffer-isolated from each other
The differential reference is then buffered and divided to 3.5 to reduce the power consumption, they are followed by the
GHz to serve as the frequency reference for the on-chip PLL. vector modulator gates to minimize the coupling between the
The combined TILTIA and divider together draw 9 mA from channels. The vector modulators are fully independent with
a 1V supply. An added benefit of this topology is its inherent phase and amplitude errors of 3.7◦ and 3.6% rms (Fig. 8c,d),
built-in self-test (BIST) capability. Digitally configuring the respectively, when using a lookup table. Each phase shifter
TILTIA to self-oscillate enables the characterization of all the drives a two-stage power amplifier (PA), which generates more
subsequent stages without an input signal. than +12 dBm output power at 28 GHz for a total power
of +21 dBm with a drain efficiency of 23% (Fig. 8b). The
B. Low-multiplier frequency synthesis
output PA stage has series-inductors added between the driving
The frequency multiplying PLL (3.5 GHz to 28 GHz) transistors and the cascode in order to align the output voltage
in Fig. 5 is co-designed with the receiver amplifier to limit and current waveforms, which slightly increases the drain
the output bandwidth and reduce the reference-related jitter,

112
 VDD
Vout ps,p Vout ps,n
Ltune

Vin ps,p Vin ps,p

Vout ps,p Vout ps,n

Ctune Vin ps,n

0⁰ 180⁰

Gilbert cell Gilbert cell

Vq,n
Vq,p
Vi,p

Vi,n
Vq Vi
Fig. 9. Test setup for a single optically synchronized RFIC module.

Polyphase R R R R
filter dB MKR: -28.5 dBm Integrated jitter = 590 fs
C C C C -30 -75
-40 -80
Vin,p

Vin,n
Vin,p Vin,n -85
-50
-60
-70
Fig. 6. Phase shifter schematics with Gilbert cell and polyphase filter. -80 -100
-90 -105
-100 -110
Meas. noise floor
Z0=65Ω
Vout
Center 27.9 GHz Span 50MHz 5 MHz/DIV 100KHz 1MHz 10MHz
(a) (b)
Ltune Ltune VDD
VDD VCAS Fig. 10. (a) Output of an optically synchronized RFIC module. (b) System
phase noise with an optical reference, where the CMOS-PD is mounted next
Vin,p Vin,n
to the RFIC (integrated PD shows similar performance).

Fig. 7. Schematic of the power amplifier. This measurement was done both with an on-chip integrated
CMOS-PD and with an identical external CMOS-PD,
fabricated on the same die and connected to the auxiliary
efficiency. This PA topology was specifically chosen to provide pad, with similar results. Fig. 10 shows the output signal
flexible element-level amplitude control. spectrum and the resulting phase noise measurement. It should
III. M EASUREMENT RESULTS be noted that this is an unbuffered measurement which reflects
A. Module optical synchronization additional amplitude noise and increased noise floor due
to free-space attenuation. Fig. 11 shows the beam steering
As one demonstration of OTS, we distribute an optical capabilities of the optically synchronized array.
carrier, intensity modulated at 7 GHz by the reference clock,
over a 25m optical fiber to the CMOS photodiode (Fig. 9). B. Data transfer
Data transfer through the array is demonstrated by
modulating the IQ phase-shifter steering angle. The
Ref: -70 dBc/Hz Center frequency: 28GHz 13 25
Pout [dBm]

10 dB/ modulation is done for a single output channel in order

Drain Efficiency [%]

11 20 to minimize multipath reflections, using a pseudo-random

9 15
154MHz
Integrated jitter = 147 fs 7 10

Estimated Input Power [dBm]

5
10KHz 1GHz -10 -6 -2 2 6
(a) (b)
5 1
S21 [dB]

0.8 90⁰
135⁰ 0.6 45⁰
0
0.4
0.2
-5 180⁰ 0⁰
RMS Errors
Phase = 3.7⁰
Mag. = 3.6%
-10
Frequency [GHz] 225⁰ 315⁰
-15 26 27 28 29 30 270⁰
(c) (d)
Fig. 8. (a) PLL phase noise, (b) PA output power and drain efficiency, Fig. 11. Beam steering of an optically synchronized RFIC module, CMOS-PD
(c) normalized TX channel gain at all 180 different phase states, and (d) mounted next to the RFIC (integrated PD shows similar performance).
uncalibrated vector modulator constellation.

113
 dB dB
-30 -30
Optical ref. RF ref. -40 -40

0.6 Mbps 0.6 Mbps -50 -50

-60 -60
-70 -70
-80 -80
-90 -90
-100 -100

(a) (b)
dB
-30
-40

(a) (b) -50

-60
Fig. 12. 16-QAM constellation with an (a) optical, and (b) RF reference. -70

-80

-90
RFIC module -100

5 m optic-fiber
N9030B
12 cm Laser (c) (d)
Spectrum -3dB split
source
Analyzer Fig. 14. Optical synchronization of two modules: (a) module 1 peak power
5 m optic-fiber is -29.25 dBm, (b) module 2 is -28.90 dBm, and (c) combined peak power
RFIC module is -24.11 dBm, demonstrating coherent addition of the two module outputs.
(d) The normalized power vs. number of active elements radiated by a single
Fig. 13. Test setup showing optical synchronization of two RFIC modules.
RFIC module.

custom logic state machine implemented on an FPGA. The large-aperture arrays in high-volume commercial applications.
TX channel output bandwidth (Fig. 8c) is larger than 1 GHz Along with the reduced mass and loss, it provides an
and thus supports high data rates, with the data rate being attractive alternative to traditional high-frequency clocking
limited by the chip programming interface speed in the current schemes. Table 2 compares the optically driven RFIC to other
implementation. Fig. 12 displays the raw measurement of the state-of-the-art works, illustrating the significant size scaling
received signal, measured by a signal analyzer. It shows the benefits of our approach.
EVM when the reference is driven by a laser source through
the CMOS-PD, compared to the same chip driven by an R EFERENCES
external RF signal connected its auxiliary pad, proving the [1] S. Jeon et al., “A scalable 6-to-18 GHz concurrent dual-band quad-beam
phased-array receiver in CMOS,” JSSC, vol. 43, no. 12, pp. 2660–2673,
viability of OTS. It is noteworthy that the shown EVM is 2008.
calculated and affected by deterministic constellation errors [2] M. Gal-Katziri and A. Hajimiri, “A sub-picosecond hybrid DLL for
as resolved by the instrument, and so can be further improved large-scale phased array synchronization,” in ASSCC, Nov 2018, pp.
231–234.
using post-processing procedures. [3] B. Gao et al., “High-resolution phased array radar imaging by
photonics-based broadband digital beamforming,” Opt. Express, vol. 27,
C. Synchronizing two electrically distant arrays no. 9, pp. 13 194–13 203, Apr 2019.
Lastly, we use OTS to synchronize between two electrically [4] Y. He et al., “Long-distance telecom-fiber transfer of a radio-frequency
reference for radio astronomy,” Optica, vol. 5, no. 2, pp. 138–146, Feb
distant array elements. We drive two phased array modules 2018.
through two 5m optical fibers carrying the same optical signals, [5] M.-J. Lee and W.-Y. Choi, “Performance optimization and improvement of
as shown in Fig. 13. Half the array elements in each module silicon avalanche photodetectors in standard CMOS technology,” JSTQE,
vol. 24, no. 2, pp. 1–13, Mar. 2018.
are turned on and steered towards the receiver, producing a [6] J. D. Dunworth et al., “A 28GHz Bulk-CMOS dual-polarization
coherent increase of received power, comparable to the total phased-array transceiver with 24 channels for 5G user and basestation
power received by a single module with all its array elements equipment,” in ISSCC, 2018, pp. 70–72.
[7] J. Pang et al., “21.1 A 28GHz CMOS Phased-Array Beamformer Utilizing
steered broadside, as illustrated in Fig. 14. Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO
for 5G NR,” in ISSCC, 2019, pp. 344–346.
IV. C ONCLUSION [8] Y. Hu et al., “17.6 A 21.7-to-26.5GHz Charge-Sharing Locking
This work presents the first fully integrated OTS system Quadrature PLL With Implicit Digital Frequency-Tracking Loop
Achieving 75fs Jitter and -250dB FoM,” in ISSCC, 2020, pp. 276–278.
in a bulk-CMOS process with beam steering, remote module [9] M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated
synchronization, and data transmission capabilities. The with standard CMOS technology with over 1 THz gain-bandwidth
implementation of OTS in low-cost CMOS enables the use of product,” Optics Express, vol. 18, no. 23, p. 24189, Nov. 2010.

Table 2. Comparison table

ISSCC ’18 [6] ISSCC ’19 [7] ISSCC ’20 [8] OE [9] This work
Process 28nm CMOS 65nm CMOS 28nm 65nm 65nm CMOS
Measured PD responsivity @ 9V NA NA NA 20 mA/W 135 mA/W
Frequency [GHz] 28 28 21.7-26 NA 28
PLL phase noise [fs] @ range NA NA 76 @ 10k-30M NA 147 (590 with PD) @10k-150M
Output power/channel [dBm] 14 15.1 NA NA 12
DC power/channel [mW] 119 252 NA NA 215
Synchronization network length NA NA NA NA 10m (25m from the source)

114