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The document outlines a one-month summer training course on Digital IC Design using Verilog HDL, targeting students, faculty, and hobbyists. The course covers foundational topics in Verilog, FPGA design flow, and ASIC design approaches, with hands-on labs and projects. It includes various design examples and utilizes tools such as Vivado, Quartus, and open-source EDA tools.

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shreesaddhoon
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2 views

course_curriculum

The document outlines a one-month summer training course on Digital IC Design using Verilog HDL, targeting students, faculty, and hobbyists. The course covers foundational topics in Verilog, FPGA design flow, and ASIC design approaches, with hands-on labs and projects. It includes various design examples and utilizes tools such as Vivado, Quartus, and open-source EDA tools.

Uploaded by

shreesaddhoon
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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One-Month Summer Training on Digital IC Design Using Verilog HDL

From Simulation to FPGA and ASIC Flow

(Foundation course)

🎯 Target Audience: Topics:

●​ Combinational Logic Design:​


●​ B.E/B.Tech/M.E/M.Tech students (ECE,
EE, CSE) ●​ Sequential Logic Design:​
●​ Faculty members who are new to this
subject ●​ Finite State Machines (FSM):​
●​ Hobbyists and enthusiasts of Digital IC ○​ Moore and Mealy FSM design​
Design
●​ Beginners looking to enter FPGA or ○​ Case studies: Traffic light
ASIC design domains controller, Sequence detector

●​ Labs:

📚 Course Modules & Contents: 🔹 Week 3: FPGA Design Flow Using Vivado
and Quartus
🔹 Week 1: Foundations of Verilog HDL Objective: Translate Verilog RTL into physical
implementation on FPGA
Objective: Build strong fundamentals in Verilog
HDL syntax, semantics, and modeling
techniques. Topics:
●​ Introduction to FPGA Architecture and
Topics: Technology​
●​ Introduction to Hardware Description
Languages​ ●​ Overview of FPGA Design Flow:​

●​ Data Types & Operators in Verilog​ ○​ RTL → Synthesis → PNR →


Bitstream Generation​
○​ Nets, Registers, Vectors,
Parameters, Arrays​ ●​ Using Vivado (Xilinx-AMD) and
Quartus (Altera-Intel):​
●​ Verilog Modeling Styles:​
○​ Creating new project​
○​ Gate-Level Modeling​
○​ RTL import, Constraint files​
○​ Dataflow Modeling​
○​ Synthesis and Implementation​
○​ Behavioral Modeling​
○​ Bitstream (.bit) and .sof file
generation​
○​ Structural Modeling
●​ Labs:​ ●​ Basic Timing Constraints and IO Pin
Assignment​

🔹 Week 2: Design Examples – From Logic


to FSM
●​ Configuration and downloading the
bitstream on real hardware (if available)

●​ Labs:
Objective: Learn how to write Verilog for
practical digital designs and simulate them.
🔹 Week 4: ASIC Design Approach Using
Open-Source Tools a) 8 bit asynchronous up-down counter
b) 8 bit synchronous up-down counter
Objective: Explore the ASIC flow using
open-source EDA tools 6. sequence detector through Moore state
machines and Mealy state machines
Topics:
●​ ASIC vs FPGA: comparison Major projects
●​ Introduction to RTL-to-GDSII Flow
●​ Tools Covered: 1. UART​
○​ OpenLane (RTL to GDSII 2. Secure Hash Algorithm-1
automation) 3. 32-bit ALU
○​ OpenROAD (Synthesis, 4. Booth multiplication Algorithm​
Floorplanning, Placement, 5. Restoring and Non-restoring Algorithms

💻 Tools & Software Used:


Routing)
●​ Flow Overview:
○​ RTL → Synthesis (Yosys)
○​ Floorplanning & Power Planning
○​ Placement, Clock Tree ●​ Simulation: Icarus Verilog, GTKWave,
Synthesis, Routing ModelSim​
○​ DRC/LVS and GDSII
Generation ●​ FPGA: AMD(Xilinx) Vivado, Intel (Altera)
●​ Sky130 PDK – Understanding Quartus​
open-source Process Design Kits
●​ Labs: ●​ ASIC: Yosys, OpenLane, OpenROAD,
Magic, KLayout​

The following design examples will ●​ Platforms: Ubuntu Linux, Windows​


be considered for all Labs:
1. structural and dataflow Verilog HDL
models for
a) 4-bit ripple carry adder.
b) 4-bit carry Adder – cum Subtractor.
c) 2-digit BCD adder/subtractor.
d) 4-bit carry look-ahead adder
e) 4-bit comparator

2. Behavioral Verilog HDL models for

a) 8:1 multiplexer
b) 3:8 decoder
c) 8:3 encoder
d) 8-bit parity generator and checker

3. Hierarchical structural Verilog HDL models


for

a) 16:1 multiplexer realization using 4:1


multiplexer
b) 3:8 decoder realization through 2:4
decoder
c) 8-bit comparator using 4-bit
comparators and additional logic

4. Behavioral model for D,T and JK flip flops,


shift registers and counters.

5. Structural and Behavioral Verilog HDL


models for

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