DESIGNWARE IP DATASHEET

DDR4 multiPHY IP

Highlights Overview
• Supports JEDEC standard DDR4, DDR3, The Synopsys DesignWare® DDR4 multiPHY is a complete physical (PHY) layer
DDR3L (1.35V DDR3) , DDR3U (1.25V IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on-
DDR3), LPDDR2, and LPDDR3 SDRAMs chip (SoC), and system-in-package applications requiring high-performance
• High-performance DDR PHY supporting DDR4/DDR3/DDR3L/DDR3U/LPDDR2/LPDDR3 SDRAM interfaces operating
data rates from 0 to 2667 Mbps at up to 2667 Mbps. The DesignWare DDR4 multiPHY is ideal for systems that
require high DDR3/4 performance and also may require compatibility with
• Per-bit deskew for both read and write
the latest mobile SDRAMs (LPDDR2 and LPDDR3) for chips targeting multiple
data paths
applications with varying performance requirements.
• Per-bit deskew for address/command
bus when used with LPDDR3 SDRAMs
• Designed for rapid integration with DDR memory or
Synopsys Universal Protocol or Memory protocol controller
Controllers for a complete DDR

DFI 3.1
interface solution
• Includes application-specific DDR I/Os DDR4 multiPHY

including programmable drive strength

PHY utility block
and On-Die Termination (ODT)
• DFI 3.1 compliant controller interface
Data Address Data
block PLL command PLL block
Target Applications
• Data centers (networking and storage)
DDR I/O
• Digital home
• Mobile multimedia
• Wireless connectivity
DDR DDR
• Digital office SDRAM SDRAM

Figure 1: DesignWare DDR4 multiPHY IP

Technology
• 28-nm, 20-nm, 16-nm and below
Optimized for high performance, low latency, low area, low power, and ease of
integration, the DesignWare DDR4 multiPHY is provided as a hard DDR PHY
that is primarily delivered as GDSII and includes the application-specific I/Os.
Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that
includes PHY control features such as write leveling, data eye training, per-bit
data deskew control, PVT compensation, and support for production testing
of the DDR4 multiPHY. The DDR4 multiPHY includes a DFI 3.1 interface to
the memory controller and can be combined with any of Synopsys’ universal
memory or protocol controllers for a complete DDR interface solution.

synopsys.com/designware
DDR4 multiPHY Key Features
• Low latency, small area, low power
• Compatible with JEDEC standard DDR4 up to 2667 Mbps
• Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
––Supports DDR3L (1.35V DDR3) up to 1866 Mbps
––Supports DDR3U (1.25V DDR3) up to 1600 Mbps
• Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
• Compatible with JEDEC standard LPDDR3 SDRAMs up to 2133 Mbps
• DFI 3.1 compliant interface to the memory controller
––1:1 and 1:2 clock modes supported
––1:1 or 1:2 clock mode can be selected via software at boot time
• Support for 4-bit, 8-bit, 16-bit and 32-bit wide SDRAMs
––2-channel (64-bit) LPDDR2 and LPDDR3 SDRAM supported
• Support for SDRAM components soldered directly to PCB
• Support for DDR4 and DDR3 UDIMMs and RDIMMs
• Data path width scales in 8-bit increments from 8 bits to 72 bits
• Support for partially populated interfaces
• Support for 1, 2, 3, or 4 memory ranks
• Support for Shared AC mode that permits one address and command channel to be time division multiplexed between two
independent data channels
• Capability to be trained for two distinct frequencies to permit fast changes between two frequencies
• Voltage and temperature compensated delay lines used for:
––Centering the clock in the address/command window
––Centering the strobes in the data eyes
––DDR3/4 write leveling
––Per-bit deskew
• Support for the PHY to be distributed around a chip
––Distributed byte lanes and command lanes
––Supports LPDDR2 and LPDDR3 PoP systems
––Supports PHYs that go around a die corner
• Support for 28-nm poly orientation rules
––Macrocells and PLLs can support I/Os instantiated on orthogonal sides
––One PLL can supply two abutted macrocells
• Includes the PHY Utility Block (PUB)
––Soft IP Verilog design that includes PHY control features, such as write leveling and data eye training
––Provides support for production testing of the DDR4 multiPHY
• At-speed loopback testing on both the address and data channels
• MUX-scan ATPG (stuck-at SCAN)

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DDR4-Specific Features
• Support for DDR4 1.2V Pseudo Open Drain (POD) I/O
• DRAM addressing up to 16Gb
• MPR writes/reads
• Data bus inversion (DBI)
• Direct programming of DQ VREF level setting
• Automatic training of DQ VREF level setting
• CA parity
• Maximum power down mode

DDR4 multiPHY I/O Features

• DDR4, DDR3, DDR3L, DDR3U, LPDDR2, and LPDDR3 operating modes, including POD_12 support for DDR4
• Support for 28-nm poly orientation rules
––Two different cell orientations provided for relevant SSTL library cells permitting the thin-oxide devices to maintain a
unidirectional orientation when placed on any side of the die
• Programmable input termination (ODT)
• Programmable output impedance
• Supports ability to groups sections of I/O cells have different input termination and/or output impedance settings per section
• Supports mid-rail termination for DDR3 and DDR4 address/command channel and VDDQ termination for DDR4 data channels
• PVT-compensated ODT and output impedance
• Separate driver and receiver power-down control
• VREF supply cell
––Allows PHY to generate a register-adjustable VREF supply for the PHY and the DRAM
• Embedded boundary scan support logic
• PAD and internal loopback modes
• Supports traditional wire bond, Circuit Under Pad (CUP), and flip chip applications
• Retention feature maintains I/O cell state during VDD power down
• Power On Clear (POC) function
–– renders library power supply sequence agnostic
• Flexible pad frame design allowing user to select various options for supply cell placement, signal:power:ground ratios, and
number of signal cells

Figure 2: Synopsys DesignWare DDR4 multiPHY eye diagram

(DDR4, 2400Mbps, TSMC 28HPM)

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DDR4 multiPHY IP Deliverables
• Executable .run installation file which includes GDSII, LEF Files, LVS Netlists, .lib/.db Timing Models, Verilog Model, DRC/LVS Log
Files, I/O IBIS Model, I/O HSPICE Netlist, Parameterized Verilog top-level PHY netlist files, Sample Verification Environment, PHY
Data Book, Physical Implementation Guide, App Notes, Verification Guide, Installation Guide, Implementation Checklist
• The PHY Utility Block includes Verilog Code, Synthesis/STA constraints and scripts, Sample Verification Environment, Data Book
• DDR PHY Compiler

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP
portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP,
embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs,
Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys’
extensive investment in IP quality, comprehensive technical support and robust IP development methodology enable
designers to reduce integration risk and accelerate time-to-market.

For more information on DesignWare IP, visit synopsys.com/designware .

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10/18/18.CS12183_DW_DDR4_multiPHY_DS.