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iso7740-q1

The ISO774x-Q1 series consists of automotive-grade, high-speed, reinforced quad-channel digital isolators with isolation ratings up to 5700VRMS and a data rate of 100Mbps. These devices are AEC-Q100 qualified, feature low power consumption, and are designed for applications in hybrid and electric vehicles, including battery management systems and traction inverters. They also provide robust electromagnetic compatibility and safety certifications, making them suitable for safety-critical applications.

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iso7740-q1

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ISO7740-Q1, ISO7741-Q1, ISO7742-Q1

SLLSEU0G – NOVEMBER 2016 – REVISED OCTOBER 2024

ISO774x-Q1 Automotive, High-Speed, Reinforced Quad-Channel Digital Isolators

1 Features UL 1577. This family of devices has reinforced
insulation ratings according to VDE, CSA, TUV and
• Qualified for automotive applications
CQC.
• AEC-Q100 qualified with the following results:
– Device temperature Grade 1: –40°C to 125°C The ISO774x-Q1 devices provide high
ambient operating temperature electromagnetic immunity and low emissions at
• Functional Safety-Capable low power consumption, while isolating CMOS or
– Documentation available to aid functional safety LVCMOS digital I/Os. Each isolation channel has a
system design: ISO7740-Q1, ISO7741-Q1, logic input and output buffer separated by a double
ISO7742-Q1 capacitive silicon dioxide (SiO2) insulation barrier.
• 100Mbps data rate These devices come with enable pins which can be
• Robust isolation barrier: used to put the respective outputs in high impedance
– >30-year projected lifetime at 1500VRMS for multi-controller driving applications and to reduce
working voltage power consumption. The ISO7740-Q1 device has all
– Up to 5700VRMS isolation rating four channels in the same direction, the ISO7741-Q1
– Up to 12.8kV surge capability device has three forward and one reverse-direction
– ±100kV/μs typical CMTI channels, and the ISO7742-Q1 device has two
• Wide supply range: 2.25V to 5.5V forward and two reverse-direction channels. If the
• 2.25V to 5.5V level translation input power or signal is lost, default output is high
• Default output high (ISO774x ) and low for devices without suffix F and low for devices with
(ISO774xF) options suffix F. See the Device Functional Modes section for
• Low power consumption, typical 1.5mA per further details.
channel at 1Mbps Package Information
• Low propagation delay: 10.7ns typical PART NUMBER(1) PACKAGE PACKAGE SIZE(2)
(5V Supplies) ISO7741-Q1 DWW (SOIC, 16) 10.30mm × 14.0mm
• Robust electromagnetic compatibility (EMC) ISO7740-Q1 DW (SOIC, 16) 10.30mm × 7.50mm
– System-level ESD, EFT, and surge immunity ISO7741-Q1
DBQ (SSOP, 16) 4.90mm × 3.90mm
ISO7742-Q1
– ±8kV IEC 61000-4-2 contact discharge
protection across isolation barrier (1) For all available packages, see the orderable addendum at
– Low emissions the end of the data sheet.
• Extra-wide SOIC (DWW-16), wide-SOIC (DW-16) (2) The package size (length × width) is a nominal value and
includes pins, where applicable.
and QSOP (DBQ-16) package options
• Safety-related certifications:
VCCI VCCO
– DIN EN IEC 60747-17 (VDE 0884-17) Series Isolation
– UL 1577 component recognition program INx
Capacitors
OUTx
– IEC 61010-1, IEC 62368-1, IEC 60601-1, and
ENx
GB 4943.1 certifications
GNDI GNDO
Copyright © 2016, Texas Instruments Incorporated

2 Applications
VCCI=Input supply, VCCO=Output supply
• Hybrid, electric and powertrain system (EV/HEV) GNDI=Input ground, GNDO=Output ground
– Battery management system (BMS)
– On-board charger Simplified Schematic
– Traction inverter
– DC/DC converter
– Inverter and motor control
3 Description
The ISO774x-Q1 automotive devices are high-
performance, quad-channel digital isolators with
5700VRMS (DWW package), 5000VRMS (DW package)
and 3000VRMS (DBQ package) isolation ratings per

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
SLLSEU0G – NOVEMBER 2016 – REVISED OCTOBER 2024 www.ti.com

Table of Contents
1 Features............................................................................1 5.19 Typical Characteristics............................................ 22
2 Applications..................................................................... 1 6 Parameter Measurement Information.......................... 24
3 Description.......................................................................1 7 Detailed Description......................................................26
4 Pin Configuration and Functions...................................2 7.1 Overview................................................................... 26
5 Specifications.................................................................. 5 7.2 Functional Block Diagram......................................... 26
5.1 Absolute Maximum Ratings........................................ 5 7.3 Feature Description...................................................27
5.2 ESD Ratings............................................................... 5 7.4 Device Functional Modes..........................................28
5.3 Recommended Operating Conditions.........................6 8 Application and Implementation.................................. 30
5.4 Thermal Information....................................................7 8.1 Application Information............................................. 30
5.5 Power Ratings.............................................................7 8.2 Typical Application.................................................... 30
5.6 Insulation Specifications............................................. 8 8.3 Power Supply Recommendations.............................33
5.7 Safety-Related Certifications.................................... 10 8.4 Layout....................................................................... 34
5.8 Safety Limiting Values...............................................10 9 Device and Documentation Support............................35
5.9 Electrical Characteristics—5-V Supply..................... 12 9.1 Documentation Support............................................ 35
5.10 Supply Current Characteristics—5-V Supply.......... 13 9.2 Related Links............................................................ 35
5.11 Electrical Characteristics—3.3-V Supply.................14 9.3 Receiving Notification of Documentation Updates....35
5.12 Supply Current Characteristics—3.3-V Supply....... 15 9.4 Support Resources................................................... 35
5.13 Electrical Characteristics—2.5-V Supply ............... 16 9.5 Trademarks............................................................... 35
5.14 Supply Current Characteristics—2.5-V Supply....... 17 9.6 Electrostatic Discharge Caution................................35
5.15 Switching Characteristics—5-V Supply...................18 9.7 Glossary....................................................................35
5.16 Switching Characteristics—3.3-V Supply................19 10 Revision History.......................................................... 36
5.17 Switching Characteristics—2.5-V Supply................20 11 Mechanical, Packaging, and Orderable
5.18 Insulation Characteristics Curves........................... 21 Information.................................................................... 37

4 Pin Configuration and Functions

VCC1 1 16 VCC2

GND1 2 15 GND2

INA 3 14 OUTA
ISOLATION

INB 4 13 OUTB

INC 5 12 OUTC

IND 6 11 OUTD

NC 7 10 EN2

GND1 8 9 GND2

Figure 4-1. ISO7740-Q1 DW and DBQ Packages 16-Pin SOIC-WB and QSOP Top View

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VCC1 1 16 VCC2

GND1 2 15 GND2

INA 3 14 OUTA

ISOLATION
INB 4 13 OUTB

INC 5 12 OUTC

OUTD 6 11 IND

EN1 7 10 EN2

GND1 8 9 GND2

Figure 4-2. ISO7741-Q1 DWW, DW and DBQ Packages 16-Pin SOIC-Extra-WB, SOIC-WB and QSOP Top
View

VCC1 1 16 VCC2

GND1 2 15 GND2

INA 3 14 OUTA
ISOLATION

INB 4 13 OUTB

OUTC 5 12 INC

OUTD 6 11 IND

EN1 7 10 EN2

GND1 8 9 GND2

Figure 4-3. ISO7742-Q1 DW and DBQ Packages 16-Pin SOIC-WB and QSOP Top View

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Table 4-1. Pin Functions

PIN
Type(1) DESCRIPTION
NAME ISO7740-Q1 ISO7741-Q1 ISO7742-Q1
Output enable 1. Output pins on side 1 are enabled when EN1 is high
EN1 — 7 7 I
or open and in high-impedance state when EN1 is low.
Output enable 2. Output pins on side 2 are enabled when EN2 is high
EN2 10 10 10 I
or open and in high-impedance state when EN2 is low.
2 2 2
GND1 — Ground connection for VCC1
8 8 8
9 9 9
GND2 — Ground connection for VCC2
15 15 15
INA 3 3 3 I Input, channel A
INB 4 4 4 I Input, channel B
INC 5 5 12 I Input, channel C
IND 6 11 11 I Input, channel D
NC 7 — — — Not connected
OUTA 14 14 14 O Output, channel A
OUTB 13 13 13 O Output, channel B
OUTC 12 12 5 O Output, channel C
OUTD 11 6 6 O Output, channel D
VCC1 1 1 1 — Power supply, side 1
VCC2 16 16 16 — Power supply, side 2

(1) I = Input; O = Output

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5 Specifications
5.1 Absolute Maximum Ratings
See(1)
MIN MAX UNIT
VCC1, VCC2 Supply voltage (2) -0.5 6 V
V Voltage at INx, OUTx, ENx -0.5 VCCX + 0.5 (3) V
IO Output current -15 15 mA
TJ Junction temperature 150 °C
Tstg Storage temperature -65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
(3) Maximum voltage must not exceed 6 V.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC
±6000 V
Q100-002 HBM ESD Classification Level 3A (1)
Charged-device model (CDM), per AEC Q100-011 V
V(ESD) Electrostatic discharge ±1500 V
CDM ESD Classification Level C6
Contact discharge per IEC 61000-4-2; Isolation
±8000 V
barrier withstand test (2) (3)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(3) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.

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5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC1, VCC2 Supply Voltage 2.25 5.5 V
VCC(UVLO+) UVLO threshold when supply voltage is rising 2 2.25 V
VCC(UVLO-) UVLO threshold when supply voltage is falling 1.7 1.8 V
VHYS(UVLO) Supply voltage UVLO hysteresis 100 200 mV
VCCO = 5 V (1) -4
IOH High level output current VCCO = 3.3 V -2 mA
VCCO = 2.5 V -1
VCCO = 5 V 4
IOL Low level output current VCCO = 3.3 V 2 mA
VCCO = 2.5 V 1
VIH High level Input voltage 0.7 x VCCI (1) VCCI V
VIL Low level Input voltage 0 0.3 x VCCI V
DR Data Rate(2) 0 100 Mbps
TA Ambient temperature -40 25 125 °C

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

(2) 100 Mbps is the maximum specified data rate, although higher data rates are possible.

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5.4 Thermal Information

ISO774x-Q1
THERMAL METRIC(1) DWW (SOIC) DW (SOIC) DBQ (QSOP) UNIT
16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 58.3 83.4 109 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 21.4 46 54.4 °C/W
RθJB Junction-to-board thermal resistance 30.5 48 51.9 °C/W
ψJT Junction-to-top characterization parameter 7.1 19.1 14.2 °C/W
ψJB Junction-to-board characterization parameter 29.8 47.5 51.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W

(1) For more information about traditional and new thermal metrics, see theSemiconductor and IC Package Thermal Metrics application
note.

5.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7740-Q1
PD Maximum power dissipation (both sides) 210 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
PD1 Maximum power dissipation (side-1) 15 pF, Input a 50-MHz 50% duty cycle 45 mW
square wave
PD2 Maximum power dissipation (side-2) 165 mW
ISO7741-Q1
PD Maximum power dissipation (both sides) 210 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
PD1 Maximum power dissipation (side-1) 15 pF, Input a 50-MHz 50% duty cycle 75 mW
square wave
PD2 Maximum power dissipation (side-2) 135 mW
ISO7742-Q1
PD Maximum power dissipation (both sides) 210 mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
PD1 Maximum power dissipation (side-1) 15 pF, Input a 50-MHz 50% duty cycle 105 mW
square wave
PD2 Maximum power dissipation (side-2) 105 mW

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5.6 Insulation Specifications

VALUE
PARAMETER TEST CONDITIONS UNIT
DWW-16 DW-16 DBQ-16
CLR External clearance(1) Shortest terminal-to-terminal distance through air >14.5 >8 >3.7 mm
Shortest terminal-to-terminal distance across the
CPG External creepage(1) >14.5 >8 >3.7 mm
package surface
Distance through the
DTI Minimum internal gap (internal clearance) >21 >17 >17 μm
insulation
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >600 >600 >600 V
Material group According to IEC 60664-1 I I I
Rated mains voltage ≤ 300 VRMS I-IV I-IV I-III
Overvoltage category per IEC
Rated mains voltage ≤ 600 VRMS I-IV I-IV n/a
60664-1
Rated mains voltage ≤ 1000 VRMS I-IV I-III n/a
DIN EN IEC 60747-17 (VDE 0884-17) (2)

Maximum repetitive peak

VIORM AC voltage (bipolar) 2828 2121 566 VPK
isolation voltage
AC voltage; Time dependent dielectric breakdown
Maximum working isolation 2000 1500 400 VRMS
VIOWM (TDDB) Test; See Section 8.2.3.1
voltage
DC voltage 2828 2121 566 VDC
VTEST = VIOTM,
Maximum transient isolation t = 60 s (qualification);
VIOTM 8000 8000 4242 VPK
voltage VTEST = 1.2 x VIOTM,
t= 1 s (100% production)
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-μs waveform per IEC 62368-1 9600 8000 4000 VPK
Maximum surge isolation VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test),
VIOSM 12800 12800 10000 VPK
voltage(4) 1.2/50-μs waveform per IEC 62368-1
Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; ≤5 ≤5 ≤5
Vpd(m) = 1.2 x VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; ≤5 ≤5 ≤5
qpd Apparent charge(5) Vpd(m) = 1.6 x VIORM, tm = 10 s pC
Method b: At routine test (100% production) and
preconditioning (type test);
Vini = 1.2 x VIOTM, tini = 1 s; ≤5 ≤5 ≤5
Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)
Barrier capacitance, input to
CIO VIO = 0.4 x sin (2πft), f = 1 MHz ≅1 ≅1 ≅1 pF
output(6)
VIO = 500 V, TA = 25°C >1012 >1012 >1012
RIO Isolation resistance(6) VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 >1011 >1011 Ω
VIO = 500 V at TS = 150°C >109 >109 >109
Pollution degree 2 2 2
Climatic category 55/125/21 55/125/21 55/125/21
UL 1577
Maximum withstanding VTEST = VISO , t = 60 s (qualification),
VISO 5700 5000 3000 VRMS
isolation voltage VTEST = 1.2 x VISO , t = 1 s (100% production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.

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(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-terminal device.

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5.7 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to DIN Certified according to
Certified according to IEC Certified according to GB Certified according to EN
EN IEC 60747-17 (VDE UL 1577 Component
62368-1 and IEC 60601-1 4943.1 61010-1 and EN 62368-1
0884-17) Recognition Program
5700 VRMS (DWW-16),
5000 VRMS (DW-16) and
Maximum transient Reinforced insulation per
DWW-16: Reinforced 3000 VRMS (DBQ-16)
isolation voltage, 8000 CSA 62368-1 and IEC
Insulation, Altitude ≤ 5000 Reinforced insulation per
VPK (DWW-16, DW-16, 62368-1, 1450 VRMS
m, Tropical Climate, 1450 EN 61010-1 up to working
Reinforced) and 4242 (DWW-16), 600 VRMS
VRMS maximum working voltage of 1000 VRMS
VPK (DBQ-16); Maximum (DW-16) and 370 VRMS
DWW-16: Single voltage; (DWW-16), 600 VRMS
repetitive peak isolation (DBQ-16) max working
Protection, 5700 VRMS; DW-16: Reinforced (DW-16) and 300 VRMS
voltage, 2828 VPK voltage (pollution degree
DW-16: Single protection, Insulation, Altitude ≤ 5000 (DBQ-16);
(DWW-16, Reinforced), 2, material group I);
5000 VRMS; m, Tropical Climate, 700 5700 VRMS (DWW-16),
2121 VPK (DW-16, 2 MOPP (Means of Patient
DBQ-16: Single protection, VRMS maximum working 5000 VRMS (DW-16) and
Reinforced) and 566 Protection) per CSA
3000 VRMS voltage; 3000 VRMS (DBQ-16)
VPK (DBQ-16); Maximum 60601-1 and IEC 60601-1,
DBQ-16: Basic Insulation, Reinforced insulation per
surge isolation voltage, 400 VRMS (DWW-16) and
Altitude ≤ 5000 m, Tropical EN 62368-1 up to working
12800 VPK (DWW-16, 250 VRMS (DW-16) max
Climate, 400 VRMS voltage of 1450 VRMS
DW-16, Reinforced) and working voltage
maximum working voltage (DWW-16), 600 VRMS
10000 VPK (DBQ-16)
(DW-16) and 370 VRMS
(DBQ-16)
Certificate numbers:
Reinforced certificate: CQC15001121716
Master contract number:
40040142 File number: E181974 (DWx-16) Client ID number: 77311
220991
CQC18001199097
(DBQ-16)

5.8 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DWW-16 PACKAGE
RθJA = 58.3 °C/W, VI = 5.5 V, TJ = 150°C,
390 mA
TA = 25°C, see Figure 5-1
RθJA = 58.3 °C/W, VI = 3.6 V, TJ = 150°C,
IS Safety input, output, or supply current 596 mA
TA = 25°C, see Figure 5-1
RθJA = 58.3 °C/W, VI = 2.75 V, TJ =
780 mA
150°C, TA = 25°C, see Figure 5-1
RθJA = 58.3 °C/W, TJ = 150°C, TA = 25°C,
PS Safety input, output, or total power 2144 mW
see Figure 5-4
TS Maximum safety temperature 150 °C
DW-16 PACKAGE
RθJA =83.4°C/W, VI = 5.5 V, TJ = 150°C,
273
TA = 25°C, see Figure 5-2
RθJA = 83.4°C/W, VI = 3.6 V, TJ = 150°C,
IS Safety input, output, or supply current 416 mA
TA = 25°C, see Figure 5-2
RθJA = 83.4°C/W, VI = 2.75 V, TJ = 150°C,
545
TA = 25°C, see Figure 5-2
RθJA = 83.4°C/W, TJ = 150°C, TA = 25°C,
PS Safety input, output, or total power 1499 mW
see Figure 5-5
TS Maximum safety temperature 150 °C
DBQ-16 PACKAGE

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(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in Section 5.4 is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.

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5.9 Electrical Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -4 mA; See Figure 6-1 VCCO - 0.4 (1) 4.8 V
VOL Low-level output voltage IOL = 4 mA; See Figure 6-1 0.2 0.4 V
VIT+(IN) Rising input switching threshold 0.6 x VCCI 0.7 x VCCI V
VIT-(IN) Falling input switching threshold 0.3 x VCCI 0.4 x VCCI V
VI(HYS) Input threshold voltage hysteresis 0.1 x VCCI 0.2 x VCCI V
IIH High-level input current VIH = VCCI (1) at INx 10 µA
IIL Low-level input current VIL = 0 V at INx -10 µA
IIH High-level input current VIH = VCCI (1) at ENx 20 μA
IIL Low-level input current VIL = 0 V at ENx -20 μA
VI = VCCI or 0 V, VCM = 1200 V;
CMTI Common mode transient immunity 85 100 kV/μs
See Figure 6-4
VI = VCC/ 2 + 0.4×sin(2πft), f = 1
CI Input Capacitance (2) 2 pF
MHz, VCC = 5 V

(1) VCCI = Input-side VCC; VCCO = Output-side VCC

(2) Measured from input pin to same side ground.

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5.10 Supply Current Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO7740-Q1

EN2 = 0 V; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.3

VI = 0 V (ISO7740-Q1 with F suffix) ICC2 0.3 0.8
Supply current - Disable
EN2 = 0 V; VI = 0 V(1)(ISO7740-Q1); ICC1 5.5 7.8
VI = VCC1 (ISO7740-Q1 with F suffix) ICC2 0.3 0.8

EN2 = VCC2;; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.3

VI = 0 V (ISO7740-Q1 with F suffix) ICC2 2 3.6
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7740-Q1); ICC1 5.5 7.8
mA
VI = VCC1 (ISO7740-Q1 with F suffix) ICC2 2.2 3.9
ICC1 3.3 4.7
1 Mbps
ICC2 2.3 4

All channels switching with square ICC1 3.4 4.9

Supply current - AC signal 10 Mbps
wave clock input; CL = 15 pF ICC2 4.2 6.4
ICC1 3.8 6.6
100 Mbps
ICC2 22.7 29.5
ISO7741-Q1

EN1 = EN2 = 0 V; VI = VCCI (ISO7741-Q1); ICC1 1 2.2

VI = 0 V (ISO7741-Q1 with F suffix) ICC2 0.8 1.6
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1); ICC1 4.3 6.3
VI = VCCI (ISO7741-Q1 with F suffix) ICC2 1.8 2.8

EN1 = EN2 = VCCI; VI = VCCI (1)(ISO7741-Q1); ICC1 1.5 2.9

VI = 0 V (ISO7741-Q1 with F suffix) ICC2 2 3.7
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1); ICC1 4.8 6.8
mA
VI = VCCI (ISO7741-Q1 with F suffix) ICC2 3.2 5.2
ICC1 3.2 4.8
1 Mbps
ICC2 2.8 4.6

(1) VCCI = Input-side VCC

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5.11 Electrical Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -2mA; See Figure 6-1 VCCO - 0.3 (1) 3.2 V
VOL Low-level output voltage IOL = 2mA; See Figure 6-1 0.1 0.3 V
VIT+(IN) Rising input switching threshold 0.6 x VCCI 0.7 x VCCI (1) V
VIT-(IN) Falling input switching threshold 0.3 x VCCI 0.4 x VCCI V
Input threshold voltage
VI(HYS) 0.1 x VCCI 0.2 x VCCI V
hysteresis
IIH High-level input current VIH = VCCI (1) at INx 10 µA
IIL Low-level input current VIL = 0 V at INx -10 µA
IIH High-level input current VIH = VCCI (1) at ENx 30 μA
IIL Low-level input current VIL = 0 V at ENx -30 μA
Common mode transient VI = VCCI or 0 V, VCM = 1200
CMTI 85 100 kV/μs
immunity V; See Figure 6-4

(1) VCCI = Input-side VCC; VCCO = Output-side VCC

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5.12 Supply Current Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO7740-Q1

EN2 = 0 V; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.3

VI = 0 V (ISO7740-Q1 with F suffix) ICC2 0.3 0.7
Supply current - Disable
EN2 = 0 V; VI = 0 V(1)(ISO7740-Q1); ICC1 5.5 7.8
VI = VCC1 (ISO7740-Q1 with F suffix) ICC2 0.3 0.7

EN2 = VCC2; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.2

VI = 0 V (ISO7740-Q1 with F suffix) ICC2 1.9 3.6
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7740-Q1); ICC1 5.5 7.8
mA
VI = VCC1 (ISO7740-Q1 with F suffix) ICC2 2.2 3.9
ICC1 3.3 4.7
1 Mbps
ICC2 2.2 3.9

All channels switching with square ICC1 3.4 4.7

Supply current - AC signal 10 Mbps
wave clock input; CL = 15 pF ICC2 3.6 5.6
ICC1 3.3 5.7
100 Mbps
ICC2 17 22.3
ISO7741-Q1

EN1 = EN2 = 0 V; VI = VCCI (ISO7741-Q1); ICC1 1 2.1

VI = 0 V (ISO7741-Q1with F suffix) ICC2 0.8 1.5
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1); ICC1 4.3 6.3
VI = VCCI (ISO7741-Q1 with F suffix) ICC2 1.9 2.7

EN1 = EN2 = VCCI; VI = VCCI (1)(ISO7741-Q1); ICC1 1.5 2.8

VI = 0 V (ISO7741-Q1 with F suffix) ICC2 2 3.7
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1); ICC1 4.8 6.8
mA
VI = VCCI (ISO7741-Q1 with F suffix) ICC2 3.2 5.1
ICC1 3.2 4.7
1 Mbps
ICC2 2.7 4.5

(1) VCCI = Input-side VCC

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5.13 Electrical Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -1mA; See Figure 6-1 VCCO - 0.2(1) 2.45 V
VOL Low-level output voltage IOL = 1mA; See Figure 6-1 0.05 0.2 V
VIT+(IN) Rising input switching threshold 0.6 x VCCI 0.7 x VCCI V
VIT-(IN) Falling input switching threshold 0.3 x VCCI 0.4 x VCCI V
Input threshold voltage
VI(HYS) 0.1 x VCCI 0.2 x VCCI V
hysteresis
IIH High-level input current VIH = VCCI (1) at INx 10 µA
IIL Low-level input current VIL = 0 V at INx -10 µA
IIH High-level input current VIH = VCCI (1) at ENx 30 μA
IIL Low-level input current VIL = 0 V at ENx -30 μA
Common mode transient VI = VCCI or 0 V, VCM = 1200
CMTI 85 100 kV/μs
immunity V; See Figure 6-4

(1) VCCI = Input-side VCC; VCCO = Output-side VCC

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5.14 Supply Current Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO7740-Q1

EN2 = 0 V; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.2

VI = 0 V (ISO7740-Q1 with F suffix) ICC2 0.3 0.7
Supply current - Disable
EN2 = 0 V; VI = 0 V(1)(ISO7740-Q1); ICC1 5.5 7.8
VI = VCC1 (ISO7740-Q1 with F suffix) ICC2 0.3 0.7

EN2 = VCC2; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.2

VI = 0 V (ISO7740-Q1 with F suffix) ICC2 1.9 3.6
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO7740-Q1); ICC1 5.4 7.8
mA
VI = VCC1 (ISO7740-Q1 with F suffix) ICC2 2.2 3.9
ICC1 3.3 4.7
1 Mbps
ICC2 2.2 3.9

All channels switching with square ICC1 3.4 4.8

Supply current - AC signal 10 Mbps
wave clock input; CL = 15 pF ICC2 3.2 5.1
ICC1 3.2 5.5
100 Mbps
ICC2 13 17.7
ISO7741-Q1

EN1 = EN2 = 0 V; VI = VCCI (ISO7741-Q1); ICC1 1 2.2

VI = 0 V (ISO7741-Q1 with F suffix) ICC2 0.8 2.8
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1); ICC1 4.3 6.3
VI = VCCI (ISO7741-Q1 with F suffix) ICC2 1.8 2.8

EN1 = EN2 = VCCI; VI = VCCI (1)(ISO7741-Q1); ICC1 1.4 2.9

VI = 0 V (ISO7741-Q1 with F suffix) ICC2 2 3.9
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1); ICC1 4.7 6.8
mA
VI = VCCI (ISO7741-Q1 with F suffix) ICC2 3.2 5.21
ICC1 3.1 4.8
1 Mbps
ICC2 2.7 4.7

(1) VCCI = Input-side VCC

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5.15 Switching Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 6 10.7 17 ns
See Figure 6-1
PWD Pulse width distortion(1) |tPHL – tPLH| 0 5.9 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 4 ns
tsk(pp) Part-to-part skew time(3) 4.4 ns
tr Output signal rise time 2.4 3.9 ns
See Figure 6-1
tf Output signal fall time 2.4 3.9 ns
tPHZ Disable propagation delay, high-to-high impedance output 9 22 ns
tPLZ Disable propagation delay, low-to-high impedance output 9 20 ns
Enable propagation delay, high impedance-to-high output for
7 20 ns
ISO774x
tPZH
Enable propagation delay, high impedance-to-high output for See Figure 6-2
3 8.5 μs
ISO774x with F suffix
Enable propagation delay, high impedance-to-low output for
3 8.5 μs
ISO774x
tPZL
Enable propagation delay, high impedance-to-low output for
7 20 ns
ISO774x with F suffix
Measured from the time VCC goes
tDO Default output delay time from input power loss 0.1 0.3 μs
below 1.7V. See Figure 6-4
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.8 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

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5.16 Switching Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 6 11 18.5 ns
See Figure 6-1
PWD Pulse width distortion(1) |tPHL – tPLH| 0.1 5.9 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 4.4 ns
tsk(pp) Part-to-part skew time(3) 5 ns
tr Output signal rise time 1.3 3 ns
See Figure 6-1
tf Output signal fall time 1.3 3 ns
tPHZ Disable propagation delay, high-to-high impedance output 17 31 ns
tPLZ Disable propagation delay, low-to-high impedance output 17 30 ns
Enable propagation delay, high impedance-to-high output for
17 30 ns
ISO774x
tPZH
Enable propagation delay, high impedance-to-high output for See Figure 6-2
3.2 8.5 μs
ISO774x with F suffix
Enable propagation delay, high impedance-to-low output for
3.2 8.5 μs
ISO774x
tPZL
Enable propagation delay, high impedance-to-low output for
17 30 ns
ISO774x with F suffix
Measured from the time VCC goes
tDO Default output delay time from input power loss 0.1 0.3 μs
below 1.7V. See Figure 6-4
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.9 ns

(1) Also known as pulse skew.

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5.17 Switching Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 7.5 12 21 ns
See Figure 6-1
PWD Pulse width distortion(1) |tPHL – tPLH| 0.2 5.9 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 4.4 ns
tsk(pp) Part-to-part skew time(3) 5.3 ns
tr Output signal rise time 1 3.5 ns
See Figure 6-1
tf Output signal fall time 1 3.5 ns
tPHZ Disable propagation delay, high-to-high impedance output 22 41 ns
tPLZ Disable propagation delay, low-to-high impedance output 22 40 ns
Enable propagation delay, high impedance-to-high output for
18 40 ns
ISO774x
tPZH
Enable propagation delay, high impedance-to-high output for See Figure 6-2
3.3 8.5 μs
ISO774x with F suffix
Enable propagation delay, high impedance-to-low output for
3.3 8.5 μs
ISO774x
tPZL
Enable propagation delay, high impedance-to-low output for
18 40 ns
ISO774x with F suffix
Measured from the time VCC goes
tDO Default output delay time from input power loss 0.1 0.3 μs
below 1.7V. See Figure 6-4
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.7 ns

(1) Also known as pulse skew.

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5.18 Insulation Characteristics Curves

800 600
VCC1 = VCC2 = 2.75 V VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V 500 VCC1 = VCC2 = 5.5 V
Safety Limiting Current (mA)

Safety Limiting Current (mA)

600
400

400 300

200
200
100

0 0
0 50 100 150 200 0 50 100 150 200
Ambient Temperature (oC) D017 Ambient Temperature (qC) D001

Figure 5-1. Thermal Derating Curve for Safety Figure 5-2. Thermal Derating Curve for Safety
Limiting Current for DWW-16 Package Limiting Current for DW-16 Package
450 2250
VCC1 = VCC2 = 2.75 V
400 VCC1 = VCC2 = 3.6 V 2000
VCC1 = VCC2 = 5.5 V Safety Limiting Power (mW)
Safety Limiting Current (mA)

350 1750

300 1500

250 1250

200 1000

150 750

100 500

50 250

0 0
0 50 100 150 200 0 20 40 60 80 100 120 140 160
Ambient Temperature (qC) Ambient Temperature (oC) D018
D002

Figure 5-3. Thermal Derating Curve for Safety Figure 5-4. Thermal Derating Curve for Safety
Limiting Current for DBQ-16 Package Limiting Power for DWW-16 Package
1600 1400

1400 1200
Safety Limiting Power (mW)

Safety Limiting Power (mW)

1200
1000
1000
800
800
600
600
400
400

200 200

0 0
0 50 100 150 200 0 50 100 150 200
Ambient Temperature (qC) D003
Ambient Temperature (qC) D004

Figure 5-5. Thermal Derating Curve for Safety Figure 5-6. Thermal Derating Curve for Safety
Limiting Power for DW-16 Package Limiting Power for DBQ-16 Package

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5.19 Typical Characteristics

25 10
ICC1 at 2.5 V ICC1 at 2.5 V
ICC2 at 2.5 V 9 ICC2 at 2.5 V
20 ICC1 at 3.3 V 8 ICC1 at 3.3 V
ICC2 at 3.3 V ICC2 at 3.3 V
Supply Current (mA)

Supply Current (mA)

ICC1 at 5 V 7 ICC1 at 5 V
ICC2 at 5 V ICC2 at 5 V
15 6
5
10 4
3
5 2
1
0 0
0 25 50 75 100 0 25 50 75 100
Data Rate (Mbps) Data Rate (Mbps)
TA = 25°C CL = 15 pF TA = 25°C CL = No Load

Figure 5-7. ISO7740-Q1 Supply Current vs Data Figure 5-8. ISO7740-Q1 Supply Current vs Data
Rate (With 15-pF Load) Rate (With No Load)
20 10
ICC1 at 2.5 V ICC1 at 2.5 V
18 ICC2 at 2.5 V 9 ICC2 at 2.5 V
16 ICC1 at 3.3 V 8 ICC1 at 3.3 V
ICC2 at 3.3 V ICC2 at 3.3 V
Supply Current (mA)

Supply Current (mA)

14 ICC1 at 5 V 7 ICC1 at 5 V
ICC2 at 5 V ICC2 at 5 V
12 6
10 5
8 4
6 3
4 2
2 1
0 0
0 25 50 75 100 0 25 50 75 100
Data Rate (Mbps) Data Rate (Mbps)
TA = 25°C CL = 15 pF TA = 25°C CL = No Load

Figure 5-9. ISO7741-Q1 Supply Current vs Data Figure 5-10. ISO7741-Q1 Supply Current vs Data
Rate (With 15-pF Load) Rate (With No Load)

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16 10
ICC1 at 2.5 V ICC1 at 2.5 V
14 ICC2 at 2.5 V 9 ICC2 at 2.5 V
ICC1 at 3.3 V 8 ICC1 at 3.3 V
12 ICC2 at 3.3 V ICC2 at 3.3 V
Supply Current (mA)

Supply Current (mA)

ICC1 at 5 V 7 ICC1 at 5 V
10 ICC2 at 5 V ICC2 at 5 V
6
8 5

6 4
3
4
2
2 1
0 0
0 25 50 75 100 0 25 50 75 100
Data Rate (Mbps) Data Rate (Mbps)
TA = 25°C CL = 15 pF TA = 25°C CL = No Load

Figure 5-11. ISO7742-Q1 Supply Current vs Data Figure 5-12. ISO7742-Q1 Supply Current vs Data
Rate (With 15-pF Load) Rate (With No Load)
6 0.9

0.8
5
High-Level Output Voltage (V)

Low-Level Output Voltage (V) 0.7

4 0.6

0.5
3
0.4

2 0.3

0.2
1 VCC at 2.5 V VCC at 2.5 V
VCC at 3.3 V 0.1 VCC at 3.3 V
VCC at 5 V VCC at 5 V
0 0
-15 -10 -5 0 0 5 10 15
High-Level Output Current (mA) Low-Level Output Current (mA) D012
D011

TA = 25°C TA = 25°C

Figure 5-13. High-Level Output Voltage vs High- Figure 5-14. Low-Level Output Voltage vs Low-
level Output Current Level Output Current
2.1 14

2.05
Power Supply UVLO Threshold (V)

13
Propagation Delay Time (ns)

1.95 12

1.9
11
1.85

1.8 10

1.75 VCC1 Rising

VCC2 Rising 9 tPHL at 2.5 V tPLH at 3.3 V
1.7 VCC1 Falling tPLH at 2.5 V tPHL at 5 V
VCC2 Falling tPHL at 3.3 V tPLH at 5 V
1.65 8
-55 -5 45 95 125 -55 -25 5 35 65 95 125
Free-Air Te mperature (C) Free-Air Temperature (qC) D014

Figure 5-15. Power Supply Undervoltage Threshold Figure 5-16. Propagation Delay Time vs Free-Air
vs Free-Air Temperature Temperature

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6 Parameter Measurement Information

VCCI

Isolation Barrier
VI 50% 50%
IN OUT
0V

Input tPLH tPHL

Generator CL
VI 50 VO
(See Note A) See Note B VOH
50% 90% 50%
VO
10%
VOL
tr tf

Copyright © 2016, Texas Instruments Incorporated

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50kHz, 50% duty cycle, tr ≤ 3ns, tf ≤ 3ns, ZO =
50Ω. At the input, 50Ω resistor is required to terminate Input Generator signal. The 50Ω resistor is not needed in actual application.
B. CL = 15pF and includes instrumentation and fixture capacitance within ±20%.

Figure 6-1. Switching Characteristics Test Circuit and Voltage Waveforms

VCCO

VCC
RL = 1 k ±1%
Isolation Barrier

VCC / 2
VCC / 2
VI
IN OUT
0V VO 0V
tPZL tPLZ
VOH
EN 0.5 V
VO 50%
CL
VOL
See Note B
Input
Generator VI
(See Note A) 50
Isolation Barrier

VCC
VO
IN OUT
3V VCC / 2 VCC / 2
VI
0V
EN tPZH
RL = 1 k ±1% VOH
CL
See Note B 50%
Input VO 0.5 V
Generator VI
50 tPHZ 0V
(See Note A)

Copyright © 2016, Texas Instruments Incorporated

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10kHz, 50% duty cycle,
tr ≤ 3ns, tf ≤ 3ns, ZO = 50Ω.
B. CL = 15pF and includes instrumentation and fixture capacitance within ±20%.

Figure 6-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform

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VI See Note B

VCC VCC
VI 1.7 V

Isolation Barrier
0V
IN = 0 V (Devices without suffix F) IN OUT
VO tDO
IN = VCC (Devices with suffix F)
default high
VOH
CL
See Note A VO 50%
VOL
default low

A. CL = 15pF and includes instrumentation and fixture capacitance within ±20%.

B. Power Supply Ramp Rate = 10mV/ns

Figure 6-3. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI VCCO

C = 0.1 µF ±1% C = 0.1 µF ±1%

Pass-fail criteria:
The output must
Isolation Barrier remain stable.
IN OUT
S1
+

CL VOH or VOL
See Note A
±

GNDO
GNDI + VCM ±

A. CL = 15pF and includes instrumentation and fixture capacitance within ±20%.

Figure 6-4. Common-Mode Transient Immunity Test Circuit

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7 Detailed Description
7.1 Overview
The ISO774x-Q1 family of devices an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin
is low then the output goes to high impedance. The ISO774x-Q1 devices also incorporate advanced circuit
techniques to maximize the CMTI performance and minimize the radiated emissions due to the high frequency
carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 7-1, shows a
functional block diagram of a typical channel.
7.2 Functional Block Diagram

Transmitter Receiver
EN

OOK
Modulation
TX IN SiO2 based
TX Signal Capacitive RX Signal Envelope RX OUT
Conditioning Isolation Conditioning Detection
Barrier

Emissions
Oscillator Reduction
Techniques

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Figure 7-1. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 7-2 shows a conceptual detail of how the ON-OFF keying scheme works.

TX IN

Carrier signal through

isolation barrier

RX OUT

Figure 7-2. On-Off Keying (OOK) Based Modulation Scheme

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7.3 Feature Description

Table 7-1 provides an overview of the device features.
Table 7-1. Device Features
MAXIMUM DATA DEFAULT
PART NUMBER CHANNEL DIRECTION PACKAGE RATED ISOLATION(1)
RATE OUTPUT

4 Forward, DW-16 5000 VRMS / 8000 VPK

ISO7740-Q1 100 Mbps High
0 Reverse DBQ-16 3000 VRMS / 4242 VPK

ISO7740-Q1 with F 4 Forward, DW-16 5000 VRMS / 8000 VPK

100 Mbps Low
suffix 0 Reverse DBQ-16 3000 VRMS / 4242 VPK
DWW-16 5700 VRMS / 8000 VPK
3 Forward,
ISO7741-Q1 100 Mbps High DW-16 5000 VRMS / 8000 VPK
1 Reverse
DBQ-16 3000 VRMS / 4242 VPK
DWW-16 5700 VRMS / 8000 VPK
ISO7741-Q1 with F 3 Forward,
100 Mbps Low DW-16 5000 VRMS / 8000 VPK
suffix 1 Reverse
DBQ-16 3000 VRMS / 4242 VPK

2 Forward, DW-16 5000 VRMS / 8000 VPK

ISO7742-Q1 100 Mbps High
2 Reverse DBQ-16 3000 VRMS / 4242 VPK

ISO7742-Q1 with F 2 Forward, DW-16 5000 VRMS / 8000 VPK

100 Mbps Low
suffix 2 Reverse DBQ-16 3000 VRMS / 4242 VPK

(1) See Section 5.7 for detailed isolation ratings.

7.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO774x-
Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by providing purely differential internal
operation.

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7.4 Device Functional Modes

Table 7-2 lists the functional modes for the ISO774x-Q1 devices.
Table 7-2. Function Table
OUTPUT
INPUT OUTPUT
VCCI (1) VCCO ENABLE COMMENTS
(INx)(3) (OUTx)
(ENx)
H H or open H Normal Operation:
L H or open L A channel output assumes the logic state of the input.
PU PU
Default mode: When INx is open, the corresponding channel output
Open H or open Default goes to the default logic state. Default is High for ISO774x-Q1 and
Low for ISO774x-Q1 with F suffix.
A low value of output enable causes the outputs to be high-
X PU X L Z
impedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is High
for ISO774x-Q1 and Low for ISO774x-Q1 with F suffix.
PD PU X H or open Default When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel
output assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(2).
X PD X X Undetermined When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.

(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
(2) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.

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7.4.1 Device I/O Schematics

Input (ISO774x) Input (ISO774xF)

VCCI VCCI VCCI VCCI VCCI VCCI VCCI

1.5 MW

985 W 985 W
INx INx

1.5 MW

Output Enable
VCCO
VCCO VCCO VCCO VCCO

2 MW

~20 W 1970 W
OUTx ENx

Copyright © 2016, Texas Instruments Incorporated

Figure 7-3. Device I/O Schematics

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The ISO774x-Q1 devices are high-performance, quad-channel digital isolators. These devices come with enable
pins on each side which can be used to put the respective outputs in high impedance for multi master driving
applications and reduce power consumption. The ISO774x-Q1 devices use single-ended CMOS-logic switching
technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with
digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform
to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal
lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a
line transceiver, regardless of the interface type or standard.
8.2 Typical Application
Figure 8-1 shows the typical isolated CAN interface implementation.

3.3 V 10 F
2
Vcc 1:1.33 MBR0520L
3 1 5 ISO 3.3V
D2 IN OUT
TPS76333-Q1
SN6505x-Q1 10 F 0.1 F 10 F
3 2
EN GND
1
D1
GND GND MBR0520L
4 5
ISO Barrier

0.1 F 0.1 F
0.1 F 29,57 0.1 F
3
VDDIO VCC1 VCC2 VCC
26 1 16
CANRXA OUTC INC CANH 7
TMS320F28 5 12 4 RXDTCAN1042-Q1
035PAGQ
CANTXA INA OUTA 1
TXD CANL 6
14
25 3 GND
VSS
ISO7742-Q1 2
6,28
0.1 F
3
0.1 F 29,57 OUTD IND VCC
6 11
VDDIO 4 RXD CANH 7
26 INB OUTB TCAN1042-Q1
CANRXA 4 13 6
TMS320F28 1 TXD CANL
GND1 GND2
035PAGQ 2,8 9,15 GND
CANTXA
25 2
VSS
6,28

Copyright © 2020, Texas Instruments Incorporated

Figure 8-1. Typical Isolated CAN Application Circuit

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8.2.1 Design Requirements

To design with these devices, use the parameters listed in Table 8-1.
Table 8-1. Design Parameters
PARAMETER VALUE
Supply voltage, VCC1 and VCC2 2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1 0.1 µF
Decoupling capacitor from VCC2 and GND2 0.1 µF

8.2.2 Detailed Design Procedure

Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO774x-Q1 family of devices only require two external bypass capacitors to operate.
2 mm maximum 2 mm maximum
from VCC1 from VCC2

0.1 µF 0.1 µF

VCC1 VCC2
1 16

GND1 GND2
2 15

INA 3 14 OUTA

INB 4 13 OUTB

INC 5 12 OUTC

OUTD 6 11 IND

EN1 EN2
7 10

GND1 GND2
8 9

Figure 8-2. Typical ISO774x-Q1 Circuit Hook-up

The DWW package provides wider creepage and clearance without the need for two isolators in series or an
extra isolated power supply, saving design cost and board space. For more details, please refer to the technical
document How to Meet the Higher Isolation Creepage & Clearance Needs in Automotive Applications.

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8.2.3 Application Curve

The following typical eye diagrams of the ISO774x-Q1 family of devices indicates low jitter and wide open eye at
the maximum data rate of 100 Mbps.

Ch4 = 1 V / div
Ch4 = 1 V / div

Time = 2.5 ns / div Time = 2.5 ns / div

Figure 8-3. Eye Diagram at 100 Mbps PRBS 216 – 1, Figure 8-4. Eye Diagram at 100 Mbps PRBS 216 – 1,
5 V and 25°C 3.3 V and 25°C
Ch4 = 500 mV / div

Time = 2.5 ns / div

Figure 8-5. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C

8.2.3.1 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 8-6 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 50% for
lifetime which translates into minimum required insulation lifetime of 30 years at a working voltage that's 20%
higher than the specified value.
Figure 8-7 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over the lifetime
of the barrier. Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of
36 years. Other factors, such as package size, pollution degree, material group, and more can further limit the
working voltage of the component. The working voltage of DW-16 package is specified up to 1500 VRMS. At
the lower working voltages, the corresponding insulation lifetime is much longer than 36 years. The insulation
withstand capability of DWW-16 package is 2000 VRMS with a corresponding lifetime of 34 years. DBQ-16
package at 400 VRMS working voltage has a much longer lifetime than both DW-16 and DWW-16 packages.

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A
Vcc 1 Vcc 2

Time Counter

DUT > 1mA

GND 1 GND 2

Oven at 150°C

Figure 8-6. Test Setup for Insulation Lifetime Measurement

1.E+12

1.E+11

1.E+10 50 %
54 Yrs
1.E+09
36 Yrs
1.E+08
Time to Fail (sec)

1.E+07 TDDB Line (<1 ppm Fail Rate)

1.E+06 VDE Safety

Margin Zone
1.E+05
Operating Zone
1.E+04

1.E+03

1.E+02 20%

1.E+01
200 1200 2200 3200 4200 5200 6200

Applied Voltage (VRMS)

Working Isolation Volatage = 1500 VRMS Protected Insulation Lifetime = 36 Years

up to 150°C Applied Voltage Frequency = 60 Hz

Figure 8-7. Insulation Lifetime Projection Data

8.3 Power Supply Recommendations

To help provide reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors must be placed as close to the supply
pins as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1 or
SN6505B-Q1 . For such applications, detailed power supply design and transformer selection recommendations
are available in SN6501-Q1 Transformer Driver for Isolated Power Supplies and SN6505x-Q1 Low-Noise 1-A
Transformer Drivers for Isolated Power Supplies data sheets .

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8.4 Layout
8.4.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 8-8). Layer stacking must
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of the
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
typically have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep the planes symmetrical. This makes the stack mechanically stable and prevents warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
8.4.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths
of up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to the lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
8.4.2 Layout Example

High-speed traces
10 mils
Ground plane
Keep this
space free FR-4
40 mils from planes, 0r ~ 4.5
traces, pads,
and vias
Power plane
10 mils
Low-speed traces
Figure 8-8. Layout Example Schematic

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9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
• Texas Instruments, TCAN1042-Q1 Automotive fault protected CAN transceiver with CAN FD data sheet
• Texas Instruments, TMS320F28035 Piccolo™ Microcontrollers data sheet
• Texas Instruments, TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
9.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
ISO7740-Q1 Click here Click here Click here Click here Click here
ISO7741-Q1 Click here Click here Click here Click here Click here
ISO7742-Q1 Click here Click here Click here Click here Click here

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
Piccolo™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (January 2024) to Revision G (October 2024) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated distance through isolation, while maintaining other insulation specifications.......................................8
• Updated the input leakage current for ENx pins throughout the electrical characteristic sections................... 12
• Updated the TDDB plot and the projected lifetime........................................................................................... 32

Changes from Revision E (July 2023) to Revision F (January 2024) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated Thermal Characteristics, Safety Limiting Values, and Thermal Derating Curves to provide more
accurate system-level thermal calculations........................................................................................................ 5
• Updated electrical and switching characteristics to match device performance.................................................5

Changes from Revision D (October 2020) to Revision E (July 2023) Page

• Changed standard name from: "DIN VDE V 0884-11:2017-01" to: "DIN EN IEC 60747-17 (VDE 0884-17)"
throughout the document....................................................................................................................................1
• Removed standard revision and year references from all standard names throughout the document.............. 1
• Added Maximum impulse voltage (VIMP) specification per DIN EN IEC 60747-17 (VDE 0884-17)....................8
• Changed test conditions and values of Maximum surge isolation voltage (VIOSM) specification per DIN EN IEC
60747-17 (VDE 0884-17)................................................................................................................................... 8
• Clarified method b test conditions of Apparent charge (qPD)..............................................................................8
• Removed references to standard IEC/EN/CSA 60950-1 throughout the document.........................................10
• Switched the labels for VCC1 falling and VCC2 rising in the graph legend of Power Supply Undervoltage
Threshold vs Free-Air Temperature .................................................................................................................22

Changes from Revision C (February 2020) to Revision D (October 2020) Page

• Added Functional Safety bullet in Section 1 ......................................................................................................1

Changes from Revision B (June 2018) to Revision C (February 2020) Page

• Made editorial and cosmetic changes throughout the document ...................................................................... 1
• Changed From: "Isolation Barrier Life: >40 Years" To: " >100-year projected lifetime at 1500 VRMS working
voltage" in Section 1 ..........................................................................................................................................1
• Added "Up to 5700 VRMS isolation rating" in Section 1 ..................................................................................... 1
• Added "Up to 12.8 kV surge capability" in Section 1 .........................................................................................1
• Added "±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier" in Section 1 .................... 1
• Changed VDE standard name From: DIN V VDE V 0884-11:2017-01 To: DIN VDE V 0884-11:2017-01
throughout the document ...................................................................................................................................1
• Deleted "All Certifications Complete except CQC Approval of DBQ-16 Package Devices" in Section 1 .......... 1
• Updated list of applications in Section 2 section................................................................................................ 1
• Updated Simplified Schematic to show two isolation capacitors in series per channel instead of a single
isolation capacitor ..............................................................................................................................................1
• Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V ..........................................................5

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• Added the following table note to Data rate specification: "100 Mbps is the maximum specified data rate,
although higher data rates are possible"............................................................................................................ 6
• Changed ISO7741-Q1 PD1 or Maximum power dissipation by side-1 from 50mW to 75 mW and PD2 or
Maximum power dissipation by side-2 from 150mW to 125 mW .......................................................................7
• Changed DW-16 package values of VIORM from 1414 VPK to 2121 VPK and and VIOWM from 1000 VRMS and
1414 VDC to 1500 VRMS and 2121 VDC ............................................................................................................. 8
• Modified test conditions of VIOWM and VIOSM .....................................................................................................8
• Updated table title to "Safety-Related Certifications" and updated certification information............................ 10
• Corrected ground symbol for 'Input (ISO774xF)' schematic in Section 7.4.1 .................................................. 29
• Updated Figure 8-1 by changing CAN transceiver From: SN65HVD231Q To: TCAN1042-Q1 and transformer
driver From: SN6501-Q1 To: SN6505x-Q1.......................................................................................................30
• Added SN6505x-Q1 reference in Section 8.3 section ..................................................................................... 33
• Added 'How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems' application
report to Section 9.1 section ............................................................................................................................35
• Added SN6505x-Q1 data sheet reference in Section 9.1 section.................................................................... 35

Changes from Revision A (May 2018) to Revision B (June 2018) Page

• Changed the isolation rating of the DBQ package from 2500 VRMS to 3000 VRMS ........................................... 1
• Moved the HBM and CDM values from the Featues section to the ESD Ratings table..................................... 5
• Changed VIOTM from 3600 VPK to 4242 VPK for the DBQ package.................................................................... 8
• Added VTEST to the conditions for the maximum transient isolation voltage parameter.....................................8
• Changed method b1 V ini condition for apparent charge..................................................................................... 8
• Changed all "plan to certify" to "Certified" and all "Certification Planned" to the proper certification number.. 10
• Changed CMTI TYP value from 75kV/μs to 100 kV/μs in all Electrical Characteristics tables.........................12
• Changed the tDO TYP value from 6μs to 0.1μs and the MAX value from 9μs to 0.3μs in all Switching
Characteristics tables....................................................................................................................................... 18
• Switched the line colors for VCC at 2.5 V and V CC at 3.3 V in Figure 5-14 ......................................................22
• Switched the labels for VCC1 falling and VCC2 rising in the graph legend of Power Supply Undervoltage
Threshold vs Free-Air Temperature .................................................................................................................22

Changes from Revision * (November 2016) to Revision A (May 2018) Page

• Updated the Safety-Related Certifications table...............................................................................................10
• Changed minimum CMTI from 40 to 85 in all Electrical Characteristics tables................................................ 12

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO7740FQDBQQ1 LIFEBUY SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7740FQ
ISO7740FQDBQRQ1 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7740FQ Samples

ISO7740FQDWQ1 LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7740FQ
ISO7740FQDWRQ1 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (ISO7740F, ISO7740 Samples
FQ)
ISO7740QDBQQ1 LIFEBUY SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7740Q
ISO7740QDBQRQ1 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7740Q Samples

ISO7740QDWQ1 LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7740Q
ISO7740QDWRQ1 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (ISO7740, ISO7740Q Samples
)
ISO7741FQDBQQ1 LIFEBUY SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7741FQ
ISO7741FQDBQRQ1 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7741FQ Samples

ISO7741FQDWQ1 LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7741FQ
ISO7741FQDWRQ1 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (ISO7741F, ISO7741 Samples
FQ)
ISO7741FQDWWQ1 LIFEBUY SOIC DWW 16 45 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7741FQ
ISO7741FQDWWRQ1 ACTIVE SOIC DWW 16 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7741FQ Samples

ISO7741QDBQQ1 LIFEBUY SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7741Q
ISO7741QDBQRQ1 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (7741, 7741Q) Samples

ISO7741QDWQ1 LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7741Q
ISO7741QDWRQ1 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (ISO7741, ISO7741Q Samples
)
ISO7741QDWWQ1 LIFEBUY SOIC DWW 16 45 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7741Q
ISO7741QDWWRQ1 ACTIVE SOIC DWW 16 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7741Q Samples

ISO7742FQDBQQ1 LIFEBUY SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7742FQ
ISO7742FQDBQRQ1 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7742FQ Samples

ISO7742FQDWQ1 LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7742FQ

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 20-Dec-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO7742FQDWRQ1 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (ISO7742F, ISO7742 Samples
FQ)
ISO7742QDBQQ1 LIFEBUY SSOP DBQ 16 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7742Q
ISO7742QDBQRQ1 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 7742Q Samples

ISO7742QDWQ1 LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7742Q
ISO7742QDWRQ1 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (ISO7742, ISO7742Q Samples
)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 20-Dec-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ISO7740-Q1, ISO7741-Q1, ISO7742-Q1 :

• Catalog : ISO7740, ISO7741, ISO7742

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Mar-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7740FQDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7740FQDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7740FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7740FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7740FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7740FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7740QDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7740QDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7740QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7740QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7740QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7741FQDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7741FQDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7741FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7741FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7741FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Mar-2025

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7741FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7741FQDWWRQ1 SOIC DWW 16 1000 330.0 24.4 18.0 10.0 3.0 20.0 24.0 Q1
ISO7741QDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7741QDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7741QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7741QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7741QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7741QDWWRQ1 SOIC DWW 16 1000 330.0 24.4 18.0 10.0 3.0 20.0 24.0 Q1
ISO7742FQDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7742FQDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7742FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7742FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7742FQDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7742QDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7742QDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7742QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7742QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7742QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7742QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Mar-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7740FQDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7740FQDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7740FQDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7740FQDWRQ1 SOIC DW 16 2000 350.0 350.0 43.0
ISO7740FQDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7740FQDWRQ1 SOIC DW 16 2000 353.0 353.0 32.0
ISO7740QDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7740QDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7740QDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7740QDWRQ1 SOIC DW 16 2000 367.0 367.0 45.0
ISO7740QDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7741FQDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7741FQDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7741FQDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7741FQDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7741FQDWRQ1 SOIC DW 16 2000 367.0 367.0 45.0
ISO7741FQDWRQ1 SOIC DW 16 2000 350.0 350.0 43.0
ISO7741FQDWWRQ1 SOIC DWW 16 1000 350.0 350.0 43.0

Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Mar-2025

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7741QDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7741QDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7741QDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7741QDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7741QDWRQ1 SOIC DW 16 2000 367.0 367.0 45.0
ISO7741QDWWRQ1 SOIC DWW 16 1000 350.0 350.0 43.0
ISO7742FQDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7742FQDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7742FQDWRQ1 SOIC DW 16 2000 356.0 356.0 35.0
ISO7742FQDWRQ1 SOIC DW 16 2000 367.0 367.0 45.0
ISO7742FQDWRQ1 SOIC DW 16 2000 350.0 350.0 43.0
ISO7742QDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7742QDBQRQ1 SSOP DBQ 16 2500 350.0 350.0 43.0
ISO7742QDWRQ1 SOIC DW 16 2000 367.0 367.0 38.0
ISO7742QDWRQ1 SOIC DW 16 2000 350.0 350.0 43.0
ISO7742QDWRQ1 SOIC DW 16 2000 367.0 367.0 38.0
ISO7742QDWRQ1 SOIC DW 16 2000 367.0 367.0 45.0

Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Mar-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ISO7740FQDBQQ1 DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7740FQDWQ1 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7740FQDWQ1 DW SOIC 16 40 507 12.83 5080 6.6
ISO7740QDBQQ1 DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7740QDWQ1 DW SOIC 16 40 507 12.83 5080 6.6
ISO7740QDWQ1 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7741FQDBQQ1 DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7741FQDWQ1 DW SOIC 16 40 507 12.83 5080 6.6
ISO7741FQDWQ1 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7741FQDWWQ1 DWW SOIC 16 45 507 20 5000 9
ISO7741QDBQQ1 DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7741QDWQ1 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7741QDWQ1 DW SOIC 16 40 507 12.83 5080 6.6
ISO7741QDWWQ1 DWW SOIC 16 45 507 20 5000 9
ISO7742FQDBQQ1 DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7742FQDWQ1 DW SOIC 16 40 507 12.83 5080 6.6
ISO7742FQDWQ1 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7742QDBQQ1 DBQ SSOP 16 75 505.46 6.76 3810 4
ISO7742QDWQ1 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO7742QDWQ1 DW SOIC 16 40 507 12.83 5080 6.6

Pack Materials-Page 5
PACKAGE OUTLINE
DWW0016A SCALE 1.000
SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE

C
17.4 SEATING PLANE
17.1
A PIN 1 ID AREA 0.1 C
14X 1.27
16
1

10.4 2X
10.2
NOTE 3 8.89

8
9
0.51
16X (2.286)
14.1 0.31
B 0.25 A B C
13.9 2.65 MAX
NOTE 4

0.28
TYP
SEE DETAIL A 0.22

(1.625)

0.25
GAGE PLANE

0.3
0 -8 1.1 0.1
0.6

DETAIL A
TYPICAL
4221501/B 10/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0,15 mm per side.
4. This dimension does not include interlead flash.

www.ti.com
EXAMPLE BOARD LAYOUT
DWW0016A SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE

16X (2) (14.25) 16X (DIM C) (DIM B)

16X (0.6) 16X (0.6)

1 1
16 16

SYMM SYMM

14X 8 9 14X 8 9
(1.27) (1.27)
(R0.05) SYMM SYMM
(R0.05)
TYP TYP
(16.25) (DIM A)

LAND PATTERN EXAMPLE LAND PATTERN EXAMPLE

STANDARD PCB CLEARANCE & CREEPAGE OPTIMIZED
SCALE:3X SCALE:3X

OPTION DIM A DIM B DIM C

01 16.375 14.5 1.875
02 16.625 15 1.625
03 16.725 15.2 1.525

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK

METAL UNDER
OPENING OPENING
SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4221501/B 10/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DWW0016A SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE

16X (2)
SYMM
1
16

16X (0.6)

(R0.05) TYP SYMM

14X (1.27) 8 9

(16.25)

SOLDER PASTE EXAMPLE

STANDARD
BASED ON 0.125 mm THICK STENCIL
SCALE:4X

(DIM B)
16X (DIM C)
SYMM
1
16

16X (0.6)

(R0.05) TYP SYMM

14X (1.27) 8 9

(DIMA)

SOLDER PASTE EXAMPLE

PCB CLEARANCE & CREEPAGE OPTIMIZED
BASED ON 0.125 mm THICK STENCIL
SCALE:4X

OPTION DIM A DIM B DIM C

01 16.375 14.5 1.875
02 16.625 15 1.625
03 16.725 15.2 1.525
4221501/B 10/2024

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

www.ti.com
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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iso7740-q1

Uploaded by

iso7740-q1

Uploaded by

ISO7740-Q1, ISO7741-Q1, ISO7742-Q1

SLLSEU0G – NOVEMBER 2016 – REVISED OCTOBER 2024

ISO774x-Q1 Automotive, High-Speed, Reinforced Quad-Channel Digital Isolators

4 Pin Configuration and Functions

2 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3

Table 4-1. Pin Functions

(1) I = Input; O = Output

4 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

5.2 ESD Ratings

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5

5.3 Recommended Operating Conditions

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

5.4 Thermal Information

5.5 Power Ratings

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7

5.6 Insulation Specifications

Maximum repetitive peak

8 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9

5.7 Safety-Related Certifications

5.8 Safety Limiting Values

10 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11

5.9 Electrical Characteristics—5-V Supply

(1) VCCI = Input-side VCC; VCCO = Output-side VCC

12 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

5.10 Supply Current Characteristics—5-V Supply

EN2 = 0 V; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.3

EN2 = VCC2;; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.3

All channels switching with square ICC1 3.4 4.9

EN1 = EN2 = 0 V; VI = VCCI (ISO7741-Q1); ICC1 1 2.2

EN1 = EN2 = VCCI; VI = VCCI (1)(ISO7741-Q1); ICC1 1.5 2.9

All channels switching with square ICC1 3.7 5.5

(1) VCCI = Input-side VCC

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13

5.11 Electrical Characteristics—3.3-V Supply

(1) VCCI = Input-side VCC; VCCO = Output-side VCC

14 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

5.12 Supply Current Characteristics—3.3-V Supply

EN2 = 0 V; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.3

EN2 = VCC2; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.2

All channels switching with square ICC1 3.4 4.7

EN1 = EN2 = 0 V; VI = VCCI (ISO7741-Q1); ICC1 1 2.1

EN1 = EN2 = VCCI; VI = VCCI (1)(ISO7741-Q1); ICC1 1.5 2.8

All channels switching with square ICC1 3.5 5.2

(1) VCCI = Input-side VCC

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15

5.13 Electrical Characteristics—2.5-V Supply

(1) VCCI = Input-side VCC; VCCO = Output-side VCC

16 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

5.14 Supply Current Characteristics—2.5-V Supply

EN2 = 0 V; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.2

EN2 = VCC2; VI = VCC1 (1)(ISO7740-Q1); ICC1 1.2 2.2

All channels switching with square ICC1 3.4 4.8

EN1 = EN2 = 0 V; VI = VCCI (ISO7741-Q1); ICC1 1 2.2

EN1 = EN2 = VCCI; VI = VCCI (1)(ISO7741-Q1); ICC1 1.4 2.9

All channels switching with square ICC1 3.4 5.2

(1) VCCI = Input-side VCC

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17

5.15 Switching Characteristics—5-V Supply

(1) Also known as pulse skew.

18 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: ISO7740-Q1 ISO7741-Q1 ISO7742-Q1

5.16 Switching Characteristics—3.3-V Supply

(1) Also known as pulse skew.

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19