Journal of Computational Electronics (2018) 17:745–755

https://doi.org/10.1007/s10825-018-1136-6

Characteristics of GaAs/GaSb tunnel field-effect transistors without

doping junctions: numerical studies
Mahdi Vadizadeh1

Published online: 26 February 2018

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Abstract
Tunneling field-effect transistor (TFET) suffers from ultra-sharp doping concentration gradients in both the source/channel
junction and drain/channel junction. Recently, the junctionless (JL) TFET device has been proposed to avoid the issue of
ultra-sharp doping concentration gradients. Employing III–V semiconductor as a drain/channel material and a group IV
semiconductor as a source material has been proposed to improve the heterojunctionless (HJL) TFET device performance.
GaAs:Ge HJL-TFET has proved more efficient than other HJL-TFET structures in providing more ON-state current, less
OFF-state current, and less subthreshold slope (SS). For the first time in this paper, GaSb as the source material and GaAs
as the drain/channel material have been proposed. This is the so-called GaAs:GaSb HJL-TFET structure. Simulation results
show that the GaAs:GaSb HJL-TFET provides improvement in both ION /IOFF ratio and SS as compared to GaAs:Ge HJL-
TFETs. We demonstrate that for a 20 nm channel length, the GaAs:GaSb HJL-TFET average SS is improved by 19% and the
point slope by 52%, as compared to those of the GaAs:Ge HJL-TFET. Numerical simulations show that the average SS and
ION /IOFF ratio of GaAs:GaSb HJL-TFET are nearly 9 mV/dec and 3E12, respectively, for a 10 nm channel length. Thus, the
GaAs:GaSb HJL-TFET holds promise for future logic transistor applications.

Keywords Average subthreshold slope · GaAS:GaSb HJL-TFET · Junctionless tunnel FET · Ultra-sharp doping concentration
gradients

1 Introduction process difficult [11]. Recently, the junctionless (JL) FET

device, which includes a single type doping at the same level
Metal oxide semiconductor field-effect transistor (MOS- in the source, drain, and channel regions, has been proposed
FET) device dimensions are aggressively scaled down to to avoid the formation of ultra-sharp source/drain doping pro-
the nanometer regime to achieve higher chip density, higher files [11–17].
speed, and lower operating power. However, short chan- Subthreshold slope (SS) is a criterion characterizing the
nel effects (SCEs) such as drain-induced barrier lower- sharpness of the switching from IOFF to ION for the FET
ing (DIBL), punch through, enhanced leakage current and devices. One of the main shortcomings in a JL-FET device,
reduced device performance have arisen as obstacles to this similar to a MOSFET, is its SS limited to a value greater than
procedure [1–4]. Various structures have been proposed to 60 mV/dec [11–17]. However, it should be noted that the
reduce the SCEs in MOSFET devices [5–10]. JL-FET sacrifices SS in order to gain simplicity in fabrica-
Modern MOSFETs in the nanometer regime have been tion and immunity from variability/scattering as mentioned in
fabricated with ultra-sharp doping concentration gradients in [18,19]. To reduce SS, the tunneling FET has been introduced,
the source/channel junction as well as drain/channel junction. in which the band-to-band tunneling (BTBT) mechanism has
Switching doping within a nanometer region from source to been employed for current flow [10,20]. TFET devices, as
the channel and drain to the channel makes the fabrication compared to SOI-MOSFETs with similar dimensions, pro-
vide less SS, and less OFF-state current, but less ON-state
B Mahdi Vadizadeh current [21–23]. Use of a germanium channel [24], strained
[email protected] silicon [25], and so on, has been proposed to eliminate the
shortcoming of a low ON-state current in TFET devices. The
1 Department of Electrical Engineering, Abhar Branch, Islamic TFET is in fact a p–i–n diode in which the potential in the
Azad University, Abhar, Iran

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intrinsic region is controlled by the gate voltage. Ultra-sharp 2 nm. The source/channel/drain regions are doped with donor
doping concentration gradients in the source/channel junc- type impurities to 1×1019 cm−3 . These values are consistent
tion as well as drain/channel junction in nanoscale TFET with references [26–28]. The CG work function is 4.3 eV
devices is as major problem for its fabrication. Recently, and makes i-channel forms beneath the CG. The PG work
JL-TFET devices have been suggested to suppress the prob- function is 5.9 eV and makes a p-type region forms beneath
lem of ultra-sharp doping concentration gradients in regular the PG. The channel length is varied between 10 and 20 nm in
nanoscale TFET devices [26–28]. The JL-TFET is a thin our simulations. HJL-TFET devices have a junction between
film n-type silicon, in which the control gate (CG) makes an two semiconductors with a single type doping at the same
i-channel. Furthermore, the JL-TFET has a p auxiliary gate level, instead of doping junctions in regular TFET devices.
(PG) that makes a p-type region. Therefore, a HJL-TFET device still has been categorized as
The use of III–V compound semiconductors for the JL- a JL-TFET [28].
TFET device channel has been proposed to improve both The simulations are carried out by a commercial tool.
the parameters of the ON-state current and SS in HJL-TFET The local band-to-band tunneling (BTBT) model neglects
devices [28]. Investigations in [28] indicated that the highest the variation of the quasi-fermi levels over the tunneling
ION /IOFF ratio and lowest value of SS were related to the path, and it assumes that there are always initial and final
HJL-TFET device with GaAs from III–V compound semi- states available for the tunneling process. The nonlocal
conductor as the drain/channel material, and Ge from group effects in electron tunneling process, such as variation of the
IV semiconductor as the source material. The major goal of quasi-fermi levels over the tunneling length and the spatial
this study is to propose a new HJL-TFET for improvement variation of the energy bands in lateral direction, are taken
of the switching behavior. In the present paper, it was pro- into account by nonlocal BTBT model [29]. In order to take
posed, for the first time, to use GaSb as the source material the high doping concentration into account, band gap nar-
and GaAs as the drain/channel material. These materials have rowing (BGN) model is comprised [30]. The BGN model
not been applied for HJL-TFETs so far. The drain/channel affects the intrinsic carrier concentration. Trap-assisted tun-
material (GaAs) and source material (GaSb) are considered in neling results in a reduction of Shockley–Read–Hall (SRH)
such a way that the proposed structure fabrication is feasible. recombination lifetimes in regions of strong electric fields
Challenges of the fabrication process of the proposed device, and affects the OFF-state current of the JL-TFET device. The
namely the GaAs:GaSb HJL-TFET, have been discussed. Schenk’s model is applied to take trap-assisted tunneling into
Besides, the performance of the GaAs:GaSb HJL-TFET account [31]. The concentration-dependent Shockley-Read-
device and the optimized device discussed elsewhere [28], the Hall (SRH) model is considered for more accuracy of the
GaAs:Ge HJL-TFET is compared based on the parameters OFF-state current. The interface trap effect as well as effect
of ION /IOFF , and average SS for different channel lengths. of quantum confinement near the gate oxide is also taken
This paper is organized as follows: The details of the into account [30,32]. The expressed models are considered
proposed structure and simulation models are explained in by [26–28].
Sect. 2. In the Sect. 3 of this paper, the operation of principle Although TFETs might be less sensitive to changes in
of the JL-TFET device is analyzed. In Sect. 4, the results of channel mobility than MOSFETs since the transport through
simulation are discussed. Finally, in Sect. 5, a conclusion will the tunnel junction dominates over any scattering in the chan-
be provided. nel, the Lombardi model is adopted in our simulations for
more accuracy [30]. The transverse field and doping depen-
dent of the mobility in the JL-TFET device are taken into
2 Device structure and simulation models account by Lombardi model.

The JL-TFET is in fact a thin film silicon heavily n-type

doped, in which the control gate (CG) makes an i-channel 3 Operating principles
beneath the CG as well as the P auxiliary gate (PG) makes
an p-type region beneath the PG. The simulated double gate The JL-TFET device without PG and CG electrodes is assem-
JL-TFET structure and double gate HJL-TFET are shown in bled to an n-type semiconductor. Simulation results show that
Fig. 1a, b, respectively. The band gap of the source, channel PG and CG affect the energy bands diagrams and carrier den-
and drain regions is the same in a JL-TFET device, while sity of the JL-TFET device. To investigate the PG and CG
the band gap of the source region is not the same with drain effects, we have plotted the diagrams of the energy bands and
and channel regions band gap in the HJL-TFET device. In carrier density along both n-type semiconductor (JL-TFET
the both simulated JL-TFET and HJL-TFET, source/drain without PG and CG) and JL-TFET device, which is shown
lengths are 20 nm, the body thickness is 5 nm, device width in Fig. 1a, for the channel length of 20 nm in OFF-state, see
is 1um, and the high-k oxide (HfO2 (k = 29)) thickness is Fig. 2. Comparing between energy bands and carrier density

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Fig. 1 a JL-TFET and b HJL-TFET. The structural parameters of simulated devices in this paper (i.e., HJL-TFET and JL-TFET) are consistent
with [26–28]

Fig. 2 a Energy band diagram and b carrier density, taken horizontally conditions of the JL-TFET are as follows: VGS = 0 V and VDS = 1 V.
across the n-type semiconductor (symbols) and JL-TFET device (lines) The bias condition of n-type semiconductor is VDS = 1 V
with 20 nm channel length at a distance 1 nm from the surface. The bias

of JL-TFET and those of the n-type semiconductor in Fig. 2 4 Result and discussion
demonstrates that the difference of PG and CG work func-
tions with thin film silicon in JL-TFET converts the source The use of a III–V compound semiconductor material in the
and channel regions into p-type and intrinsic regions, respec- JL-TFET device channel would improve the ON-state cur-
tively. As a result, the source/channel/drain regions behave rent and SS compared to a regular JL-TFET device with a
as p–i–n. silicon channel. In [28], various structures of HJL-TFETs
In fact, the JL-TFET device behaves like a reverse bias using III–V compound semiconductor materials are proposed
pin diode, which is turned on by applying positive voltage for improving the ON-state current and subthreshold slope.
on the control gate. Figure 3a, b demonstrates the diagrams The HJL-TFET device proposed in [28] is similar to the
of energy bands and carrier density for JL-TFET device device shown in Fig. 1b. The investigations in [28] show
shown in Fig. 1a for the channel length of 20 nm in ON- that the maximum ION /IOFF ratio and minimum value of
state. As can be observed, the voltage applied to CG drives average SS are related to the HJL-TFET device with GaAs as
the energy bands in channel region downward; consequently, drain/channel material (material-1) and Ge as source mate-
the electrons of the source valence band tunnel to the channel rial (material-2). In the present paper, for the first time, a
conduction band and the tunneling current flows. Results of new HJL-TFET structure with GaAs as drain/channel mate-
the numerical simulations indicated that the ON-state cur- rial (material-1) and GaSb as source material (material-2) is
rent and average SS for the device in Fig. 1a with the channel proposed in order to improve the performance of the HJL-
length of 20 nm are 0.2 mA/um and 30 mV/dec, respectively. TFET device.

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Fig. 3 a Energy band diagram and b carrier density, taken horizontally across the JL-TFET device with 20 nm channel length at a distance 1 nm
from the surface in the ON-state. The bias conditions are as follows: VGS = 1 V and VDS = 1 V

Figure 4a illustrates the energy band diagram of the respectively. In the present study, IOFF is the drain current
GaAs:GaSb HJL-TFET with 20 nm channel length across at VGS = 0 V and VDS = 1 V.
the device in thermal equilibrium (VGS = VDS = 0 V). 2. The ON-state current of GaAs:GaSb and GaAs:Ge struc-
As shown, electron quasi-fermi level (E Fn ) and hole quasi- tures is almost the same. In the present study, ION is the
fermi level (E Fp ) are flat in both of the source/channel and drain current at VGS = 1 V and VDS = 1 V.
drain/channel interfaces. The energy band diagram in the lat- 3. The average subthreshold slope and point slope of
eral direction is shown in Fig. 4b, c for the proposed device GaAs:GaSb structure are less than those of GaAs:Ge
structure in the OFF and ON states, respectively. The applied structure (see inset of Fig. 5a).
voltage to the CG decreases the tunneling barrier width in
source/channel interface in the ON-state. Considering the The OFF-state current of HJL-TFET device depends on
position of the Fermi levels in Fig. 4c, the fact reveals that the electron-hole density within the channel. The product
the full states of source region are located in front of empty of the electron-hole density by considering the BGN is
states of channel region in the tunneling junction, so the elec- expressed as follows [30,33]:
tron tunneling from the source into the channel is allowed in  
lateral direction and the tunneling current flows. Therefore, E Fn − E Fp
np = n 2i,eff
exp .
the operational principles of GaAs:GaSb HJL-TFET device KT
 
are similar to those of JL-TFET device expressed in Sect. 3. E g,app
The main difference between the proposed structure in the n i,eff = n i,0 exp
2 2
. (1)
KT
present paper and the optimized structure in [28] (i.e., GaAs
as material-1 and Ge as material-2) is to use GaSb instead of where n, p, n i,eff , E Fn , E Fp , K, and T indicate electron density,
Ge in the source region. Other device structural parameters hole density, effective carrier concentration at heavy doping,
of proposed structure are similar to those given for the opti- electron quasi-fermi level, hole quasi-fermi level, Boltzmann
mized structure in [28], and thus, it would be fair to compare constant, and temperature in Kelvin, respectively. Moreover,
the performance of the two devices. In the following sections, n i,0 is the intrinsic carrier concentration at moderate doping
the HJL-TFET device optimized in [28] and the HJL-TFET levels, and E g,app is the apparent BGN, which is a function
proposed in the present paper will be indicated by GaAs:Ge of the doping level [30,33].
and GaAs:GaSb, respectively. Figure 6a, b, respectively, demonstrates the square prod-
Figure 5a compares the ID −VGS characteristic of the HJL- uct of electron-hole density and quasi-fermi level along the
TFET device for GaAs:Ge and GaAs:GaSb structures with HJL-TFET device for the channel length of 20 nm in OFF-
the channel length of 20 nm. The simulated ID −VGS char- state. As seen, less (E Fn − E Fp ) in the channel of GaAs:GaSb
acteristic of GaAs:Ge structure and the results in [28] are structure than the channel of GaAs:Ge structure leads to less
consistent. The important points in Fig. 5a are as follows: np in the channel of GaAs:GaSb structure than the channel of
GaAs:Ge structure (note Eq. (1)). As a result, the resistance of
1. The OFF-state current of GaAs:GaSb and GaAs:Ge the GaAs:GaSb structure’s channel is higher than that of the
structures is IOFF = 0.12 fA/um and IOFF = 5.3 fA/um, GaAs:Ge structure’s channel, which results in a significant

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Fig. 4 Energy band diagram taken horizontally across the GaAs:GaSb HJL-TFET device with 20 nm channel length at a distance 1 nm from the
surface in a thermal equilibrium (VGS = VDS = 0 V), b OFF-state (VGS = 0 V, VDS = 1 V), and c ON-state (VGS = VDS = 1 V)

Fig. 5 ID −VGS characteristics of HJL-TFET devices with a 20 nm channel length and b various channel length. The bias condition is as follows:
VDS = 1 V. The inset of (b) the ID −VGS characteristics of HJL-TFET device with 20 nm channel length in the subthreshold region

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Fig. 6 a Square product of electron-hole density and b quasi-fermi level, taken horizontally across the HJL-TFET device with 20 nm channel length
at a distance 1 nm from the surface in the OFF-state. The bias conditions are as follows: VGS = 0 V and VDS = 1 V

reduction in the OFF-state current of GaAs:GaSb structure VTVDS=1V − VTVDS=0.05V

DIBL = . (2)
compared to GaAs:Ge structure. Consequently, for the chan- VDS=1V − VDS=0.05V
nel length of 20 nm, the ION /IOFF ratio of GaAs:GaSb and
GaAs:Ge structures is are 7 × 1013 and 2 × 1012 respectively. where VTVDS=1V is the threshold voltage at VDS = 1 and
Simulation results demonstrate that swing values along VTVDS=0.05V is the threshold voltage at VDS = 0.05 V. For
the ID −VGS curve are a function of gate voltage in TFET 20 nm channel length, DIBL for GaAs:GaSb structure is
devices [20,21]. In order to observe the subthreshold behav- 11.4 mV/V and is improved by 15.5%, as compared to that
ior, two different types of swing are defined, point slope and of the GaAs:Ge structure. As a result, SCEs are less pro-
average SS. The point slope is considered as the minimum nounced in GaAs:GaSb structure for 20 nm channel length,
slope value at any point on the ID −VGS curve, typically found as compared to GaAs:Ge structure.
right as the device leaves the OFF-state and tunneling current The total gate-to-gate capacitance (Cgg ) plays a crucial
starts to flow. Average SS is considered from the point where role in determining the intrinsic gate delay for logic transis-
the current begins to increase with increasing gate voltage, tor applications [34]. The intrinsic gate delay is Cgg VDD /ION
up to the threshold voltage. In this paper, threshold volt- [4,8,34], in which VDD is supply voltage, Cgg and ION
age defined using the constant current technique [20]. The indicate the total gate-to-gate capacitance and ON current,
point slope of the GaAs:GaSb and GaAs:Ge structures is 4.2 respectively, and their values can be extracted through numer-
and 8.8 mV/dec, respectively. Besides, the average SS of the ical simulations. Figure 7 shows the Cgg versus the gate
GaAs:GaSb and GaAs:Ge structures is 13 and 16 mV/dec. voltage. As can be seen, the Cgg in both GaAs:GaSb struc-
Thus, for the channel length of 20 nm, the point slope and ture and GaAs:Ge structure is almost identical. Therefore, it
average SS of the proposed structure are optimized by 52% can be said that the intrinsic gate delay of both structures is
and 19%, respectively, compared to the GaAs:Ge structure. almost the same. For 20 nm channel length, the intrinsic gate
In fact, the gate’s control on the channel in GaAs:GaSb struc- delay of GaAs:GaSb and GaAs:Ge structures is 7.2 fS.
ture is increased compared to GaAs:Ge structure; as a result, Simulation results show that ON-state current depends
the average SS and point slope in GaAs:GaSb structure are on GaAs:GaSb interface position for 20 nm channel length
reduced compared to GaAs:Ge structure. of device shown in Fig. 1b. The overlap of energy between
The interdependence of gate and drain in control of the source valence band and channel conduction band decreases
threshold voltage, and therefore drain current, have a further in the ON-state by shifting GaAs:GaSb interface position to
important consequence in device performance. This effect right (e.g., from 45 to 50 nm) so that it is placed underneath
is so-called drain-induced barrier lowering (DIBL). DIBL the PG. Therefore, it reduces the slope of energy band dia-
effect could be renamed as drain-induced barrier narrowing gram in tunneling junction; consequently, ON-state current
(DIBN) since the origin of the threshold voltage shift with decreases. Moreover, our simulation results show the product
increasing VDS is the drain voltage’s ability to decrease the of the electron-hole density is increased in the OFF-state by
tunneling barrier width. DIBL is a difference in the threshold shifting GaAs:GaSb interface position to right. It increased
voltage for drain voltage of 50 mV and 1 V with gate voltage the OFF-state current; consequently, SS increases. Simula-
of 1 V. DIBL is calculated from following formula [28]: tion results show that the optimal ION /IOFF and average SS

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Fig. 7 a The total gate-to-gate capacitance as the function of gate volt- channel length. b ID −VGS characteristics of GaAs:GaSb HJL-TFET
age. We assume VDS = VDD = 1 V and sweep gate voltage between 0 device with 20 nm channel length for various WSiO2
and 1 V at a frequency of 106 Hz. HJL-TFET structures have a 20 nm

can be obtained when GaAs:GaSb interface position is at and average SS ∼ 53 mV/dec [23]. The Si:InAs HJL-TFET
45 nm. device with the channel length of 20 nm had ION /IOFF ∼ 107
The width of the oxide between CG/PG (WSiO2 ) is 2 nm and average SS ∼ 32 mV/dec [28]. These results indicate
in our simulation, and this value is consistent with refer- the superiority of the device proposed in the present paper to
ence [28]. Simulation results show that the slope of energy the structures proposed in [23,28,35].
band diagram in tunneling junction (i.e., adjacent to the
source/channel junction) depends on WSiO2 for 20 nm chan- 4.1 Challenges of fabrication process
nel length of device shown in Fig. 1b. Our results show
that the slope of energy band diagram in tunneling junc- Recently, several successful attempts have been made to
tion decreases in the OFF-state by increasing the WSiO2 fabricate GaSb and GaAs junctions using metal organic
from 2 to 3 nm; consequently, OFF-state current decreases. vapor phase epitaxy (MOVPE) technique [36–38]; accord-
OFF-state current for WSiO2 = 3 nm is one order of magni- ingly, GaAs:GaSb HJL-TFET device can be fabricated with
tude lower than OFF-state current for WSiO2 = 2 nm, see a vertical junction using MOVPE technique. One of the
Fig. 7b. Moreover, our simulation results show the slope main challenges in the fabrication process of GaAs:GaSb
of energy band diagram in tunneling junction is almost HJL-TFET is lack of appropriate oxide in III–V compound
unchanged in the ON-state for WSiO2 = 3 nm, as compared semiconductors. Recently, HfO2 and Al2 O3 have been suc-
with WSiO2 = 2 nm. As a result, the ON-state current is cessfully used as the dielectric for GaAs MOSFET through
almost intact, for WSiO2 = 3 nm in comparison with that of atomic layer deposition (ALD) technique [39], which can be
WSiO2 = 2 nm. On the other hand, the slope of energy band used for other III–V compound semiconductors; therefore,
diagram in tunneling junction is decreased in the ON-state, this technique can be applied for using HfO2 as the dielectric
by increasing WSiO2 for WSiO2 larger than 3 nm. As a result, in GaAs:GaSb structure.
the ON-state current is decreased; consequently, device per- The hole density of source has a large effect on the
formance degrades, see Fig. 7b. Increasing the WSiO2 from ON-state current level and average SS value, because the
2 to 3 nm is a feasible way of bringing up the breakdown tunneling takes place between the source and the channel
voltage for the oxide between CG/PG. As mentioned above, regions. Surveys performed in this study show that hole
WSiO2 is 2 nm in GaAs:Ge structure [28]. Therefore, WSiO2 is density of source is increased by increasing the PG work
considered to be 2 nm in our simulation for the fair compari- function; consequently, the ON-state current increases as
son between the GaAs:GaSb structure and GaAs:Ge structure well as average SS decreases. Proposed GaAs:GaSb HJL-
[28]. TFET has a reasonable ON-state current for PG work
The proposed nanowire junctionless FET device with function larger than 5 eV. The importance of PG work func-
shell doping profile (SDP) had ION /IOFF ∼ 108 and tion for a value smaller than 6 eV is investigated, because
SS ∼ 61 mV/dec for the channel length of 20 nm [35]. excessive increasing of PG work function results in increas-
The dual material gate tunneling graphene nanoribbon field- ing of voltage difference between PG and CG terminals. As a
effect transistor (DMG-T-GNRFET) had ION /IOFF ∼ 105 result, oxide breakdown might be happened in the 2 nm oxide

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Fig. 8 a ID −VGS characteristics of a GaAs:GaSb structure in the the GaAs:GaSb structure with 20 nm channel length at a distance 1 nm
subthreshold region, the bias conditions are as follows: VDS = 1 V. from the surface, the bias conditions are as follows: VGS = 0.12 V and
b Square product of the electron-hole density taken horizontally across VDS = 1 V

between CG and PG due to the voltage difference between 4.3 GaAs:GaSb HJL-TFET device scaling
two terminals. The optimal values for ON-state current and
average SS are obtained for 5.9 eV [40] PG work function. Figure 5b shows the ID −VGS characteristic of the HJL-TFET
Desired work function for PG and CG can be created by the device with the channel lengths of 15 nm and 10 nm. The ON-
use of molybdenum with nitrogen implant dose as metal, as state current of TFET depends on the length of tunneling
it carries unique properties like high melting point and low junction (i.e., adjacent to the source/channel junction), while
resistivity. It helps to regulate the work functions at particular it is independent from the channel length [20,21]. Therefore,
annealing conditions, thus providing tunable work function the ON-state current of HJL-TFET does not change with the
for PG and CG according to the requirements [41]. change in channel length (see Fig. 5b). On the other hand,
by reducing the channel length, the SCEs are increased and,
as a result, the OFF-state current of HJL-TFET device is
increased (see Fig. 5b). Numerical simulations in this study
4.2 Trap-assisted tunneling in GaAs:GaSb HJL-TFET demonstrate that for the channel lengths shorter than 10 nm,
Zener breakdown for the source/channel junction occurs in
The effect of band tailing due to defect states in the band gap the OFF-state due to the increased SCEs. As a result, the
is considered by trap-assisted tunneling in our simulations HJL-TFET device does not turn off.
[42,43]. Simulation results show that trap-assisted tunneling
affects the subthreshold behavior of the GaAs:GaSb HJL- 4.3.1 Benchmarking parameters
TFET. Figure 8a shows the ID −VGS characteristic of 20
nm channel length GaAs:GaSb HJL-TFET in subthreshold In this section, the parameters of subthreshold slope and
region. The OFF-state current by taking trap-assisted tunnel- ION /IOFF ratio of the GaAs:GaSb HJL-TFET device will be
ing into account is higher than the OFF-state current when compared with those of the devices that have been recently
the trap-assisted tunneling is absent. Figure 8b shows the introduced [28,35]. Figure 9a shows the ION /IOFF ratio
product of electron-hole density of 20 nm channel length according to the channel length for GaAs:GaSb HJL-TFET,
GaAs:GaSb HJL-TFET for VGS = 0.12 V and VDS = 1 V. GaAs:Ge HJL-TFET, and SDP JL-FET [35]. The results
Electron-hole density in the channel region is increased by expressed for SDP JL-FET device were extracted from [35].
taking trap-assisted tunneling into account; hence, leakage As shown, the ION /IOFF ratio is decreased with reducing
current is increased. If the trap-assisted tunneling model channel length, due to increased SCEs.
switches off in the simulation for the 20 nm channel length of For a given channel length, however, the ION /IOFF ratio is
GaAs:GaSb structure, average SS = 10 mV/dec is obtained. drastically improved for the GaAs:GaSb HJL-TFET device.
Trap-assisted tunneling induces larger channel tunneling rate For example, the ION /IOFF ratio for the GaAS:GaSb HJL-
in the subthreshold region. As a result, OFF-state current and TFET with 15 nm channel length is about 1.6E13, while the
average SS are increased and device performance deterio- same ratio for the GaAs:Ge HJL-TFET and the SDP JL-FET
rates. with 15 nm channel length is 1.4E12 and 1.8E8, respectively.

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Journal of Computational Electronics (2018) 17:745–755 753

Fig. 9 a ION /IOFF ratio and b average SS as a function of channel length for the GaAs:GaSb HJL-TFET, GaAs:Ge HJL-TFET and SDP JL-FET

This is due to a considerable decrease in OFF-state current in TFET device has been proposed to have better switching
GaAs:GaSb HJL-TFET as compared to GaAs:Ge HJL-TFET behavior compared to the GaAs:Ge HJL-TFET devices. The
and SDP JL-FET. Figure 9b shows average SS as a function GaAs:GaSb HJL-TFET device can be fabricated with a ver-
of the channel length. As shown, the average SS of SDP tical junction using MOVPE techniques.
JL-FET is increased with reducing channel length, due to Simulation results show less product of electron-hole den-
increased SCEs. The point slope of GaAs:GaSb HJL-TFET sity in the channel of the GaAs:GaSb HJL-TFET than the
and GaAs:Ge HJL-TFET for a 10 nm channel length, how- GaAs:Ge HJL-TFET which leads to less channel resistance
ever, is less than that of GaAs:GaSb HJL-TFET and GaAs:Ge of the GaAs:GaSb HJL-TFET than the GaAs:Ge HJL-
HJL-TFET for a 15 nm channel length (see Fig. 5b). There- TFET in the OFF-state. Therefore, the OFF-state current of
fore, average SS of GaAs:GaSb HJL-TFET and GaAs:Ge GaAs:GaSb HJL-TFET is considerably reduced as compared
HJL-TFET for a 10 nm channel length is decreased, as to GaAs:Ge HJL-TFETs. The ION /IOFF ratio and averageSS
compared to that of GaAs:GaSb HJL-TFET and GaAs:Ge for the GaAs:GaSb HJL-TFET with a 15 nm channel length
HJL-TFET for a 15 nm channel length (see Fig. 9b). device are about 13.8 mV/dec and 1.6 × 1013 respectively,
The gate controllability on the channel of GaAs:GaSb while the same parameters for the GaAs:Ge HJL-TFET with
HJL-TFET is higher than that of GaAs:Ge HJL-TFET and 15 nm channel length device are about 16.9 mV/dec and 1.4
SDP JL-FET. As a result, the GaAs:GaSb HJL-TFET device × 1012 . The high ION /IOFF ratio and low average SS of
provides significantly better average SS over the GaAS:Ge the GaAs:GaSb HJL-TFET lead to a higher speed for this
HJL-TFET and SDP JL-FET for a given channel length. structure compared to the GaAs:Ge HJL-TFET. Also, for a
For example, a GaAs:GaSb HJL-TFET with 15 nm channel 20 nm channel length, the subthreshold slope at threshold
length has average SS ∼ 13.8 mV/dec, while the average current of the GaAs:GaSb and GaAs:Ge structures is 21.8
SS for the GaAs:Ge HJL-TFET and the SDP JL-FET with and 23.2 mV/dec, respectively.
15 nm channel length is 16.9 and 63 mV/dec, respectively. All results in this study depict a simulation study with-
out considering the impacts of defects due to the interfacial
regions as well as nonsmoothness of the interfacial regions.
5 Conclusion A few modifications can be applied in the simulation method
by considering the impact of defects to get more accurate
Recently, the JL-TFET device has been considered to avoid result.
the issue of ultra-sharp doping concentration gradients in
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