IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO.

4, JULY 2001 545

A New Simplified Space–Vector PWM Method for

Three-Level Inverters
Jae Hyeong Seo, Member, IEEE, Chang Ho Choi, Member, IEEE, and Dong Seok Hyun, Senior Member, IEEE

Abstract—In this paper, a new simplified space–vector pulse

width modulation (SVPWM) method for three-level inverter
is proposed. This method is based on the simplification of the
space–vector diagram of a three-level inverter into that of a
two-level inverter. If simplified by the proposed method, all the
remaining procedures necessary for the three-level SVPWM are
done like conventional two-level inverter and the execution time
is greatly reduced. The dc-link neutral-point potential control al-
gorithms are implemented more easily. And the proposed method
can be applied to the multi-level inverters above three-level. The
validity of the new SVPWM method is verified by experiment with
a 1000 KVA three-level insulated gate bipolar transistor (IGBT)
inverter.
Index Terms—Multilevel inverter, space-vector PWM, three-
level inverter.

Fig. 1. Circuit diagram of a three-level inverter.

I. INTRODUCTION

R ECENTLY, with the dramatic improvements in high

voltage technologies, high voltage insulated gate bipolar
transistor (HVIGBT) and gate commutated thyristor (GCT) are
switching frequency and the blocking voltage of the switching
device is half of the dc-link voltage. So the three-level inverter
expanding the area of their application. For the high perfor- topology is generally used in realizing the high performance,
mance ac drive systems at increased power level, high quality high voltage ac drive systems [1].
inverter output with low harmonic loss and torque pulsation However, the inherent neutral-point potential variation of a
is necessary. In case of the conventional two-level inverter three-level inverter has to be effectively suppressed to fully uti-
configuration, the harmonic contents reduction of an inverter lize the above-mentioned advantages of a three-level inverter.
output current is achieved mainly by raising the switching So many PWM strategies have been proposed to solve the neu-
frequency. tral-point potential unbalance problem [2], [3], [5]. But many of
However in the field of high voltage, high power applications, them are focused mainly on the neutral-point potential control
the switching frequency of the power device has to be restricted method, while still using the complicated dwelling time calcu-
below 1 KHz, even with the HVIGBT and GCT, due to the lation and the switching sequence selection method.
increased switching loss. So the harmonic reduction by raised In this paper, a simple SVPWM method for three-level in-
switching frequency of a two-level inverter becomes more diffi- verter is proposed. By using the new PWM strategy, dwelling
cult in high power applications. In addition, as the dc link voltage time calculation and switching sequence selection are easily
of a two-level inverter is limited by voltage ratings of switching done like conventional two-level inverter. And the neutral-point
devices, the problematic series connection of switching devices voltage control algorithm can be easily implemented. In this
is required to raise the dc link voltage. By series connection, paper, the proposed three-level SVPWM method is explained
the maximum allowable switching frequency has to be more in detail and verified using 2500 V, 1000 KVA three-level IGBT
lowered, thus the harmonic reduction becomes more difficult. inverter system.
From the aspect of harmonic reduction and high dc-link
voltage level, three-level approach seems to be the most II. SIMPLIFIED SPACE–VECTOR PWM METHOD
promising alternative. The harmonic contents of a three-level A. Basic Principles of the Proposed SVPWM Method
inverter are less than that of a two-level inverter at the same
Fig. 1 is a circuit diagram of a three-level inverter and the
switching states of each phase of the inverter are listed in Table I.
Manuscript received February 25, 2000; revised March 31, 2001. Recom-
mended by Associate Editor S. Y. R. Hui. There are three kinds of switching states P, O, and N in each
J. H. Seo is with the R&D Center, POSCON Corporation, Seoul 136-701, phase, so there exist 27 switching states in three phase three-
Korea (e-mail: [email protected]). level inverter.
C. H. Choi and D. S. Hyun are with the Department of Electrical Engineering,
Hanyang University, Seoul 133-791, Korea. By using the space–vector diagram of a three-level inverter,
Publisher Item Identifier S 0885-8993(01)05956-7. the basic principle of the proposed SVPWM method can be
0885–8993/01$10.00 ©2001 IEEE
546 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, JULY 2001

TABLE I
SWITCHING STATES AND TERMINAL VOLTAGES OF A THREE-LEVEL
INVERTER (X = U; V; W)

easily explained. The space–vector diagram of a three-level in-

verter, shown in Fig. 2, can be thought that it is composed of
six small hexagons that are the space–vector diagrams of con-
ventional two-level inverters. Each of these six hexagons, con-
stituting the space–vector diagram of a three-level inverter, cen-
ters on the six apexes of the inner small hexagon as is shown
in Fig. 3. So, if these six small hexagons are shifted toward the
center of the inner hexagon by , the space–vector diagram Fig. 2. Space–vector diagram of a three-level inverter.
of a three-level inverter is simplified to that of a two-level in-
verter. To simplify into the space–vector diagram of a two-level
inverter as explained above, the following two steps have to be
taken. First, from the location of a given reference voltage, one
hexagon has to be selected among the six hexagons. Secondly
the original reference voltage vector has to be subtracted by the
amount of the center voltage vector of the selected hexagon.
By these two steps, the three-level space–vector plane is trans-
formed to the two-level space–vector plane.
Then the determination of switching sequence and the calcu-
lation of the voltage vector duration time are done as conven-
tional two-level SVPWM method. As the proposed SVPWM
method is same in principle as conventional two-level SVPWM,
various techniques used in two-level SVPWM can be applied to Fig. 3. Simplification of a three-level space–vector diagram.
this proposed method too.
In Fig. 4, is the original reference voltage vector and
B. Correction of Reference Voltage Vector is the corrected reference voltage vector seen from the location
of the (POO), (ONN) vector.
In this section, the first procedure for the simplified Following is the sample program of this procedure explained
three-level space–vector PWM method is described in detail. in this section.
By the location of a given reference voltage vector, one hexagon
is selected among the six small hexagons that comprise the
three-level space–vector diagram. The reference voltage vector If
should stay at the inner of the selected hexagon. This procedure If
divides the three-level space–vector diagram into six regions else if
that are covered by each small hexagon as shown in Fig. 3. The else
value of in Fig. 3 represents the selected hexagon. There exist
the regions that are overlapped by adjacent small hexagons else
in the three-level space–vector diagram. So if the reference If
voltage vector stays at those regions, can have any values that else if
are possible. Fig. 3(a) and (b) illustrate two possible ways of else
selecting the value of . If those methods shown in Fig. 3(a)
and (b) are used, the value of at the shaded region of Fig. 2
can have the value of 1 or 2.
Once the value of is determined, the origin of a reference
voltage vector is changed to the center voltage vector of the
selected hexagon. This is done by subtracting the center vector
of the selected hexagon from the original reference vector, as Sample Program for the Simplifying of the Three-Level
shown in Fig. 4. This is summarized in Table II. Space–Vector Diagram
SEO et al.: NEW SIMPLIFIED SPACE–VECTOR PWM METHOD FOR THREE-LEVEL INVERTERS 547

TABLE II
REFERENCE VOLTAGE VECTOR CORRECTION OF THE PROPOSED
SVPWM METHOD

Fig. 4. Changing the base vector of an original reference voltage vector.

C. Calculation of the Dwelling Times

If the reference voltage vector is redefined as explained in
the previous section, the dwelling times are calculated at the
same manner as conventional two-level SVPWM method. The
(a) (b)
calculation of dwelling times can be done more efficiently by
the method presented in [4] as shown in the following example. Fig. 5. Neutral-point potential control of a three-level inverter.
In calculating the dwelling times, the only difference between
the two-level SVPWM and the three-level SVPWM is the factor
2 appearing at the first two lines of the following example.

if
else
if
if

if

Fig. 6. Application of the proposed SVPWM method to the four-level inverter.

the switches that have to be enabled to change their states among

Sample Program for the Dwelling Time Calculation
the four switches in each phase. This is realized by simple logic
If the dwelling times are calculated, the switching sequence
gates using the value of .
has to be determined. However the switching sequence is deter-
mined automatically by the value of . That is, on the basis of the
D. Neutral-Point Potential Control
center voltage vector of the selected hexagon, the switching se-
quence is determined as conventional two-level inverter. For ex- It is well known that there are two methods controlling the
ample, in case of Fig. 4, the switching sequence will be (POO)- neutral-point potential of a three-level inverters. The first is
(PON)-(OON)-(ONN). If the (ONN) vector is selected as a base changing the switching sequence and the second is rearranging
and the notations used in two-level space–vector diagram are the time distribution of the redundant voltage vectors. These
adopted, the switching sequence can be expressed as (111)- two methods can be easily implemented with the proposed
(110)-(010)-(000). This switching sequence is exactly the same SVPWM method. The switching sequence is easy to change
as that of conventional two-level SVPWM. Therefore in deter- using the index .
mining the switching sequence, the only thing to do is selecting 1) Method 1: Changing the Switching Sequence
548 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, JULY 2001

(a) (b)

(c) (d)
Fig. 7. Test results of the proposed SVPWM method with 100 kW induction motor. (a) Line-to-line voltage and phase current at f = 20 [Hz]. (b) Line-to-line
voltage and phase current at f = 50 [Hz]. (c) Line-to-line voltage and dc-link voltage error (V0V ) at f = 20 [Hz]. (d) Line-to-line voltage and dc-link
voltage error (V 0 V ) at f = 20 [Hz].

If the reference voltage vector stays at the region, that is charged and the lower capacitor is charged. So if the value
overlapped by adjacent small hexagon, the neutral-point of index is changed depending on the voltage error
potential can be controlled by changing the switching se- and the direction of the power, the neutral-point potential
quence. When the reference is given as in Fig. 5(a), the is controlled. This is realized by simple procedure, sub-
index can have the value 1 or 2 as explained in the pre- tracting or adding 1 from the value of .
ceding section. In this case, the switching sequence can 2) Method 2: Rearranging the Time Distribution of the Re-
be given in the order of (POO)-(PON)-(OON)-(ONN) or dundant Voltage Vectors
(PPO)-(POO)-(PON)-(OON). The former sequence is the If the reference voltage vector stays at the region C in
case that the index has the value of 1, and the latter is Fig. 5(b), the switching sequence is given as follows:
the case that the index has the value of 2. In Fig. 5(a),
is the original reference voltage vector and is
the corrected reference voltage vector when the index
has the value of 1. is the corrected reference voltage , , , and are dwelling times of the corre-
vector when the index has the value of 2. If the former sponding voltage vectors.
switching sequence is selected and the load current flows In this case, the neutral-point voltage is controlled by
out from dc-link capacitors, the load current will dis- adjusting the value of Tip and Tin in response to the
charge the lower capacitor, while charging the upper ca- voltage error and to the load conditions [5]. As the voltage
pacitor of the dc-link. But on the contrary, if the latter vector (POO) and (OON) are same in magnitude and in
switching sequence is selected, the upper capacitor is dis- phase, changing the dwelling times of the two vectors has
SEO et al.: NEW SIMPLIFIED SPACE–VECTOR PWM METHOD FOR THREE-LEVEL INVERTERS 549

explained in this paper. Fig. 6 shows the case of four-level

SVPWM. From Fig. 6, we can know that the space–vector
diagram of a four-level inverter is composed of six three-level
space–vector diagrams whose center vectors are shown as cir-
cles. If it is simplified to the three-level space–vector diagram,
the remaining procedures for the SVPWM can be done like that
of the proposed three-level SVPWM method.

III. TEST RESULTS

The proposed SVPWM method was programmed with the
TMS320C31 DSP board and the 3300 V, 1200 A, EUPEC
IGBT’s are used to develop the three-level inverter. The inverter
was designed for driving the 630 kW, 2500 V induction motor,
but the 3300 V, 100 kW induction motor and RL load was used
for the test.
The test results of the developed system are shown in Figs. 7
and 8. The waveforms shown in Fig. 7 are the test results of
driving the 3300 V, 100 KW induction motor at 3600 V dc-link
voltage. Fig. 8 shows test results when the RL is used as a load
of inverter at 3250 V dc-link voltage. From the test results, we
can know that the proposed SVPWM is good at pulse-width
modulation of a three-level inverter and the voltage balance of
the dc-link is controlled fairly well in the whole speed range
of the motor, even though the proposed method is simple in its
structure.

IV. CONCLUSION
In the field of high power, high performance applications, the
three-level inverter seems to be the most promising alternative.
In this paper, a new simplified space–vector PWM method for
the three-level inverter is proposed and described in detail. The
proposed SVPWM method has the following features.
1) The switching sequence is determined without a look-up
table, so the memory of the controller can be saved.
2) The dwelling times of voltage vectors are calculated at
the same manner as two-level SVPWM. Thus the pro-
posed method reduces the execution time of the three-
level SVPWM.
3) It is easy to implement the neutral-point potential control
Fig. 8. Test results of the proposed SVPWM method with RL load. (a)
line-to-line voltage and phase current at f = 20 [Hz]; (b) line-to-line voltage algorithm.
and phase current at f = 50 [Hz]. 4) It can be applied to the multi-level SVPWM method
above four-level.
no effect on the output voltage vector only if the following The validity of the presented SVPWM method is verified by
equations are satisfied experimental results. The developed three-level IGBT inverter
system was applied to the #2 steel making factory of Pohang
Steel Corporation (POSCO).

REFERENCES
[1] J. H. Suh, “A design of a new snubber circuit for three-level gate turn-off
The underlined part of the sample program in Sec- thyristor inverters,” in Proc. EPE Conf., 1995, pp. 573–578.
tion II-C shows this process. [2] D. S. Hyun, “A Novel PWM Scheme for a Three-Level Voltage Source
Inverter with GTO Thyristors,” in Proc. IAS Conf., 1994, pp. 1151–1157.
E. Application to the Multilevel SVPWM [3] R. Jotten, “A fast space–vector control for a three-level voltage source
inverter,” in Proc. EPE Conf., 1991, pp. 70–75.
The proposed SVPWM method is also applicable to the [4] J. S. Kim, “A novel voltage modulation technique of the space vector
multi-level SVPWM above three-level. For example, the PWM,” Trans. Inst. Elect. Eng. Jpn., vol. 116-D, no. 8, pp. 820–825,
1996.
four or five-level space–vector diagram can be simplified to [5] S. Tamai, “3-level GTO converter-inverter pair system for large capacity
the three-level space–vector diagram on the same principles induction motor drive,” in Proc. EPE Conf., 1993, pp. 45–50.
550 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 4, JULY 2001

Jae Hyeong Seo (M’96) was born in Kyeong-San, Dong Seok Hyun (S’79–M’83–SM’91) received the
Korea, on May 21, 1971. He received the B.S. and B.E. and M.E. degrees from Hanyang University,
M.S. degrees in electrical engineering from Hanyang Seoul, Korea, in 1973 and 1978, respectively, and
University, Seoul, Korea, in 1994 and 1996, respec- the Ph.D. degree from Seoul National University,
tively. Seoul, in 1986, all in electrical engineering.
Since 1996, he has been with the Department of From 1976 to 1979, he was with the Agency of De-
Power Electronics, R&D Center, POSCON Corpo- fense Development, Korea, as a researcher. He was
ration, Seoul, as an Associate Research Engineer, a Research Associate in the Department of Electrical
where he has been engaged in the development Engineering, University of Toledo, Toledo, OH, from
and design of high voltage, high power converter 1984 to 1985, and a Visiting Professor of electrical
systems, and their control strategies. His current engineering, Technical University Münich, Germany,
research interests are high performance, high voltage motor drive systems, from 1988 to 1989. Since 1979, he has been at Hanyang University, where he is
power quality systems, and control problems in power electronics. currently a Professor in the Department of Electrical Engineering and Director
of the Advanced Institute of Electrical Engineering and Electronics (AIEE).
He is the author of more than 80 publications concerning electric machines,
high-power engineering, power electronics, and motor drives. His research in-
Chang Ho Choi (M’84) received the B.S. degree terests include power electronics, motor drives, digital signal processing, trac-
from Ajou University, Suwon, Korea, in 1979 tions, and their control systems.
the M.S. degree from Seoul National University, Dr. Hyun is a member of the Korean Institute of Electrical Engineers, the In-
Seoul, Korea, in 1984, and the Ph.D. degree from stitution of Electrical Engineers, U.K, and the IEEE Power Electronics, Industry
Hanyang University, Seoul, in 2000, all in electrical Applications, Circuits and Systems, and Electron Devices Societies.
engineering.
From 1983 to 1986, he had been with the Research
Institute of LG Industrial Systems Co., Ltd., Anyang,
Korea, where he was a Senior Researcher in the
Department of Power Electronics. From 1987 to
1990, he had been with Korea Servo Corporation,
Suwon, as a Principal Researcher in the Department of Servo Motor Drives.
Since 1990, he has been with the Department of Power Electronics, R&D
Center of POSCON Corporation, Seoul, as a Chief Researcher. His current
research interests are high-power motor drive system for continuous processing
lines, power quality systems, high-voltage pulse power applications, and
energy saving systems.