UNIT:-3

What are Sequential Circuits?

A sequential circuit refers to a special type of circuit. It consists of a series
of various inputs and outputs. Here, the outputs depend on a combination
of both the present inputs as well as the previous outputs. This previous
output gets treated in the form of the present state.

Types of Sequential Circuits

There are basically two types of sequential circuits:

1. Asynchronous sequential circuits

2. Synchronous sequential circuits

Clock Signal
The clock signal refers to a periodic signal where the ON and OFF times do not
need to be the same. Thus, whenever the ON and OFF times of the clock signal
happen to be the same, we use a square wave to represent the clock signal. Here
is a diagram that represents a typical clock signal:
Latches
Latches are digital circuits that store a single bit of information and hold its
value until it is updated by new input signals. They are used in digital
systems as temporary storage elements to store binary information. Latches
can be implemented using various digital logic gates, such as AND, OR,
NOT, NAND, and NOR gates
Introduction to flip flops

A flip flop is an electronic circuit with two stable states that can be
used to store binary data. The stored data can be changed by
applying varying inputs. Flip-flops and latches are fundamental
building blocks of digital electronics systems used in computers,
communications, and many other types of systems.

1. R-S flip flop

2. D flip flop
3. J-K flip flop
 4. T flip flop

1) RS flip flop

The basic NAND gate RS flip flop circuit is used to store the data and
thus provides feedback from both of its outputs again back to its
inputs. The RS flip flop actually has three inputs, SET, RESET and
clock pulse.

Figure-1:R-S flip flop circuit diagram

Figure-2:Characteristics table of R-S flip flop

### 2) D flip flop
A D flip flop has a single data input. This type of flip flop is obtained
from the SR flip flop by connecting the R input through an inverter,
and the S input is connected directly to data input. The modified
clocked SR flip-flop is known as D-flip-flop and is shown below.
From the truth table of SR flip-flop we see that the output of the SR
flip-flop is in unpredictable state when the inputs are same and high.
In many practical applications, these input conditions are not
required. These input conditions can be avoided by making them
complement of each other.

Figure-3:Circuit diagram of D flip flop

Figure-4:Characteristics table of D flip flop

3) J-K flip flop

In a RS flip-flop the input R=S=1 leads to an indeterminate output.

The RS flip-flop circuit may be re-joined if both inputs are 1 than also
the outputs are complement of each other as shown in
characteristics table below.

Figure-5:Circuit diagram of J-K flip flop

Figure-6:Characteristics table of J-K flip flop

4) T flip flop

T flip-flop is known as toggle flip-flop. The T flip-flop is modification

of the J-K flip-flop. Both the JK inputs of the JK flip – flop are held at
logic 1 and the clock signal continuous to change as shown in table
below.

Figure-7:Circuit diagram of T flip flop

Race-around Condition in JK Flip- lops

From the above truth table of the JK flip-flops, it can be observed that when J
= 1 and K =1, then output Qn+1 = Qn', which means for inputs J = 1 and K =
1, the JK flip-flops acts as a toggle switch.
Let us consider the inputs J = 1 and K = 1, and the output Q = 0. After the
propagation delay (let Δt) of the flip-flops, the output of the JK flip-flops
changes from 0 to 1. As we know, the output of the JK flip-flops is connected
to its inputs. Hence, the output also acts as input, and thus after the next delay
(Δt), the output will change from 1 to 0. This process will continue till the end
of the applied clock signal. Thus, the output of the JK flip-flops is uncertain.
This condition of JK flip-flops is called the race-around condition.

Race-around condition in JK flip-flops is shown in Figure-2, where T is the total

duration of clock pulse.

How the Race-around Condition Can Be Avoided?

The problem of the race-around condition does not exist in the flip-flops where
the inputs do not change during the presence of clock pulse. But, in the case
of JK flip-flops, the inputs change during the clock pulse due to the feedback
path present between inputs and outputs. Hence, in JK flip-flops, the race
around condition is a major problem.

The problem of race-around condition and the uncertainty of output can be

avoided by increasing the delay of the flip-flops. For that, the delay of the flip-
flops must be greater than the duration of the clock signal, i.e. Δt > T. In
another way, the duration of the applied clock signal (T) must be reduced to
make it less than the delay of the flip-flops (Δt).

However, the increase in the delay of the flip-flops is not a good practice
because it decreases the speed of the system. On the other hand, it is also
quite difficult to decrease the duration of the clock pulse (T) beyond the delay
of the flip-flops (Δt). This is because, the delay of the JK flip-flops (Δt) is of
the order of nanoseconds.

Hence, the most practical way to solve the problem of race-around condition
in JK flip-flops is to use the JK flip-flops in the Master and Slave Mode. In the
master-slave mode of JK flip-flops, two JK flip-flops are cascaded.

This is all about the race-around condition and its remedies in JK flip-flops.

Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q output
toggle until the CLK is 1. Thus, the uncertain or unreliable output produces. This
problem is referred to as a race-round condition in JK flip-flop and avoided by ensuring
that the CLK set to 1 only for a very short time.

Explanation
The master-slave flip flop is constructed by combining two JK flip flops. These flip flops
are connected in a series configuration. In these two flip flops, the 1st flip flop work as
"master", called the master flip flop, and the 2nd work as a "slave", called slave flip flop.
The master-slave flip flop is designed in such a way that the output of the "master" flip
flop is passed to both the inputs of the "slave" flip flop. The output of the "slave" flip
flop is passed to inputs of the master flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is
also used. For passing the inverted clock pulse to the "slave" flip flop, the inverter is
connected to the clock's pulse. In simple words, when CP set to false for "master", then
CP is set to true for "slave", and when CP set to true for "master", then CP is set to false
for "slave"
Working of a master slave flip flop –
1. When the clock pulse goes to 1, the slave is isolated; J and K
inputs may affect the state of the system. The slave flip-flop is
isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and
output is obtained.
2. Firstly the master flip flop is positive level triggered and the slave
flip flop is negative level triggered, so the master responds before
the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input
of the slave and the clock forces the slave to reset, thus the slave
copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input
of the slave and the Negative transition of the clock sets the slave,
copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and
thus the slave toggles on the negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
Timing Diagram of a Master Slave flip flop –

1. When the Clock pulse is high the output of master is high and
remains high till the clock is low because the state is stored.
2. Now the output of master becomes low when the clock pulse
becomes high again and remains low until the clock becomes high
again.
3. Thus toggling takes place for a clock cycle.
4. When the clock pulse is high, the master is operational but not the
slave thus the output of the slave remains low till the clock
remains high.
5. When the clock is low, the slave becomes operational and remains
high until the clock again becomes low.
6. Toggling takes place during the whole process since the output is
changing once in a cycle.
This makes the Master-Slave J-K flip flop a Synchronous device as it only
passes data with the timing of the clock signal.

Applications of Flip-Flops:
These are the various types of flip-flops being used in digital electronic
circuits and the applications of Flip-flops are as specified below.
 Counters
 Frequency Dividers
 Shift Registers
 Storage Registers
 Bounce elimination switch
 Data storage
 Data transfer
 Latch
 Registers
 Memory