CXG1122EN

SP5T GSM Triple-Band/GPRS Antenna Switch

Description
The CXG1122EN is one of a range of low insertion 16 pin VSON (Plastic)
loss, high power MMIC antenna switches for GSM/
GPRS triple-band, dual-band (CXG1121TN) and
applications. The low insertion loss on transmit
means increased talk time as the Tx power amplifier
can be operated at a lower output level. On-chip logic
reduces the component count and simplifies the PCB
layout by allowing the direct connection of the switch
to digital baseband control lines with the CMOS logic
levels.
This switch is an SP5T, one antenna can be routed
to either of the 2 Tx or 3 Rx ports. It requires 3 CMOS
control lines (CTL1, CTL2 and Tx ON).
The Sony's GaAs JFET process is used for low
insertion loss. An evaluation PCB is available.

Features
• Insertion loss: (Tx) 0.5dB typ. at 34dBm (GSM900)
• 3 CMOS compatible control lines
• Low second harmonic: –40dBm typ. at 34dBm (GSM900)
• Small package size: 16-pin VSON (2.7mm × 3.5mm × 0.9mm)

Applications
Triple-band handsets using the combinations of followings:
• GSM900/DCS1800/PCS1900
• GPRS
• DECT

Structure
GaAs J-FET MMIC

Absolute Maximum Ratings (Ta = 25°C)

• Bias voltage VDD 7 V
• Control voltage VCTL 5 V
• Operating temperature Topr –20 to +80 °C

GaAs MMICs are ESD sensitive devices. Special handling precautions are required.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E01Z20-PS
 CXG1122EN

Pin Configuration

Rx1 9 8 ANT

GND 10 7 GND

Rx2 11 6 Tx1

GND 12 5 GND

Rx3 13 4 Tx2

GND 14 3 GND

CTL1 15 2 VDD

CTL2 16 1 Tx ON

Truth Table
On Pass CTL1 CTL2 Tx ON
ANT – Tx1 GSM900 H Don't care H
ANT – Tx2 DCS1800 & PCS1900 L Don't care H
ANT – Rx1 GSM900/DCS1800/PCS1900 H L L
ANT – Rx2 GSM900/DCS1800/PCS1900 L L L
ANT – Rx3 GSM900/DCS1800/PCS1900 L H L

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 CXG1122EN

Electrical characteristics (Ta = 25°C)

Item Symbol Path Condition Min. Typ. Max. Unit
Tx1, Tx2 – ANT ∗1 0.5 0.7 dB
Tx1, Tx2 – ANT ∗2 1.0 1.2 dB
Insertion loss IL Rx1 – ANT ∗3 0.65 0.85 dB
Rx2 – ANT ∗4 1.2 1.4 dB
Rx3 – ANT ∗5 1.2 1.4 dB
∗3 18 20 dB
ANT – Tx1, Tx2
∗4 , ∗5 14 16 dB
Isolation ISO
Tx – Rx1, Rx2, Rx3 ∗1 23 25 dB
Tx – Rx1, Rx2, Rx3 ∗2 18 20 dB
VSWR VSWR 1.2
2fo –40 –36 dBm
Harmonics∗ Tx1, Tx2 – ANT ∗1 , ∗2
3fo –34 –30 dBm
P1dB compression
P1dB Tx1, Tx2 – ANT ∗1 , ∗2 36 dBm
input power
Control current ICTL VCTL = 3.0V 80 120 µA
Supply current for
ITX/IRX VDD = 3.3V 0.3 1 mA
Tx and Rx modes

Electrical characteristics are measured with all the RF ports terminated in 50Ω.
∗ Harmonics measured with Tx inputs harmonically matched. It is recommended that the harmonic matching is
used to ensure the optimum performance.

∗1 Power incident on GSM Tx, Pin = 34dBm, 880 to 915MHz, VDD = 3.3V, GSM Tx enabled
∗2 Power incident on DCS/PCS Tx, Pin = 32dBm, 1710 to 1910MHz, VDD = 3.3V, DCS/PCS Tx enabled
∗3 Power incident on ANT, Pin = 10dBm, 925 to 960MHz, VDD = 3.3V, GSM Rx enabled
∗4 Power incident on ANT, Pin = 10dBm, 1805 to 1880MHz, VDD = 3.3V, DCS Rx enabled
∗5 Power incident on ANT, Pin = 10dBm, 1930 to 1990MHz, VDD = 3.3V, PCS Rx enabled

Supply Voltage Value (VDD)

Mode Min. Typ. Max. Unit

GSM/DCS Tx 3.0 3.3 3.5 V
GSM/DCS/PCS Rx 2.7 3.0 3.5 V

CMOS Logic Value

Logic Min. Typ. Max. Unit

High 2.4 2.8 3.2 V
Low 0 0.4 V

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 CXG1122EN

DC Block Capacitors and Decoupling Capacitors

9 Rx1 ANT 8
47pF 47pF

10 GND GND 7

11 Rx2 Tx1 6
22pF 47pF

12 GND GND 5

13 Rx3 Tx2 4
22pF 22pF

14 GND GND 3

15 CTL1 VDD 2
100pF 100pF

16 CTL2 Tx ON 1
100pF 100pF

Note) Capacitors are required on all the RF ports for DC blocking (22pF – 47pF). Decoupling capacitors are
required on VDD and on control lines.

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 CXG1122EN

Application Note

Impedance Matching for Harmonic Minimization

This note outlines the method used to find the source impedance to present to a transmit port at the second
harmonic frequency (2fo) to reduce the second harmonic level at the antenna.
This should be carried out for a set of devices that represent the process variants. This way a compromise can
be found that suits all the variants.
The necessary equipment is shown immediately below.

Power Meter

Fundamental, fo Second Harmonic, 2fo

Signal 10dB Load Pull

B.P.F. Diplexer
Generator Coupler Tuner

DC Block

D.U.T.

DC Block

Spectrum
Analyzer

The device should be mounted on a PCB with 50Ω tracks running from all the RF pins to SMA connectors on
the PCB edge (DUT). All the ports should be externally DC blocked and the unused ports should be terminated in
50Ω. All the measurements should be performed at the incident powers for which the harmonic levels are
specified in this document.
The 2nd harmonic level at the antenna port is measured using the spectrum analyzer and the vertical and
horizontal position of the load pull stub adjusted such that this level is minimized.
The device should then be removed from the board and an SMA connector mounted such that the source
impedance seen by the transmit port at 2fo can be measured using a VNA.
Measurements should be de-embedded to the end of the SMA center pin.
A network should then be designed to match the impedance of the low pass filter (LPF), which usually comes
in front of the device, to the 2fo source impedance that gives sufficiently reduced 2fo levels for all the devices
measured.
The network should be designed to maintain a good match and insertion loss at the fundamental frequency.
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 CXG1122EN

Package Outline Unit: mm

16PIN VSON (PLASTIC)

+ 0.1
0.8 – 0.05

0.6

3.5
0.05 S

A S

0.35 ± 0.1

0.5 ± 0.2
2.5

2.7

B
x2
0.4 0.35 ± 0.1
0.15 S B
1.4 x4
0.15 S A B

0.23 ± 0.02
0.05 M S A-B

0.2 ± 0.01
0.03 ± 0.03
(Stand Off)

Solder Plating

0.13 ± 0.025
+ 0.09
0.14 – 0.03

TERMINAL SECTION
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE VSON-16P-01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.02 g

LEAD PLATING SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL COPPER ALLOY
SOLDER COMPOSITION Sn-Bi Bi:1-4wt%
PLATING THICKNESS 5-18µm

–6– Sony Corporation