Embedded Sys1_updated
Embedded Sys1_updated
Embedded Systems
Semester wise Pattern for Students Admitted to Higher Degree Programmes in the First Semester
Year First Semester U Second Semester U
M.E. Embedded Systems
BITS G553 Real-Time Systems 5 BITS G540 Research Practice 4
EEE G512 Embedded System Design 4 CS G523 Software for Embedded Systems 5
I Elective * MEL G642 VLSI Architecture 5
Elective * Elective *
17 18
EEE G626 Hardware-Software Co-Design 5 BITS G629T Dissertation 16
Elective * or Or
II Elective * BITS G639 Practice School 20
Elective *
17 16/20
2
Course Descriptions
Real-time software, Real-time operating systems scheduling, virtual memory issues, and file systems,
real-time databases, fault tolerance, and exception handling techniques, reliability evaluation, data
structures, and algorithms for real-time/embedded systems, programming languages, compilers, and run
time environment for real-time/embedded systems, real-time system design, real-time communication
and security, real-time constraints and multiprocessing and distributed systems.
Real-time and embedded systems; software issues in the embedded system; software development
process; requirement analysis: use cases, identification, and analysis of use cases, use case diagrams;
design: architectural design, design patterns, and detailed design; implementation: languages,
compilers, runtime environments, and operating systems for embedded software; testing:
methodologies, test cases. The course will also consist of laboratory practices and the development of
software for embedded systems.
FPGA and ASIC based design, Low-Power Techniques in RT Embedded Systems On-chip networking.
Hardware Software partitioning and scheduling, Co-simulation, synthesis and verifications,
Architecture mapping, HW-SW Interfaces, and Re-configurable computing.
Overview of CISC processor architectures; Instruction set architecture of CISC processor; hardware
flow-charting methods; implementing microprocessor logic from hardware flowcharts; RISC
instruction set architecture; Pipelined execution of RISC instructions; pipeline execution unit design;
control hazards; design of memory hierarchy.
This course is designed to train the students towards acquiring competence in research methodologies.
The course will be conducted in terms of actual participation in Research and Development Work. Each
student will be assigned to a faculty member to work on specified projects. The student will be required
to present many seminars in his research area in a structured manner.
3
CS G553 Reconfigurable Computing [5]
Overview of Programmable Logics. FPGA fabric architectures. Logic Elements and Switch Networks.
Design and Synthesis of Combinational and Sequential Elements. Placement and Routing. Pipelining
and other Design Methodologies. Fine-grained and Coarse-Grained FPGAs. Static and Dynamic
Reconfiguration. Partitioning. Hardware/Software Portioning and Partial Evaluation. Systolic
Architectures.
Overview, history and industry perspective; working principles; mechanics and dynamics, thermofluid
engineering; scaling law; microactuators, microsensors and microelectromechanical systems;
microsystem design, modeling and simulation; materials; packaging; microfabrication: bulk, surface,
LIGA, etc; micromanufacturing; microfluidics; micro-robotics; case studies.
Introduction; design of analog filters; design of digital filters: (IIR and FIR); structures for the
realization of digital filters; random signals and random processes; linear estimation and prediction;
Wiener filters; DSP processor architecture; DSP algorithms for different applications.
Review of stochastic processes, models and model classification, the identification problem, some field
of applications, classical methods of identification of impulse response and transfer function models,
model learning techniques, linear least square estimator, minimum variance algorithm, stochastic
approximation method and maximum likelihood method, simultaneous state and parameter estimation
of extended Kalman-filter, non-linear identification, quasi linearization, numerical identification
methods.
This course deals with the three main application areas of Network Embedded Systems – Wireless
Sensor Networks, Automotive Networks, and Industrial Networks– Network Architecture, Deployment
Issues, Network Protocol stack: Modular and Cross-Layer Design. Network Node: Architectures,
Operating Systems, and Applications. Middleware Issues and Design. Security and Encryption
Introduction to NMOS and CMOS circuits; NMOS and CMOS processing technology; CMOS circuits
and logic design; circuit characterization and performance estimation; structured design and testing;
symbolic layout systems; CMOS subsystem design; system case studies.
Deep submicron device behavior and models, Interconnect modeling for parasitic estimation, Clock
signals and system timing--Digital phase-locked loop design, memory, and array structures,
Input/output circuits design, ASIC technology, FPGA technology, High-speed arithmetic circuits
design,-Parallel prefix computation, Logical effort in circuit design, Low power VLSI circuits-
Adiabatic logic circuits, Multi threshold circuits, Digital BICMOS circuits, Design of VLSI systems.
4
MEL G624 Advanced VLSI Architectures [5]
Instruction set design and architecture of programmable DSP architectures; dedicated DSP architectures
for filters and FFTs; DSP transformation and their use in DSP architecture design; Application Specific
Instruction set Processor; superscalar and VLIW architectures.
Concepts of measurement of electrical and nonelectrical parameters; displacement, force, pressure, etc.
and related signal conditioning techniques, drives and actuators, concepts of
microprocessors/microcontrollers architecture and programming, memory, and I/O interfacing. System
design concepts through case studies.
Sampling process, representation of discrete-time signals, use of transforms in signal spectrum analysis,
Fourier transform, fast Fourier transform, Z transform, the realization of filters, recursive and
nonrecursive filters, effects of quantization and finite word length, hardware implementation