Advantage and disadvantage of RISC== Advantage 1.

Faster execution speed RISC processors

use the simpler instructions that can be executed more quickly leading to improved overall
performance inthe many tasks. 2.Lower power consumption The simpler design of a RISC
processors often results in the lower power usage making them the ideal for mobile devices and
energy efficient computing. 3. Easier to design and manufacture RISC processors have a simpler
architecture which can make them the easier and potentially cheaper to design and produce.

Disadvantage== Larger code size RISC processors often require more lines of code to perform
complex tasks, which can lead to larger program sizes and increased memory usage. 2.More work
for compilers The simpler instruction set means compilers for RISC processors need to do more work
to translate high-level programming languages into machine code. 3.Limited built-in functionality
RISC processors have fewer complex instructions built into hardware, which can make certain
specialized tasks less efficient without additional software support.

Advantage and disadvantage of CISC == ADVANTAGE 1.Smaller code size CISC processors can
perform complex operations with single instructions, often resulting in more compact code and
reduced memory usage. 2.Rich instruction set The diverse set of complex instructions can make
programming easier and more intuitive for certain tasks, especially in assembly language.
3.Backwards compatibility CISC architectures, like x86, often maintain compatibility with older
software, making system upgrades easier for users and businesses.

Disadvantage== Slower execution speed Complex instructions typically take longer to execute,
potentially resulting in slower overall performance compared to RISC processors. 2.Higher power
consumption The more complex hardware required for the CISC processors often leads to a
increased power usage making them less suitable for the mobile devices. 3.More complex
hardware design a CISC processors require more complex circuitry to handle their varied the
instructions which can make them a more challenging and expensive to design and manufacture.

Basic features of RISC processor ==

8255 PPI== PPI 8255 is a general purpose programmable I/O device designed to interface the CPU
with its outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor. It consists of three 8-bit bidirectional I/O
ports i.e. PORT A, PORT B and PORT C. We can assign different ports as input or output.

8257 DMA Controller== DMA stands for Direct Memory Access. It is designed by Intel to transfer
data at the fastest rate. It allows the device to transfer the data directly to/from memory without
any interference of the CPU. 2.Using a DMA controller, the device requests the CPU to hold its data,
address and control bus, so the device is free to transfer data directly to/from the memory. The
DMA data transfer is initiated only after receiving HLDA signal from the CPU.

Features of 8257== It has four channels which can be used over four I/O devices. 2.Each channel
has 16-bit address and 14-bit counter. 3.Each channel can transfer data up to 64kb. 3.Each
channel can be programmed independently. 4.Each channel can perform read transfer, write
transfer and verify transfer operations. 5.It generates MARK signal to the peripheral device that
128 bytes have been transferred. 6. It requires a single phase clock. 7.Its frequency ranges from
250Hz to 3MHz. 8.It operates in 2 modes, i.e., Master mode and Slave mode.

8259 PIC microcontroller=== Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5
hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086 microprocessors
respectively. But by connecting Intel 8259 with these microprocessors, we can increase their
interrupt handling capability. Intel 8259 combines the multi-interrupt input sources into a single
interrupt output. Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example,
Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessor
from 5 to 8 interrupt levels.

Features of intel 8259 PIC=== Features of Intel 8259 PIC are as follows: 1.Intel 8259 is designed
for Intel 8085 and Intel 8086 microprocessor. 2.It can be programmed either in level triggered or
in edge triggered interrupt level. 3.We can mask individual bits of interrupt request register.
4.We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259
PICs. 5.Clock cycle is not required.

Logical operation== CMP : Compare contents of register or memory with accumulator by

performing subtraction. Eg: CMP B.CPI : Compare immediate data with accumulator. Eg: CPI
45.ANA : Logical AND register or memory with accumulator. Eg: ANA B.RLC : Each bit of accumulator
is rotated left by one position. CY is modified according to bit D7 and remaining not affected.RRC :
Each bit of accumulator is rotated right by one position. CY is modified according to bit D0 and
remaining not affected.RAL : Each bit of accumulator is rotated left through carry flag. Bit D7 is
placed in carry flag and carry flag is placed at D0. Remaining flag are not modified.RAR : Each bit of
accumulator is rotated right through carry flag. Bit D0 is placed in carry flag and carry flag is placed at
D7. Remaining flag are not modified.CMA : The contents of accumulator are complemented. This
means 0 is changed to 1 or vice-versa.
Addressing modes:==The way of specifying data to be operated by an instruction is called addressing
mode. Types of addressing modes –
In 8085 microprocessor there are 5 types of addressing modes:Immediate Addressing
Mode ,Register Addressing Mode ,Direct Addressing Mode ,Register Indirect Addressing
Mode,Implied/Implicit Addressing Mode

1>immediate Addressing mode:==In immediate addressing mode the source operand is always data.
If the data is 8-bit, then the instruction will be of 2 bytes, if the data is of 16-bit then the instruction
will be of 3 bytes. Examples:
MVI B, 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)

2>register addressing mode:==In register addressing mode, the data to be operated is available
inside the register(s) and register(s) is(are) operands. Therefore the operation is performed within
various registers of the microprocessor. Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)

3>Direct Addressing mode:== In direct addressing mode, the data to be operated is available inside
a memory location and that memory location is directly specified as an operand. The operand is
directly available in the instruction itself.Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)

4> Register Indirect Addressing:== In register indirect addressing mode, the data to be operated is
available inside a memory location and that memory location is indirectly specified by a register
pair. Examples: MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contents of B-C register to the accumulator)
STAX B (store accumulator contents in memory pointed by register pair B-C)

5.Implied /Implicit Addressing Mode== In implied/implicit addressing mode the operand is hidden
and the data to be operated is available in the instruction itself. Examples:
CMA (finds and stores the 1’s complement of the contents of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
OPCODE FETCH==

MEMORY READ CYCLE:==