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Lab3

This document outlines Lab 3 of the Digital Logic Design Laboratory, focusing on MSI Combinational Logic. Students will learn to design and simulate various combinational circuits, including half and full adders, priority encoders, and decoders using specific integrated circuits. The lab includes objectives, procedures, and tasks that require students to implement circuits via simulation software and analyze the results.

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Lý Khải Minh
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3 views

Lab3

This document outlines Lab 3 of the Digital Logic Design Laboratory, focusing on MSI Combinational Logic. Students will learn to design and simulate various combinational circuits, including half and full adders, priority encoders, and decoders using specific integrated circuits. The lab includes objectives, procedures, and tasks that require students to implement circuits via simulation software and analyze the results.

Uploaded by

Lý Khải Minh
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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INTERNATIONAL UNIVERSITY

SCHOOL OF ELECTRICAL ENGINEERING

Digital Logic Design Laboratory

Lab 3

MSI Combinational Logic (II)

Full name: …………………………………………….


Student number: ………………………………….
Class: ……………………………………………….......
Date: …………………………………………………....

Digital Logic Design Laboratory 1-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

I. Objectives

In this laboratory, students will study:


- Understand the operation of combinational logic circuit.
- The operation of some combinational ICs such as: full adder, decoder, encoder.

II. Procedure

1. Design the adder with two one-bit binary.


a. Design the half adder two one-bit binary.
Two inputs are A, B. Two outputs are S and C.
Build the truth table and the expressions

The simplified expressions:

Implement the circuit via simulation software and paste the result in here

Make comment on the results

Digital Logic Design Laboratory 2-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

b. Design the full adder two one-bit binary.


Three inputs are Cin, A, B. Two outputs are S and Cout.
Build the truth table and the expressions

The simplified expressions:

Implement the circuit via simulation software and paste the result in here

Make comment on the results

2. 8-to-3 Priority Encoder (Interrupt sorter) – IC 74HC148


a. Investigate IC – 74HC148
Construct the circuit as below:

Digital Logic Design Laboratory 3-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Figure 1 – Encoder 8-to-3 IC 74LS148

- The outputs are connected to LED displays to determine the logic levels.
- Choose the input data D0 - D7 by switches in the order from SW0 to SW7.
- Control EI by using switch.
- Observe the results and fulfill the truth table of 74HC148.

- What are the functions of GS and EO ?

Input Output
EI D0 D1 D2 D3 D4 D5 D6 D7 GS A2 A1 A0 E0
1 X X X X X X X X
0 1 1 1 1 1 1 1 1
0 X X X X X X X 0
0 X X X X X X 0 1
0 X X X X X 0 1 1
0 X X X X 0 1 1 1
0 X X X 0 1 1 1 1
0 X X 0 1 1 1 1 1
0 X 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1

Implement the circuit via simulation software and paste the result in here

b. Priority encoder

Digital Logic Design Laboratory 4-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Let’s EI equal to 0, fill the outputs A2, A1, A0 in the following cases
A2 A1 A0
Case 1:
I3 = I2 = I1 = 0
I7 = I6 = I5 = I4 = I0 = 1.

Case 2:
I7 = I2 = 0.
I6 = I5 = I4 = I3 = I1= I0 =1

Case 3:
All 8 inputs are equal to 0.

Case 1:
Implement the circuit via simulation software and paste the result in here

Make comment on results


_____________________________________________________________________
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Case 2:
Implement the circuit via simulation software and paste the result in here

Make comment on results


_____________________________________________________________________
_____________________________________________________________________

Case 3:
Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 5-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Make comment on results


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_____________________________________________________________________

3. 2-to-4 Decoder - IC74HC139


Construct the circuit as below:

Figure 2 – Decoder 2-line-to-4-line IC 74HC139

- 4 outputs (Y0-Y3) are connected to LED display (Led 1-4).


- The data inputs (A, B) and control input (G) are connected to switches.
- Change the states of inputs to fulfill the truth table of IC 74HC139.

Inputs
Outputs
Control Data
G B A Y0 Y1 Y2 Y3
0 0 0
0 0 1
0 1 0
0 1 1
1 X X

Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 6-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Briefly describe the operation of the IC

4. 3-TO-8 Decoder– IC 74HC138


Construct the circuit as below:

Figure 3 – 3-to-8 Decoder/demultiplexer - IC 74HC138

- 8 outputs are connected by using LEDs.


- The inputs are controlled by switches.
- Observe the results and fulfill the truth table

INPUT OUTPUT
E3 E2 E1 C B A Y0 Y1 Y2 Y 3 Y4 Y 5 Y 6 Y7
1 0 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
0 X X X X X
X 1 X X X X
X X 1 X X X

Digital Logic Design Laboratory 7-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Implement the circuit via simulation software and paste the result in here

Briefly describe the operation of the IC

5. Design combinational circuits using decoders and OR gate


- Implement Boolean expression using IC 74HC138 & OR gate.
- The data inputs A, B, C are connected to switches.
- The control inputs are in suitable levels.
- Implement the circuit and verify the truth table

a. f =x ' y z ' + xz
Establish the truth table

Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 8-9


INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Verify the truth table and make comment on the results

b. f =x ' yz + x + y ' z '


Establish the truth table

Implement the circuit via simulation software and paste the result in here

Verify the truth table and make comment on the results

Digital Logic Design Laboratory 9-9

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