An Efficient BIST Architecture for Embedded RAMs

Youngkyu Park , Jaeseok Park, and Sungho Kang

Department of Electrical & Electronic Engineering
Yonsei University
Seoul, Korea
{hipyk, bbajaepjs}@soc.yonsei.ac.kr, [email protected]

embedded memory. The objectives of embedded memory test

Abstract - In this paper, a new BIST(Built-In Self-Test)
design and the benefits of various test approaches are
structure for efficient test of embedded RAMs is proposed. In
summarized in [1]. Deterministic BIST is presented as the
proposed embedded memory BIST(EMBIST) architecture,
most efficient solution when at-speed coverage and tester
various algorithms are allowed to be executed, and just one
memory requirements are considered. While in [1]
controller can test more than one embedded memories. And,
deterministic BIST approach is identified to be the most
the proposed EMBIST has efficient structure that requires
effective scheme, the MBIST engine proposed by the author
smaller hardware overhead. The experimental result
supports only predefined algorithms and does not provide the
demonstrates the effectiveness of proposed EMBIST
flexibility that a direct access scheme would have provided.
architecture.
The correlation between the functional fault coverage and
defect coverage for a particular array topology is investigated
1. Introduction in [2]. The authors have shown the correlation between the
As current System-on-Chip(SOC) designs become memory layout of an array and the fault coverage levels for various
intensive, the manufacturing yield of such devices greatly fault models, such as stuck-at, transition, stuck open, coupling
depends on the yield of embedded memories. The embedded and data retention faults. As an extension to this work,
memory takes 80%~90% of the total SoC transistors and dynamic fault models are defined in [3]. The authors analyzed
testing embedded memory has become a significant issue in the dynamic fault coverage of the industry standard algorithms
developing SOC. Currently, the most widely used method for and proposed two new test algorithms to overcome the
testing embedded memory is the Built-In Self-Test(BIST) deficiencies of the standard algorithms.
method[1][2]. The Memory BIST method performs the self-test
by the built-in test circuiting inside the chip. Therefore it
carries certain overheads such as larger internal area. However, 3. Proposed EMBIST Architecture
the self-test are performed to each module, which simplifies The proposed structure of the memory BIST for testing the
the complexity of these tests. Also, due to the fact that fast embedded memory is consisted of the following components.
tests can be carried out without the need for expensive There is the EMBIST controller that generates the addresses
external testing devices, the BIST method is very widely used and the control signals. And there is a pattern generator for
for embedded memory test. generating data patterns. Also, it is composed of a response
The memory BIST consideration is that many functional analyzer that compares the test results. The EMBIST
faults may exist in memories, including the address decoder controller controls the memory BIST, and generates the
fault(AF), stuck-at fault(SAF), transition fault(TF), stuck open control signals that are needed during testing memories. In
fault(SOF), coupling fault(CF) and data retention fault(DRF) addition, the EMBIST controller generates the memory
[3]
. One single March algorithm can only test a subset of the addresses in the memory tests. The pattern generator generates
memory faults. In the embedded memory, in order to obtain the data patterns during memory tests. The response analyzer
high fault coverage, multiple March algorithms are usually compares between the output data and the expected data for
required [4]. The conventional BIST controller based on the determining if the faults exist or not. The Figure 1 shows this
finite state machines (FSM)[5][6] is not flexible to integrate embedded memory BIST(EMBIST) architecture.
multiple test algorithms.
This paper proposes a new memory BIST architecture, 3.1. EMBIST controller
embedded memory BIST(EMBIST), to test various kinds of
EMBIST controller controls the operation of each memory
memories efficiently. It is the efficient structure that can
BIST module during the test process. This module determines
execute plural different kinds of test algorithms at once. At
the starting and the ending positions of the test process. Also it
most, a large number of memory BIST can be controlled by a
ensures the running of test cycles by approving the signals to
single BIST controller
each module. EMBIST controller sends the BIST_control
signal to the pattern generator that generates the data patterns,
which correspond to each March element that forms the
2. Previous Work algorithm. Also, the EMBIST controller ensures the data
Several approaches, such as functional test, direct access pattern performs the read/write operations at the correct
test, random BIST and deterministic BIST exist for the test of address of the memory.

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 completed in two cycles. However, since the maximum cycle
is three for read-write-read operation, one dummy cycle is
added as shown in Figure 2.

Figure 2: Read operation of embedded memory

Figure 1: EMBIST Architecture In Figure 3, the actual write operation can be completed in
two cycles. The Figure 4 shows read/write operation timing
Furthermore, the Read_enable control signal is approved for the EMBIST. The clocks are falling edge-triggered signals
for the response analyzer, through which faults are verified. It and the enable signals (Read Enable and Write Enable) are
also generates the control signals of the memory BIST that are active high. In this figure, notice that there may not be enough
needed during the memory tests. time to compare the output data with the expected data within
the read cycle. Therefore, the “compare” operation should be
3.2. Pattern generator done in the next cycle.
Pattern generator module generates the data patterns by the
BIST_signal control signal of the EMBIST controller. It
generates the background data or the test data for the memory
test.

3.3. Address generator

Address generator module generates address signals for
read/write operations on exactly required positions. This
address value is generated by increasing or decreasing from 0
to the last address value. Figure 3: Write operation of embedded memory

3.4. Response analyzer

Response analyzer module compares the output values
read from the memory with the expected values generated
from data generator. The Read_enable control signal, through
which output values are read from the memory, is received
from the EMBIST controller. These read values are compared
with the generated expected values in the pattern generator to
detect for faults. Then the final test results are sent to
EMBIST controller.

The March algorithms are composed of read and write

operations. In this paper, read-write-read operation is defined Figure 4: Read-Write operation of embedded memory
as well as single read/write operations for the case where
serial read, write and read operations are needed.
Figure 2, Figure 3, and Figure 4 show the timing diagrams 4. EMBIST Function
for memory read, write and read-write-read operations of The proposed EMBIST has the following three functions.
embedded memory. Note that the maximum cycles for all It is possible that EMBIST accomplishes more than one test
three operations are three for memory read-write-read algorithms, not only one algorithm. The test result has quite
operation as shown in Figure 4. In EMBIST, the maximum high fault coverage because the various plural algorithms can
cycle is used as the reference cycle for each of the memory be selected. But, increasing the number of algorithms in
operations. In Figure 2, the actual read operation can be

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EMBIST makes FSM bigger, and then it makes the hardware
overhead larger.
Just one EMBIST controller can test many kinds of
embedded memories in the proposed architecture. A single
MBIST is able to test the memories which have different size
and characteristics at once. So, it gets smaller hardware
overhead, and the test time is reduced.
The proposed EMBIST has two optional modes, bypass
mode and isolation mode, for guaranteeing controllability and
observability of I/O line. The following parts indicate what the
each modes are.

4.1. Bypass mode

With the bypass mode option, the input data lines of a
memory block are bypassed to their corresponding output data Figure 6:Only_mode of isolation
lines using multiplexors. Using this option will increase the
controllability and observability of the data lines. Note that
Figure 7 shows the isolation ring with both_mode, where
this option is not applicable to address and control lines.
both observation and control scan flip-flops are inserted by
Figure 5 shows a example of bypass mode of memory data
using the combination of Test_mode signal and MTestH
signals. If the data output signals are tri-state, then additional
signal.
scan flip-flops and AND gates are needed to control the tri-
state bypass mode. However, if the tri-state data output signals
are not connected to external bus structures, Figure 5-(a) can
be used instead of Figure 5-(b).

(a) Two-state memory output (b) tri-state memory output

Figure 5: Memory bypass mode diagram

4.2. Isolation mode

The isolation mode option is to create logic circuits to
isolate a memory block from the surrounding logic circuits of
a memory block. The isolation ring is composed of scan flip- Figure 7: Both_mode of isolation
flops which are connected as a scan chain. The isolation mode
has two options: only and both. The only_mode is to add
observation scan flip-flops for the input signals of a memory 5. Verification
block and to add control flip-flop for the output signals of a Design Complier from synopsys Inc. is used to verify the
memory block. And the both_mode is to add observation and EMBIST proposed in this paper. The process technology used
control scan flip-flops for both the input and output signals of for synthesis is TSMC0.25µm process. The BIST clock of the
a memory block. EMBIST for testing 128M bits embedded memory is targeted
Figure 6 shows an isolation ring for the only_mode. For on 333MHz and the Design Complier is used for synthesis.
the memory input signals except data bus signals, scan flip- The synthesis results are shown in the Table 1. The maximum
flops are inserted for observation points and the outputs of the frequency of EMBIST in the Table 1 is 386MHz and the cell
inserted scan flip-flops are connected to dummy output nodes. area is 32549. In order to compare with the existing BIST, the
The reason for connecting the dummy output nodes are to MBIST Architecture of Mentor Graphics Corp. is used to
prevent the dangling scan flip-flops from being removed by generate 128M bits embedded memory BIST. The generated
logic synthesis tools. For data bus signals, if the bypass mode BIST implements March C+. The BIST clock of the generated
is OFF, scan flip-flops are added for the data signals and the BIST for testing 128M bits embedded memory is targeted on
outputs of scan flip-flops are connected to multiplexors as 333MHz. The maximum frequency for the synthesis is
shown in Figure 6. If the bypass mode is ON, no scan flip- 338MHz and the cell area is 30159.
flops are inserted for data bus signals.

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 Table 1. Comparison of performances Chinese Institute of Electrical Engineering, Vol. 8, No. 4,
Test AlgorithmG MaximumG CellG pp. 387-394, Nov. 2001.
BISTG
AlgorithmG LengthG FrequencyG AreaG 6. C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y.
Chang, “A programmable BIST core for embedded
Mentor MBIST G March C+G 14NG 338MHzG 30159G
DRAM," IEEE Transactions on Design & Test of
EMBISTG March C+G 14NG 386MHzG 32549G Computers, Vol. 16, No. 1, pp. 59-70, Jan.-Mar. 1999.
7. C. Hunter, “Integrated diagnostics for embedded memory
In the March C+ algorithm environment, there are the two built-in self-test on PowerPCTM,” Proceeding of IEEE
main differences between proposed structure, EMBIST, and International Conference on Computer Design, pp. 549-
Mentor BIST. First, the proposed EMBIST is faster than 554, 1997.
Mentor MBIST by 48MHz comparing two different memory 8. V. K. Kim and T. Chen, “On comparing functional fault
BIST architectures. In the other hand, the cell area of coverage and defect coverage for memory testing,” IEEE
EMBIST has larger hardware overhead by 2390. But it comes Transactons on Computer-Aided Design of Integrated
from using both of two optional modes, bypass and isolation Circuits, vol. 18, No. 11, pp. 1676-1683, 1999
modes, which is supported by EMBIST. Therefore, the 9. S. Hamdioui, A. Al-Ars, and A. J. van de Goor, “Testing
hardware area should be smaller than that of Mentor MBIST if static and dynamic fault in random access memories,”
this option is removed. Proceeding of IEEE VLSI Test Symposium, pp. 395-400,
2002.
6. Conclusions
With the rapid growth of SOC (System-on-Chip), the
BIST is being widely used to increase the yield of the built-in
memories, which is a very important component in SOC. By
using the separate on-chip test logic, the memory test can be
performed to reduce the test time. Also it has the advantage of
being able to detect the faults at system operation speed.
The proposed EMBIST is a very efficient BIST structure
that is capable of detecting all faults in the embedded memory.
EMBIST enables efficient tests of the high-performance
embedded memories that are required essentially for the
computer system, and it reduces the test cost. Then, it
increases the fault coverage, and obtains high confidence.
Besides, EMBIST provides smallest hardware overhead by
organizing the system to control plural memories with a single
controller.

Acknowledgments
This work was supported by "System IC 2010" project of
Korea Ministry of Knowledge Economy.

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