INDIAN INSTITUTE OF INFORMATION TECHNOLOGY KOTTAYAM

Department of Electronics and Communication Engineering

Indian Institute of IEC 121 Digital Design and Electric Circuits
Information Technology
Repeat Examination, August 2023
Kottayam

Course Instructor: Dr. Milind Thomas Themalil

Time: 2:00 PM - 5:00 PM Semester II Max marks: 100
Answer all questions
Write necessary steps for each question

1. (a) The point P in the following figure is always 1. The output f will be
(5)

(b) Consider the unsigned 8-bit fixed point binary number representation below, (5)
b 7jb6b 5b 4£»3 • b 2b tb 0
where the position of the binary point is between b 3 and b2. Assume b 7is the most significant bit.
Which of the decimal numbers listed below cannot be represented exactly in the above representation?
Justify the choice(s) of your answer.
(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001

2. (a) Implement the following expression using NAND gates only (5)
Y = (a + c) (cT + ib_ + cf)
(b) A universal logic gate can implement any Boolean function by connecting sufficient number ofthem
appropriately. Check whether the logic gate shown below can function as a universal gateor not. If
yes, implement NOT, AND and OR gates using the same (assume uncomplementedinputs X and
Y , and binary inputs 0 and 1 are available). (5)

X F= X + Y
Y

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2 ^ Consider the num ber given by the decimal expression (5)
163 x 9 + 162 x 7 + 1 6 x 5 +3
The num ber o f l ’s in the unsigned binary representation o f the num ber is

Two num bers represented in signed 2 ’s com plem ent form are P = 11101101 and Q = (5)
(b)
11100110. If Q is subtracted from P, w hat is the value obtained in signed 2 ’s
com plem ent form?

4. For each o f the follow ing circuits, find the output Y .

( 10 )

<a)

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5. Design a sequence detector using Mealy model FSM which produces an output ‘1’ every time the
sequence 0101 is detected and an output ‘O’ otherwise. (10)

6. (a) The outputs ox the two flip-flops Q l, Q2 in the figure shown are initialized to 0, 0. Write the
sequencegenerated at Ql upon application of clock signal.

Q lJ
Qt J2 Q2
> >
K1 Q1 K2Q2
(51
CLK

Draw the timing diagram for V and Z for the circuit. Assume that the AND gate has a delay (5)
(k) o f lOnsand the OR gate has a delay of 5ns.

J---- u
—
X_ m ;
Y_
V i___i
i i i i
Z_ j ___i i___i
0 5 10 15 20 25 30 35 40 45 50 55 ?(ns)

7. For the function

f( a, b, c, d, e ) = I m (6, 7, 9, 11, 12, 13, 16, 17, 18, 20, 21, 23, 25, 28) , using a
Kamaughmap,

(a) Find the essential prime implicants (three).

(b) Find the minimum sum of products (7 terms).
(c) Find all of the prime implicants (twelve). (10)

8.P, Q and R are the decimal integers corresponding to the 4-bit binary number 1100 considered in
signed magnitude, l ’s complement and 2’s complement representations, respectively. Find the 6-bit
2 ’s complement representation of(P + Q + R).
( 10)

9. Use a 4-to-l multiplexer and a minimum number of external gates to realize the function F (w , X, y , Z) =
I m ( 3 , 4, 5, 7, 10, 14) + I d (1, 6, 15). The inputs are only available uncomplemented. (10)

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 (5)
1O.(a) Consider the Karnaugh map given below, where x represents “don’t care” and blank represents 0.

Assume
for r/r\ 00 01 11 10 au inpUts
b, c, d),
{a’ 00 X X
the respective
01 1 X

11 1 1
10 X X

complements (a, b, c, d) are also available. The above logic is implemented using 2-input NOR gates only. The
minimum number of gates required is _ ?

(b) Two 4-to-l multiplexers are connected as shown below. Express the output X as a sum of minterms. (5)

0 ----- 4-to-l 0 ----- h 4-to-l

1 ----- I. M l 'X 1 ----- 1UX
1 ----- 1 Y 1 ----- h Y
0 ----- h 0 ----- h
5, i S, s0
|

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