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Multiplexer and Demultiplexer

The document provides an overview of multiplexers and demultiplexers, detailing their functions, structures, and applications in digital logic circuits. It explains how multiplexers select binary information from multiple inputs to a single output, while demultiplexers route a single input to multiple outputs. Additionally, it includes examples of two-to-one and four-to-one multiplexers, as well as one-to-two and one-to-four demultiplexers, along with their truth tables and practical applications.

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2 views

Multiplexer and Demultiplexer

The document provides an overview of multiplexers and demultiplexers, detailing their functions, structures, and applications in digital logic circuits. It explains how multiplexers select binary information from multiple inputs to a single output, while demultiplexers route a single input to multiple outputs. Additionally, it includes examples of two-to-one and four-to-one multiplexers, as well as one-to-two and one-to-four demultiplexers, along with their truth tables and practical applications.

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gowthamachalla007
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Multiplexers and Demultiplexers

Dr. M Rambabu
Course Code: 24CSEN1001
Course Name: Digital Logic Circuits
Date: March 31, 2025

1 Multiplexer
A multiplexer is a combinational circuit that selects binary information from one of many input lines
and directs it to a single output line. The selection of a particular input line is controlled by a set
of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations
determine which input is selected.

1.1 Two-to-One-Line Multiplexer


A two-to-one-line multiplexer connects one of two 1-bit sources to a common destination, as shown
in Figure. 1. The circuit has two data input lines, one output line, and one selection line S.

Figure 1: Two-to-one-line muttlplexer.

ˆ When S = 0, the upper AND gate is enabled and I0 has a path to the output.

ˆ When S = 1, the lower AND gate is enabled and I1 has a path to the output.

The multiplexer acts like an electronic switch that selects one of two sources. The block diagram
of a multiplexer is sometimes depicted by a wedge-shaped symbol, as shown in Figure. 1(b). It
visually suggests how a selected input is directed into a single destination. The multiplexer is often
labeled “MUX” in block diagrams.

1.2 Four-to-One-Line Multiplexer


A four-to-one-line multiplexer is shown in Figure 2. Each of the four inputs, I0 through I3 , is applied
to one input of an AND gate. The selection lines S1 and S0 are decoded to select a particular AND
gate. The outputs of the gates are applied to a single OR gate that provides the one-line output.

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Figure 2: Four-to-one-line muttlplexer.

To demonstrate the operation of the circuit, consider the case when S1 S0 = 10. The AND gate
associated with input I2 has two of its inputs equal to 1 and the third input connected to I2 . The
other three AND gates have at least one input equal to 0, which makes their outputs equal to 0. The
output of the OR gate is now equal to the value of I2 , providing a path from the selected input to
the output.
A multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output line.

1.3 Implementation of Multiplexer


The AND gates and inverters in the multiplexer resemble a decoder circuit. In general, a 2n -to-1-line
multiplexer is constructed from an n-to-2n decoder by adding 2n input lines to it, one to each AND
gate. The outputs of the AND gates are applied to a single OR gate. The size of a multiplexer is
specified by the number 2n of its data input lines and the single output line. The n selection lines
are implied from the 2n data lines.
As in decoders, multiplexers may have an enable input to control the operation of the unit. When
the enable input is in the inactive state, the outputs are disabled. When it is in the active state, the
circuit functions as a normal multiplexer.

1.4 Multiplexers for Multiple-Bit Selection


Multiplexer circuits can be combined with common selection inputs to provide multiple-bit selection
logic. As an illustration, a quadruple 2-to-1-line multiplexer is shown in Figure. 3. The circuit has
four multiplexers, each capable of selecting one of two input lines.

ˆ Output Y0 can be selected from either input A0 or input B0 .

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Figure 3: Quadruple Two-to-one-line muttlplexer.

ˆ Similarly, output Y1 may have the value of A1 or B1 , and so on.

The input selection line S selects one of the lines in each of the four multiplexers. The enable
input E must be active (i.e., asserted) for normal operation. Although the circuit contains four
2-to-1-line multiplexers, we are more likely to view it as a circuit that selects one of two 4-bit sets of
data lines.
As shown in the function table, the unit is enabled when E = 0. Then, if S = 0, the four A
inputs have a path to the four outputs. By contrast, if S = 1, the four B inputs are applied to the
outputs. The outputs have all 0s when E = 1, regardless of the value of S.

2 Demultiplexers
A demultiplexer (DEMUX) is a combinational circuit that takes a single input and routes it to
one of several output lines. The specific output line to which the input is directed is determined by
a set of selection lines. A demultiplexer is the reverse of a multiplexer.

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2.1 One-to-Two-Line Demultiplexer
A one-to-two-line demultiplexer has one data input, one selection line, and two outputs. The selection
line determines which output receives the input signal. The circuit operation can be described as
follows:

ˆ When S = 0, the input D is directed to output Y0 , and Y1 is 0.

ˆ When S = 1, the input D is directed to output Y1 , and Y0 is 0.

The truth table for a one-to-two-line demultiplexer is given below:


Input (D) Selection (S) Output (Y0 ) Output (Y1 )
0 0 0 0
0 1 0 0
1 0 1 0
1 1 0 1

2.2 One-to-Four-Line Demultiplexer


A one-to-four-line demultiplexer expands the concept to four outputs and requires two selection lines,
S1 and S0 . The input D is routed to one of four outputs depending on the selection lines:

ˆ If S1 S0 = 00, D is directed to Y0 .

ˆ If S1 S0 = 01, D is directed to Y1 .

ˆ If S1 S0 = 10, D is directed to Y2 .

ˆ If S1 S0 = 11, D is directed to Y3 .

The truth table for a one-to-four-line demultiplexer is given below:

Input Select Lines Outputs


D S1 S0 Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0

Table 1: Truth Table of a 1-to-4 Demultiplexer

2.3 Implementation of Demultiplexer


A demultiplexer can be constructed using AND gates and inverters. Each output line is associated
with an AND gate that takes the input signal and is enabled by a specific combination of selection
lines.
For example, a one-to-four-line demultiplexer has the following Boolean equations for each output:
Y0 = D · S¯1 · S¯0
Y1 = D · S¯1 · S0
Y2 = D · S1 · S¯0
Y3 = D · S1 · S0

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2.4 Applications of Demultiplexers
Demultiplexers are widely used in digital electronics for various purposes, such as:

ˆ Data Routing: Directing data from a single source to multiple destinations.

ˆ Memory Addressing: Selecting specific memory locations in RAM.

ˆ Serial-to-Parallel Conversion: Converting serial data into parallel format for processing.

ˆ Communication Systems: Used in time-division multiplexing (TDM) to distribute signals.

2.5 Exercise for Students


Students are encouraged to design the corresponding circuit diagrams for both the one-to-two-line
and one-to-four-line demultiplexers and verify their truth tables as an exercise.

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