Electronic Devices & Circuits Lab

EE-208L
Lab Manual (Spring 2025)

University of Management & Technology

School of Engineering
Department of Electrical Engineering

Name : _____________________________
ID # : _____________________________
Section : _____________________________
 University of Management and Technology
School of Engineering
Department of Electrical Engineering

Course Outline Spring 2025

Course Code: EE-208L Course Title: Electronic Devices & Circuits Lab

Program BS-EE

Credit Hours 1

Contact Hours 3

One semester
Duration

EE-110 Circuit Analysis

Prerequisites

Resource Person Marium Shakil

Counseling Timing See Office Window (SEN-409)

Contact [email protected]

Chairman/Director signature………………………………….

Dean’s signature…………………………… Date………………………………………….

Learning Objective:
The lab deals with fundamental and practical aspect of Electronic Devices and Circuits. It is designed to
practically implement and observe the characteristics of Diodes, BJTs, MOSFETs, Operational
Amplifiers and their circuit applications. Simulations will also be part of the lab experiments. The
students will be required to prepare their lab manuals. Assessments based testing will be carried in final to
evaluate understanding of students.
Learning Methodology:

Practical, interactive, participative

Grade Evaluation Criteria

Following are the criteria for the distribution of marks to evaluate final grade in the semester.
Marks Evaluation Marks Percentage

Lab Manuals & Performance: 40

Open-Ended Lab 10

Term Project 10

Final Viva + Performance: 40

Total: 100

Recommended Text Books:

1. Fundamentals of Microelectronics by Behzad Razavi, second edition
2. Electronic Devices & Circuit Theory, Edition 11th by Robert L. Boylestad & Louis Nashelsky

Course Learning Outcomes (CLOs):

CLO 1: Reproduce different electronic circuits (with diodes/BJTs/MOSFETS/amplifiers) as per the

provided instructions, to measure the performance parameters.
CLO 2: Completes weekly lab tasks or/and the term project responsibly and effectively by fulfilling its
requirements.
 Relation to EE Program Learning Outcomes (PLOs):

Related Levels of
CLOs Teaching Methods CLO Attainment checked in
PLOs Learning
CLO 1 PLO 4 Psy-3 Instructions, Lab Work Lab Sessions, Exam

CLO 2 PLO 9 Aff-3 Instructions, Lab Work Lab Sessions, Exam

Calendar of Course contents to be covered during semester

Course Code: EE-208L Course Title: Electronic Devices & Circuits Lab

Week Course Contents / Lab Experiments CLOs

1 To study and analyze Diode Characteristics. 1

2 Implementation of Series and Parallel Diode Configuration. 1,2

3 Implementation of Half-Wave Rectification circuit 1,2

4 Implementation of Full-Wave Rectification circuit 1,2

5 To perform clipping using diode circuits. 1,2

6 To perform clamping using diode and capacitors 1,2

7 Implementation of Light-Emitting and Zener diode as clipper and 1,2

voltage regulator.
8 Implementation of Bipolar Junction Transistor (BJT) in circuits 1,2
to study their characteristics.

9 Implementation of Fixed and Voltage Divider Bias of BJTs 1,2

10 Open Ended Lab: Design light enabled switch using LDR and 1,2
Voltage divider bias of BJTs.

11 Performing Emitter and Collector Feedback Bias of BJTs. 1,2

12 Implementation of Common Emitter Amplifier Design 1,2

13 To study the VI characteristics of FET. 1,2

14 Implementing the Amplifier design. 1,2

15 A/D and D/A converter design using op amp. 1,2

16 Term Project Evaluation. 1,2

 Complex Engineering Problem/Activity:

Complex Engineering Problem

Included: No
Details

Complex Engineering Activity Included: Open Ended

Details Labs
 1
Name:
Date:
Instructor:

EXPERIMENT

Diode
Characteristics

OBJECTIVE

To calculate, compare, draw, and measure the characteristics of a silicon and

a germanium diode.

EQUIPMENT REQUIRED

Instruments
DMM

Components

Resist ors
(1) 1-kΩ

(1) 1-MΩ

Diodes
(1) Silicon

(1) Germanium

Supplies
DC power supply

Miscellaneous
Demonstration: 1 heat gun
EQUIPMENT ISSUED

Item Laboratory serial no.

DMM
DC power
supply

RESUME OF THEORY

Most modern-day digital multimeters can be used to determine the operating condition
of a diode. They have a scale denoted by a diode symbol that will indicate the condition of
a diode in the forward- and reverse-bias regions, connected to establish a forward-bias
condition, the meter will display the forward voltage across the diode at a current level
typically in the neighborhood of 2mA. If connected to establish a reverse-bias condition, a
"OL" should appear on the display to support the open-circuit approximation frequently
applied to this region. If the meter does not have the diode checking capability, the
condition of the diode can also be checked b obtaining some measure of the resistance
level in the forward- and reverse bias regions. Both techniques for checking a diode will
be introduced in the first part of the experiment.
The current-volt characteristics of a silicon or germanium diode have the
general shape shown in Fig. 1.1. Note the change in scale for both the vertical and
horizontal axes. In the reverse-biased region the reverse saturation currents are fairly
constant from 0 V to the Zener potential. In the forward-bias region the current increases
quite rapidly with increasing diode voltage. Note that the curves are rising almost
vertically at a forward-biased voltage of less than 1 V. The forward-biased diode current
will be limited solely by the network in which the diode is connected or by the maximum
current or power rating of the diode.

The "firing potential" or threshold voltage is determined by extending a straight line (dashed
lines c Fig. 1.1) tangent to the curves until it hit the horizontal axis The intersection with the VD
axis will determine the threshold voltage VT at which the current begins to rise rapidly.

Ge
ID (mA)

Si

VD (volts)

F i g u r e 1 - 1 Silicon and germanium diode

characteristics.

The DC or static resistance of a diode at any point on the characteristic is determined by the
ratio of the diode voltage at that point, divided by the diode current. That is

ohms
 Exp. 1 / Diode Characteristics

The AC resistance at a particular diode current or voltage can be determined using a

tangent line drawn as shown in Fig. 1.2. The resulting voltage (ΔV) and current (ΔI)

Ohms (1.2)
deviations can then be measured and the following equation applied.

The application of differential calculus shows that the AC resistance of a diode in the

Ohms Figure 1(-21.3)

vertical-rise section of the characteristics is given by

For levels of current at and below the knee of the curve, the AC resistance of a silicon
diode is better approximated by

(
rd=2 26mV )
ID
PROCEDURE
Part 1. Diode Test
Diode Testing Scale
The diode-testing scale of a DMM can be used to determine the operating condition of
a diode. With one polarity, the DMM should provide the "firing potential" of the diode,
while the reverse connection should result in an "OL" response to support the open-circuit
approximation.
Using the connections shown in Fig. 1.3, the constant-current source of about 2 mA
internal to the meter will forward bias the junction, and a voltage of about 0.7 V (700 mV)
will be obtained for silicon and 0.3 V (300 mV) for germanium. If the leads are reversed, an
OL indication will be obtained.
 Exp. 1 / Diode Characteristics

If a low reading (less than 1 V) is obtained in both directions, the junction is shorted
internally. If an OL indication is obtained in both directions, the junction is open.
Perform the tests of Table 1.1 for the silicon and germanium diodes.

Test Si Ge

Forward

Reverse

Based on the results of Table 1.1, are both diodes in good condition?

Resistance Scales
As indicated in the Resume of Theory section of this experiment, the condition of a diode
can also be checked using the resistance scales of a volt- ohm-meter (VOM) or digital meter.
Using the appropriate scales of the VOM or DMM, determine the resistance levels of the
forward- and reverse-bias regions of the Si and Ge diodes. Enter the results in Table 1.2.

Test Si Ge
Meter

Forward VO M

Reverse DMM

Although the firing potential is not revealed using the resistance scales, a "good" diode
will result in a lower resistance level in the forward bias state and a much higher resistance
level when reverse-biased.
Based on the results of Table 1.2, are both diodes in good condition?
 Exp. 1 / Diode Characteristics

Part 2. Forward-bias Diode Characteristics

In this part of the experiment we will obtain sufficient data to plot the forward-bias

characteristics of the silicon and germanium diodes on Fig. 1.5.

a. Construct the network of Fig. 1.4 with the supply (.E) set at 0 V. Record the
measured value of the resistor.
b. Increase the supply voltage E until V R {not E ) reads 0.1 V. Then measure V D
and insert its voltage in Table 1.3. Calculate the value of the corresponding
current I D using the equation shown in Table 2.3.

Table 1.3
VR(V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VD(V)
VR
lD= (mA)
Rmeas

VR(V) 0.9 1 2 3 4 5 6 7 8 9 10
VD(V)

VR
lD= (mA)

Rmeas

c. Repeat step b for the remaining settings of V R , using the equation

in Table 1.3.
d. Replace the silicon diode by a germanium diode and complete Table 1.4.

VR(V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

VD(V)
VR
lD= (mA)
Rmeas

VR(V) 0.9 1 2 3 4 5 6 7 8 9 10
VD(V)
VR
lD= (mA)
Rmeas
 Exp. 1 / Diode Characteristics

e. On Fig. 1.5, plot ID versus VD for the silicon and germanium diodes. Complete
the curves by extending the lower region of each curve
to the intersection of the axis at ID = 0 mA and VD = 0 V. Label each curve and
clearly indicate data points. Be neat!

f. How do the two curves differ? What are their similarities?

Figure 1-5

Part 3. Reverse Bias

a. In Fig. 1.6 a reverse-bias condition has been established. Since the reverse
saturation current will be relatively small, a large resistance of 1 MΩ is required if
the voltage across R is to be of measurable amplitude. Construct the circuit of Fig.
1 . 6 and record the measured value of R on the diagram.
 Exp. 1 / Diode Characteristics

Figure 1-6

b. Measure the voltage Calculate the reverse saturation current from

IS = VR/(RMEAS ||RM). The internal resistance (R M ) of the DMM is included because
of the large magnitude of the resistance R. Your instructor will provide the
internal resistance of the DMM for your calculations. If unavailable, use a typical
value of 10 MΩ.

Rm =

VR (measured) =

Is (calculated) =

c. Repeat Part 3(b) for the germanium diode.

VR (measured) =

IS (calculated) =

d. How do the resulting levels of IS for silicon and germanium compare?

e. Determine the DC resistance levels for the silicon and germanium diodes using
the equation

RDC = VD =
VD = E-VR
ID Is Is

RDC (calculated) (Si) =

 Exp. 1 / Diode Characteristics

RDC (calculated) (Ge) =

Are the resistance levels sufficiently high to be considered open- circuit

equivalents if appearing in series with resistors in the low kilohm range?

Part 4. DC Resistance

a. Using the Si curve of Fig. 1.5, determine the diode voltage a diode current levels
indicated in Table 1.5. Then determine the resistance at each current level. Show
all calculations.

Table 1.5

ID(mA) VD RDc
0.2
1
5
10

b. Repeat Part 4(a) for germanium and complete Table 1.6 (Table 1.6 is the same as
Table 1.5).

Table 1.6

ID(mA) VD RDc

0.2

10

c. Does the resistance (for Si and Ge) change as the diode cur increases and we move
up the vertical-rise section of characteristics?
 Exp. 1 / Diode Characteristics

Part 5. AC Resistance

a. Using the equation rd =ΔV/ΔI (Eq. 1.2), determine the resistance of the silicon
diode at I D = 9 mA using the curve of 1.5. Show all work.

rd (calculated) =

b. Determine the AC resistance at I D = 9 mA using the equation rd = 26 mV/ID(mA)

for the silicon diode. Show all work.

rd (calculated) =
How do the results of Parts 5 ( a ) and 5 (b) compare?

c. Repeat Part 5 ( a ) for I D = 2 m A for the silicon diode.

rd (calculated) =

d. Repeat Part 5 (b) for I D = 2 mA for the silicon diode. Use Eq. 1.4.

rd (calculated) =

How do the results of Parts 5 ( c ) and 5 (d) compare?

Part 6. Firing Potential

Graphically determine the firing potential (threshold voltage) of each diode from its characteristics
as defined in the Resume of Theory. Show the straight-line approximations on Fig. 1.5.
VT (silicon) =
VT (germanium) =
 Name
Date
Instructor

2
E X P E R I M E NT

Series
and Para lel
Diode
Configuration

OBJECTIVE

To analyze networks with diodes in a series or parallel configuration and to calculate andmeasure
the circuit voltages of various diode circuits.

EQUIPMENT REQUIRED

Instruments
DMM

Components Resistors
(1) 1-kΩ
(2) 2.2-kΩ

Diodes
(2) Silicon
(1) Germanium
Supplies
DC power supply

EQUIPMENT ISSUED
Item Laboratory
serial no.
DC power supply
DMM

25
 Exp. 2 26

RESUME OF THEORY
The analysis of circuits with diodes and a DC input requires that the state of the
diodes first be determined. For silicon diodes (with a transition voltage or "firing
potential" of 0.7 V), the voltage across the diode must be at least 0.7 V with the polarity
appearing in Fig. 2.1a for the diode to be in the "on” state. Once the voltage across the
diode reaches 0.7 V the diode will turn “on" and have the electrical equivalent of Fig.
2.1b. For V D < 0.7 V or for voltages with the opposite polarity of Fig. 2.1a, the diode
can be approximated as an open circuit. For germanium diodes, replace the transition
voltage germanium value of 0.3 V.

In most networks where the applied DC voltage exceeds the transition voltage of the
diodes, the state of the diode can usually be determine simply by mentally replacing the
diode by a resistor and determining the direction of current through the resistor. If the
direction matches the arrowhead diode symbol, the diode is in the "on" state, and if the
opposite, it is in the "off' state. Once the state is determined, simply replace the diode
transition voltage or open circuit and analyze the rest of the network.

(a) (b)

Figure 2-1 Forward-biased silicon diode.

Be alert to the location of the output voltage V o = V R = I R R . T h i s i s
particularly helpful in situations where a diode is in an open condition and the current
is zero. For I R = 0, V o = V R = I R R = 0(R) =0V.In addition, an open circuit can
have a voltage across it, but the current is zero Further, a short circuit has a zero-volt
drop across it, but the current is limited only by the external network or limitations of
the diode.
The analysis of logic gates requires that one make an assumption the state of the diodes,
determine the various voltage levels, and then determine whether the results violate
any basic laws, such as that a point in a network (such as V o ) can have only one voltage
level. It is usually helpful to keep in mind that there must be a forward-bias voltage
across a diode to the transition voltage to turn it "on." Once V o is determined and no
laws are violated with the diodes in their assumed state, a solution configuration can be
assumed.

PROCEDURE
Exp. 2 27

Part 1. Threshold Voltage VT

For both the silicon and the germanium diode, determine the threshold using the
diode-checking capability of the DMM or a curve tracer. For this experiment the "firing
voltages" obtained will establish the equivalent characteristics for each diode appearing
in Fig. 2.2. Record the of VT

obtained for each diode in Fig. 2.2. If

the diode-checking capability or curve
tracer is unavailable, assume VT = 0.7
V for silicon and VT = 0.3 V for
germanium.

F i g u r e 2 - 2 Firing voltage for silicon and germanium.

Part 2. Series Configuration

a. Construct the circuit of Fig. 2.3. Record the measured value of R.

Figure 2-3

b. Using the firing voltages of the silicon and germanium diodes as measured in Part 1 and the
measured resistance for R, calculate the theoretical values of Vo and ID. Insert the level of
VT for VD.

VD=
V0 (calculated) =
ID (calculated) =

c. Measure the voltages VD and Vo, using the DMM. Calculate the current ID from measured
values. Compare with the results of Part 2( b ) .
Exp. 2 28

VD (measured) =
Vo (measured) =
ID (from measured)=Vo/R2=

+Vd_

d . Construct the circuit of Fig. 2.4. Record the measured value each resistor.

e . Using the measured values of VD and Vo from Part 1 and the measured resistance
values for R1 and R2, calculate the theoretical values of Vo and ID. Insert the level of VT
for VD.

VD (measured) =

Vo (measured) =
ID (from measured) =

f. Measure the voltages VD and V0, using the DMM. Calculate current ID from measured values.
Compare with the results of step 2 ( e ) .

VD (measured) =

V0 (measured) =
ID (from measured) = Vo/R2 =

g. Reverse the silicon diode in Fig. 2.4 and calculate the theoretical values of VD, V0, and ID.
Exp. 2 29

VD =

Vo (calculated) =
ID (calculated) = Vo/R2 =

h . Measure VD and Vo for the conditions of Part 2( g ) . Calculate the current from
measured values. Compare with the results of Part 2( g ) .

VD (measured) =

Vo (measured) =
ID (from measured) = Vo/R2 =

Figure 2-5
i . Construct the network of Fig. 2.5. Record the measured value of R.

j . Using the firing voltages of the silicon and germanium diodes as measured in Part 1,
calculate the theoretical values of V1 (across both diodes), Vo, and ID.

V1 (calculated) =
 Exp. 2 30

Vo (calculated) =

ID (calculated) =

k . Measure V1 and Vo, and compare to the results of Part 2(j). Calculate the current ID
from measured values and compare to the level of Part 2(j).

V1 (measured) =

Vo (measured) =
ID ( from measured) =Vo/R=
:

Part 3. Parallel Configuration

a. Construct the network of Fig. 2.6. Record the measured value of R

Figure 2-6

b. Using the firing voltages of the silicon and germanium diodes as

measured in Part 1, calculate the theoretical values of Vo and VR.

Vo (calculated) =

VR (calculated) =
c. Measure Vo and VR and compare with the results of Part 3(b).

Vo (measured) =
VR (measured) =

d. Construct the network of Fig. 2.7. Record the measured value of: each
resistor.
Exp. 2 31

e. Using the firing voltages of the silicon diode as measured in Part1,

calculate the theoretical values of Vo, VR , and ID.

Vo (calculated) =
VR1 (calculated) =
ID (calculated) =

f. Measure Vo and VR1 . Using the measured values of Vo and VR1

calculate IR1 and IR2 and determine ID. Compare to the results of
Part 3(e).

Vo (measured) =

VR1(measured) =

ID (from measured) =

g. Construct the network of Fig. 2.8. Record the measured value of the
resistor.

Figure 2-8

h.Using the firing voltages of the silicon and germanium diodes as

measured in Part 1, calculate the theoretical values of Vo and VR.

Vo (calculated) =
Exp. 2 32

VR (calculated) =
i. Measure Vo and VR and compare with the results of Part 3(h).

Vo(measured) =
VR (measured) =
 Name:
Date:
Instructor:

Experiment

3
Half-Wave
Rectification

OBJECTIVE
To calculate, draw, and measure the DC output voltages of half-wave rectifier
circuits.

EQUIPMENT REQUIRED
Instruments
Oscilloscope
DMM
Components
Resistors
(2) 2.2-kΩ
(1) 3.3-kΩ

(4) Silicon Diodes

Supplies

Function generator

Miscellaneous

12.6-V center-tapped transformer with fused line cord

EQUIPMENT ISSUED
Item Laboratory serial no.

Oscilloscope

DMM

Function generator

RESUME OF THEORY
The primary function of half-wave rectification systems is to establish a DC level from a sinusoidal
input signal that has zero average (DC) level.
The half-wave voltage signal of Fig. 3.1, normally established by network with a single diode, has
an average or equivalent DC voltage level equal to 31.8% of the peak voltage Vm.
That is,

Vdc= 0.318Vpeakvolts (Half wave) (3.1)

For large sinusoidal inputs (Vm>>VT) the forward-biased transition voltage VT of a diode can be
ignored. However, for situations when the peak value of the sinusoidal signal is not that much
greater than VT, VT can have a noticeable effect on VDC.

Figure 3-1 Half-wave rectified signal

In rectification systems the peak inverse voltage (PIV) must be considered carefully. The PIV
voltage is the maximum reverse-bias voltage that a diode can handle before entering the Zener
breakdown region. For typical single-diode half-wave rectification systems, the required PIV level
is equal to the peak value of the applied sinusoidal signal.

PROCEDURE

PART 1. THRESHOLD VOLTAGE

Choose one of the four silicon diodes and determine the threshold voltage, VT, using the
diode-checking capability of the DMM or a curve tracer.
VT=
PART 2. HALF-WAVE RECTIFICATION
a. Construct the circuit of Fig. 3.2 using the chosen diode of Part 1. Record the measured
value of the resistance R. Set the function generator to a 1000-Hz 8-Vp.p sinusoidal

R(meas) =

Figure 3-2 Half-wave rectifier.

voltage using the oscilloscope.

b. Using the threshold voltage VT of Part 1, determine the theoretical output voltage VD for
the circuit of Fig. 3.2 and sketch the waveform on Fig. 3.3 for one full cycle using the
same sensitivities as those used for the input. Indicate the maximum and minimum values
on the output waveform.

Figure 3-3

c. Using the oscilloscope with the AC-GND-DC coupling switch in the DC position, obtain
the voltage vo and sketch the waveform on fig. 3.4. Before viewing vo be sure to set the v0
= 0 V line using the GND position of the coupling switch. Use the same sensitivities as in
Part 2(b).
 Figure 3-4

How do the results of Parts 2(b) and 2(c) compare?

d. Calculate the DC level of the half-wave rectified signal of Part 2(c) using eq.3.1

e. Measure the DC level of vo using the DC scale of the DMM and find the percentage
difference between the measured value and the calculated value of part2(d) using the
following equation:

% Difference = |VDC(calc) – VDC(meas)| / VDC(calc)

VDC (measured) =

(% Difference) =

f. Reverse the diode of Fig. 3.2 and sketch the output waveform obtained using the oscilloscope
on Fig. 3.5. Be sure the coupling switch is in the DC position and the v0 = OV line is preset
using the GND position. Include the maximum and minimum voltage levels on the plot as
determined using the chosen vertical sensitivity.
 Figure 3-5

g. Calculate and measure the DC level of the resulting waveform of Fig. 3.5. Insert the proper
sign for the polarity of as defined by Fig. 3.2 using Eq. 3.1.

VDC (calculated) =
VDC (measured) =
 Name:
Date:
Instructor:

Experiment

4
Full-Wave
Rectification

OBJECTIVE
To calculate, draw, and measure the DC output voltages of half-wave and full-wave
rectifier circuits.

EQUIPMENT REQUIRED
Instruments
Oscilloscope
DMM
Components
Resistors
(2) 2.2-kΩ
(1) 3.3-kΩ

(4) Silicon Diodes

Supplies

Function generator

Miscellaneous

12.6-V center-tapped transformer with fused line cord

EQUIPMENT ISSUED
Item Laboratory serial no.

Oscilloscope

DMM

Function generator

RESUME OF THEORY
The primary function of full-wave rectification systems is to establish a DC level from a sinusoidal
input signal that has zero average (DC) level.

The full-wave rectified signal of Fig. 4.1 has twice the average or DC level of the half-wave signal, or
63.6% of the peak value Vm. That is,

Vdc= 0.636Vpeakvolts (Full wave) (4.1)

For large sinusoidal inputs (Vm>>VT) the forward-biased transition voltage VT of a diode can be
ignored. However, for situations when the peak value of the sinusoidal signal is not that much
greater than VT, VT can have a noticeable effect on VDC.

F i g u r e 4 . 1 Full-wave rectified signal.

In rectification systems the peak inverse voltage (PIV) must be considered carefully. The PIV
voltage is the maximum reverse-bias voltage that a diode can handle before entering the Zener
breakdown region. For the four-diode full wave bridge rectification system, the required PIV level
is again the peak value, but for a two-diode center-tapped configuration, it is twice the peak value
of the applied signal.
PROCEDURE

PART 1. THRESHOLD VOLTAGE

Choose one of the four silicon diodes and determine the threshold voltage, VT, using the
diode-checking capability of the DMM or a curve tracer.
VT=
PART 2. FULL-WAVE RECTIFICATION (BRIDGE CONFIGURATION)
a. Construct the full-wave bridge rectifier of Fig. 4.2. Be sure that the diodes are inserted
correctly and that the grounding is as shown. If unsure, ask your instructor to check your
setup. Record the measured value of the resistor R.

Secondary

In addition, measure the rms voltage at the transformer secondary using the DMM set to AC.
Record that rms value below. Does it differ from the rated 12.6 V?

Vrms (measured) =

b. Calculate the peak value of the secondary voltage using the measured value (Vpeak =
1.414Vrms).

Vpeak (calculated) =

Figure 4.3
c. Using the VT of Part 1 for each diode, sketch the expected output waveform vo on Fig. 4.3.
Choose a vertical and a horizontal sensitivity based on the amplitude of the secondary
voltage. Consult your oscilloscope to obtain a list of possible sensitivities Record your
choice for each below.

Vertical Sensitivity = Horizontal Sensitivity =

d. Using the oscilloscope with the coupling switch in the DC position, obtain the waveform
for vo and record on Fig. 4.4. Use the vo = 0 V line using the GND position of the
coupling switch. Label the maximum and minimum values of the waveform using the
chosen vertical sensitivity. How do the waveforms of parts 2(c) and 2(d) compare?

Fig 4.4

e. Determine the DC level of the full-wave rectified waveform of Fig. 4.4

VDC (calculated) =

f. Measure the DC level of the output waveform using the DMM and calculate the percent
difference between the measured and calculated values.
 VDC (measured) =

(% Difference) =

PART 3. FULL-WAVE CENTER-TAPPED CONFIGURATION

a. Construct the network of Fig. 4.19. Record the measured value of the resistor R.

Measure the two secondary voltages of the transformer with the DMM set on AC.
Record below. Do they differ from the 6.3 V rating?

Vrms (measured) =
Vrms (measured) =

Using the average of the two rms readings, calculate the peak value of the overall
secondary voltage.

Vpeak (calculated) =

b. Using the VT of Part 1 for each diode, sketch the expected output waveform vo on Fig.
4.5. Choose a vertical and a horizontal sensitivity based on the amplitude of the
secondary voltage. Record your choice for each below.

Figure 4.5
 Vertical sensitivity =

Horizontal sensitivity =

c. Using the oscilloscope with the coupling switch in the DC position, obtain the
waveform for vo and record on Fig. 4.6. Use the same sensitivities employed in
Part 3(b) and be sure to preset the vo = 0 V line using the GND position of the
coupling switch. Label the maximum and minimum values of the waveform

Figure 4.6
using the chosen vertical sensitivity.

How do the waveforms of Figs. 4.5 and 4.6 compare?

d. Determine and compare the calculated and measured values of the DC level
associated with vo.

Calculated =

Measured =
 Name:
Date:
Instructor:

Experiment Clipping

5
Circuits

OBJECTIVE

To calculate, draw, and measure the output voltages of series and parallel clipping circuits

EQUIPMENT REQUIRED

Instruments
Oscilloscope
DMM
Components

Resistors
(1) 2.2-kΩ

Diode
(1) Silicon
(1) Germanium

Supplies
(1) 1.5-V D cell and holder
Function generator

EQUIPMENT ISSUED

Item Laboratory serial no.

Oscilloscope
DMM

Function generator

52
RESUME OF THEORY

The primary function of clippers is to "clip" away a portion of an applied

alternating signal. The process is typically performed by a resistor-diode
combination. DC batteries are used to provide additional shifts or “cuts” of the
applied voltage. The analysis of clippers with square-wave inputs is the easiest to
perform since there are only two levels of input voltage. Each can be treated as a
DC input and the output voltage for the corresponding time interval determined.
For sinusoidal and triangular inputs, various instantaneous values can be treated
as DC levels and the output level determined. Once a sufficient number of plot
points for the output voltage vo has been determined, it can be sketched in total.
Once the behavior of clippers is established, the effect of the placement of elements
in various positions can be predicted and the analysis completed.

PROCEDURE

Part1. Threshold Voltage

Determine the threshold voltage for the silicon and germanium diodes the
diode-checking capability of the DMM or a curve tracer. Round off to the
hundredths place when recording in the designated space below.

VT(Si) =
VT(Ge) =

Part 2. Parallel Clippers

a. Construct the clipping network of Fig. 5.1. Record the measured resistance
value and voltage of the D cell. Note that the input is an 8 Vp-p square wave at a
frequency of 1000 Hz.

Figure 5-1

b. Using the measured values of R, E, and VT, calculate the voltage VO when the
applied square wave is +4 V and -4 V. What is the level of VO? Show all the
steps of your calculations to determine V0.

VO (calculated) = VO (calculated) =
 c. Using the results of Parts 2(b), sketch the expected waveform for VO using the
horizontal axis of Fig. 5.2 as the VO = 0 V line. Use a vertical sensitivity of 1
V/cm and a horizontal sensitivity of 0.2 ms/cm.

Sketch of Vo
from
calculated
results

Figure 5-2

d. Using the sensitivities settings provided in Part 2(c), set the input square
wave and record VO on Fig. 5.3 using the oscilloscope. Be sure to preset the VO
= 0 V line using the GND position of the coupling switch (and the DC position
to view the waveform).

Sketch of V
o
from
measured
results:

Figure 5-3

How does the waveform of Fig. 5.3 compare with the predicted result of Fig.
5.2?
 e. Reverse the battery of Fig. 5.1 and, using the measured values of R, E, and VT,
calculate the level of V0 for the time interval when Vi = +4V and Vi = - 4 V.

Vo (calculated) = Vo (calculated) =

f. Using the results of Parts 2(e) and 2(f), sketch the expected waveform for VO
using the horizontal axis of Fig. 5.4 as the Vo= 0 V line. Use the same
sensitivities provided in Part 2(c).

Sketch of Vo from

calculated results:

Figure 5-4

g. Set the
input square wave and record VO on Fig. 5.5 using oscilloscope. Be sure to
preset the VO = 0 V line using the GND position of the coupling switch (and the
DC position to view the waveform).
How does the waveform of Fig. 5.4 compare with the predicted result of Fig.
5.5?

Sketch of Vo
from
measured
results:

Figure 5-5
 Part 3. Parallel Clippers (continued)
a. Construct the network of Fig. 5.6. Record the measured value of the resistance.
Note that the input is now a 4 Vp-p square wave at f= 1000 Hz.

Figure 5-6

b. Using the levels of VT determined in Part 1, calculate the level of VO for the
time interval when VT = +2 V.

VO (calculated) =

c. Repeat Part 3(b) for the time interval when VT = -2 V.

VO (calculated) =

d. Using the results of Parts 3(b) and 3(c), sketch the expected waveform for VO
using the horizontal axis of Fig. 5.7 as the VO = 0 V line. Insert your chosen
vertical and horizontal sensitivities below.

Vertical sensitivity =

Horizontal sensitivity =

Sketch of Vo from calculated

results:

Figure 5-7

e. Using the sensitivity settings chosen in Part 3(d), set the input square wave an
d
record VO on Fig.5.8 using the oscilloscope. Be sure to preset the VO = 0 V
line
 using the GND position of coupling switch (and the DC position to view the
waveform).

Sketch of Vo
from
measured results

Figure 5-8

How does the waveform of fig 5.8 compare with the predicted result of 5.7?

Part 4. Parallel Clippers (Sinusoidal Input)

a. Rebuild the circuit of Fig. 5.1 but change the input signal to an 8 Vp-p sinusoidal
signal with the same frequency (1000 Hz).
b. Using the results of Part 2 and any other analysis technique sketch the expected
output waveform for VO on Fig. 5.9. In particular, find VO when the applied signal is
at its positive and negative peak and zero volts. Also, list the chosen vertical and
horizontal sensitivities below:

Sketch of Vo
from
calculated
results:

Figure 5-9

VO (calculated) when Vi = +4 V =
VO (calculated) when Vi = -4 V =
VO (calculated) when V= 0 V =
 Vertical sensitivity =
Horizontal sensitivity =

c. Using the sensitivity settings chosen in Part 4(b), set the input sinusoidal
waveform and record VO on Fig. 5.10 using the oscilloscope. Be sure to preset the
VO = 0 V line using the GND position of the coupling switch.

Sketch of Vo
from
Measured
results

Figure 5-10

How does the waveform of Fig. 5.10 compare with the predicted result of Fig. 5.9?

Part 5. Series Clippers

a. Construct the circuit of Fig. 5.11. Record the measured resistance value and the
DC level of the D cell. The applied signal is an 8 Vp-p square wave at a frequency of
1000 Hz.

Figure 5-11

b. Using the measured values of R, E, and VT, calculate the voltage VO for the time
interval when Vi = +4 V.

VO (calculated) =

c. Repeat Part 5(b) for the time interval when Vi = -4 V.

VO (calculated) =
 d. Using the results of Parts 5(b) and 5(c), sketch the expected waveform for VO using
the horizontal axis of Fig. 5.12 as the 0 V line. Insert your chosen vertical and
horizontal sensitivity
settings below.

Sketch of Vo from
calculated results:

Figure 5-12

Vertical sensitivity =
Horizontal sensitivity =

e. Using the sensitivities chosen in Part 5(d), set the input square wave and record
VO on Fig. 5.13 using the oscilloscope. Be sure to preset the VO = 0 V line using the
GND position of the coupling switch (and the DC position to view the waveform).

Sketch of Vo
from
measured results:

Figure 5-13

How does the waveform of Fig. 5.13 compare with the predicted result of Part 5(d)?
 f. Reverse the battery of Fig. 5.11 and, using the measured values of R, E, and
VT, calculate the level of VO for the time interval when Vi = +4 V.

VO (calculated) =

g. Repeat Part 5(f) for the time interval when Vi = -4 V.

VO(calculated) =

h. Using the results of Parts 5(f) and 5(g), sketch the expected waveform for VO
using the horizontal axis of Fig. 5.14 as the VO = 0 V line. Use the following
sensitivities:

Vertical: 2 V/cm

Horizontal: 0.2 ms/cm

Sketch of Vo fromcalculated
results:
Figure 5-14

i. Using the sensitivities provided in Part 5(h), set the input square wave and
record VO on Fig. 5.15 using the oscilloscope. Be sure to preset the VO = 0 V line
using the GND position of the coupling switch (and the DC position to view the
waveform).

Sketch of Vo from measured result:

How does the waveform of Fig.

5.15 compare with the predicted
Figure 5-15
 pattern of Fig. 5.14?

Part 6. Series Clippers (Sinusoidal Input)

a. Rebuild the circuit of Fig. 5.11 but change the input signal to an 8 Vp.p sinusoidal
signal with the same frequency (1000 Hz).

b. Using the results of Part 5 and any other analysis technique, sketch the expected
output waveform for VO on Fig. 5.16. In particular, find VO when the applied signal
is at its positive and negative peak and zero volts. Use a vertical sensitivity of
1 V/cm and a horizontal sensitivity of 0.2 ms/cm.

Sketch of Vo from
calculated results:

Figure 5-16

VO (calculated) when Vi = +4 V =
V O (calculated) when Vi =-4V=
VO (calculated) when Vi = 0 V =

c. Using the sensitivities provided in Part 6(b), set the input sinusoidal waveform
and record VO on Fig. 5.17 using the oscilloscope. Be sure to preset the VO = 0 V line
using the GND position of the
coupling switch.

Sketch of Vo from
measured results:

Figure 5-17
How does the waveform of Fig. 5.17 compare with the
predicted result of Fig. 5.16?
 Name:
Date:
Instructor:

Experiment

6
Clamping
Circuits

OBJECTIVE
To calculate, draw, and measure the output voltage of clampers.

EQUIPMENT REQUIRED

Instruments
Oscilloscope
DMM

Components
Resistors

(1) 100-Ω
(1) 1-kΩ
(1) 100-kΩ
Diode

(1) Silicon

Capacitor

(1) 1µF

Supplies
(1) 1.5-V D cell and holder
(2) Function generator

66
Exp. 6 67

EQUIPMENT ISSUED
Item Laboratory serial no.
Oscilloscope
DMM

Function generator

RESUME OF THEORY
Clampers are designed to "clamp" an alternating input signal to a specific level
without altering the peak-to-peak characteristics of the waveform. Clampers are
easily distinguished from clippers in that they include capacitive element. A
typical clamper will include a capacitor, diode, and resistor, with some also having
a DC battery. The best approach to the analysis of clampers is to use a step-by-step
approach. The first step should be an examination of the network for that part of
the input signal that forward biases the diode. Choosing this part of the input
signal will save time and probably avoid some unnecessary confusion. With the
diode forward biased the voltage across the capacitor and across the output
terminals ca be determined. For the rest of the analysis it is then assumed that the
capacitor will hold on to the charge and voltage level established during this
interval of the input signal. The next part of the input signal can then be analyzed
to determine the effect of the stored voltage across the capacitor and the
open-circuit state of the diode on the output voltage.
The analysis of a clamper can be quickly checked by simply noting whether the
peak-to-peak voltage of the output signal is the same as the peak-to-peak voltage
of the applied signal. It is a characteristic of clamper that must be satisfied.

PROCEDURE
Part1 Threshold Voltage
Determine the threshold voltage for the silicon diode using the diode checking
capability of the DMM or a curve tracer. If either approach is unavailable assume
VT -=0.7 V.
VT =

Part 2. Clampers (R, C, Diode Combination)

a. Construct the network of Fig. 6.1 and record the measured value of R. Using
the value of VT from Part 1, calculate VC and Vo for the interval of that causes
the diode to be in the "on" state.

VC (calculated) =
VO (calculated) =

b. Using the
Exp. 6 68

results of Part 2(a), calculate the level of Vo after vi switches to the other leveland
turns the diode "off."

V0 (calculated) =

c. Using the results of Parts 2(a) and 2(b), sketch the expected waveform for Vo
in Fig. 6.2 for one full cycle of Vi. Use the horizontal center axis as the Vo = 0 V
line. Record the chosen vertical and horizontal sensitivities below:

Sketch of Vo from
calculated results:

Figure 6-2

Vertical sensitivity =
Horizontal sensitivity =
d. Using the sensitivities of Part 2(a), use the oscilloscope to view the output
waveform v0. Be sure to preset the Vo = 0 V line on the screen using the GND
position of the coupling switch (and the DC position to view the waveform).
Record the resulting waveform on Fig. 6.3.
How does the waveform of Fig. 6.3 compare with the expected waveform of Fig.
6.2?

Sketch of Vo from
measured results:

Figure 6-3
e. Revers
Exp. 6 69

VC (calculated) =
VO (calculated) =
f. Using the results of Part 2(e), calculate the level of VO after vi switches to the
other level and turns the diode "off."

V0 (calculated) =
g. Using the results of Parts 2(e) and 2(f), sketch the expected waveform for v
o on
Fig. 6.4. Use the horizontal axis as the VO = 0 V line. Record the chosen
vertical and horizontal sensitivities below:

Sketch of Vo from
calculated response:

Figure 6-4
Vertical sensitivity =
Horizontal sensitivity =

h. Using the sensitivities of Part 2(g), use the oscilloscope to view the output
waveform vo. Be sure to preset the VO = 0 V line on the screen using the GND
position of the coupling switch (and the DC position to view the waveform).
Record the resulting waveform on Fig. 6.5.

Sketch of Vo from

measured results:

How does the

Figure 6-5
Exp. 6 70

waveform of Fig. 6.5 compare with the expected waveform of Fig. 6.4?

Part 3. Clampers with a DC Battery

a. Construct the network of Fig. 6.6 and record the measured values of R and E.
Using the value of VT from Part 1, calculate VC and VO for the interval of vi that
causes the diode to be in the "on" state.

VC (calculated) = VO (calculated) =

b. Using the results of Part 3(a), calculate the level of vo after vi switches to the
other level and turns the diode "off."

VO (calculated) =

c. Using the results of Parts 3(a) and 3(b), sketch the expected waveform for vo
on Fig. 6.7. Use the horizontal center axis as the VO=0 V line. Record the
chosen vertical and horizontal sensitivities below:

Sketch of Vo fr
m
o

calculated results:

ertical
sensitivity =

Figure 6-7
Exp. 6 71

Horizontal sensitivity =

d. Using the sensitivities of Part 3(c), use the oscilloscope to view the output
waveform VO. Be sure to preset the VO = 0 V line on the screen using the GND
position of the coupling switch (and the DC position to view the waveform).
Record the resulting waveform on Fig. 6.8.

How does the waveform of Fig. 6.8 compare with the expected waveform of Fig.
6.7?

Sketch of Vo from
measured results:

Figure 6-8

e. Reverse the diode of Fig. 6.6 and, using the value of VT from Part 1, calculate
the levels of VC and VO for the interval of the input voltage vi that causes the
diode to be in the "on" state.

VC (calculated) =

VO (calculated) =

f. Using the results of Part 3(e), calculate the level of VO after vi switches to the
other level and turns the diode "off."

VO (calculated)
=

g. Using the results of Parts 3(e) and 3(f), sketch the expected waveform for vo on
Fig. 6.9. Use the horizontal center axis as the VO= 0 V line. Record the chosen
vertical and horizontal sensitivities below:

Vertical sensitivity =

Horizontal sensitivity =
Exp. 6 72

Sketch of Vo from
calculated results:

Figure 6-9

h. Using the sensitivities of Part 3(g), use the oscilloscope to view the output
waveform vo. Be sure to preset the VO = 0 V line on the screen using the GND
position of the coupling switch (and the DC position to view the waveform).
Record the resulting waveform on Fig. 6.10.

Sketch of Vo from
measured results:

Figure 6-10

How does the waveform of Fig. 6.10 compare with the expected waveform
of Fig. 6.9?

Part 4. Clampers (Sinusoidal Input)

a. Reconstruct the network of Fig. 6.1 but change the input signal to an
8 Vp-p sinusoidal signal with the same frequency (1000 Hz).

b. Using the results of Parts 1 and 2 and any other analysis technique at your
disposal, sketch the expected output waveform for VO on Fig. 6.11. In particular,
find VO when vi is its positive and negative peak value and when vi = 0 V. Record
the chosen vertical and horizontal sensitivities below:
Exp. 6 73

Sketch of Vo from
calculated results:

Figure 6-11

Vo(calculated) when Vi= +4 V is

VO(calculated) when VI = -4 V is
VO (calculated) when Vj = 0 V is
Vertical sensitivity =
Horizontal sensitivity =

c. Using the sensitivities of Part 4(b), use the oscilloscope to view the output
waveform VO. Be sure to preset the VO = 0 V line on the screen using the GND
position of the coupling switch (and the DC position to view the waveform).
Record the resulting waveform on Fig. 6.12.

Sketch of Vo from
measured results:

Figure 6-12

How does the waveform of Fig. 6.12 compare with the expected waveform of Fig. 6.11?
Exp. 6 74

Part 5. Clampers (Effect of R)

a. Determine the time constant (τ = RC) for the network of Fig. 6.1 for the
interval of the input signal that causes the diode to assume the "off” state and
be approximated by an open circuit.

τ (calculated) =

b. Calculate the period of the applied signal. Determine half the period to
correspond with the time interval that the diode is in the "off” state during the
first cycle of the applied signal.

T(calculated) = T/2 (calculated) =

c. The discharge period of an RC network is about 5τ. Calculate the time interval
established by 5τ using the result of Part 5(a) and compare to T/2 calculated in
Part 5(b).

5τ (calculated) =

d. For good clamping action, why is it important for the time interval specified
by 5τ to be much larger than T/2 of the applied signal?

e. Change R to 1 kΩ and calculate the new value of 5τ.

5 τ (calculated) =

f. How does the 5τ calculated in Part 5(e) compare to T/2 of the applied signal?
How would you expect the new value of R to affect the output waveform VO?

g. Set the input of Fig. 6.1 with R = 100Ω and record the resulting waveform on
Fig. 6.13. Be sure to preset the Vo = OV line in the center of the screen using
the GND position of the coupling switch and be sure to use the DC position to
view the waveform. Insert the chosen vertical and horizontal sensitivities
below:

Figure 6-13
Exp. 6 75

Vertical sensitivity = Horizontal sensitivity =

h. Comment on the resulting waveform of Fig. 6.13. Is the distortion as you

expected? Are you surprised by the positive and negative peaks? Why?

i. Change R to 100 Ω and calculate the new value of 5τ

5τ (calculated) =

j. How does the 5τ calculated in Part 5(i) compare to T/2 for the applied signal?
What effect will the lower value of R have on the waveform of Fig. 6.13?

k. Set the input of Fig. 6.1 with R = 100 Ω and record the resulting waveform on
Fig. 6.14. Be sure to preset the V0 =0 V line using the coupling switch and use
the DC position to view the waveform VO. Insert the chosen vertical and
horizontal sensitivities below:

Vertical sensitivity = Horizontal sensitivity =

Figure 6-14

l. Comment on the resulting waveform of Fig. 6.14. Compare it to the waveform

of Fig. 6.13 and the properly clamped waveform of Fig. 6.3.

m. Using the results of Parts 5(a) through 5(1), establish a relationship between5τ
and the period of the waveform (T) that will ensure that the output waveform
has the same characteristics as the input. Note that the requested
relationship is between 5τ and T and not T/2.
Exp. 6 76

Name:
Date:
Instructor:

Experiment Light-Emitting

7
and Zener
Diode

OBJECTIVE

To calculate, draw, and measure the currents and voltages of light-emitting diodes
(LEDs) and Zener diodes.

EQUIPMENT REQUIRED
Instruments

DMM
Components

Resistors
(1) 100-Ω
(1) 220- Ω
(1) 330- Ω
(1) 2.2-k Ω
(1) 3.3-k Ω
(2) 1-k Ω

Diode

(1) Silicon
(1) LED
(1) Zener (10-V)

Supplies

DC power supply

80
Exp. 6 / Procedure 81

EQUIPMENT ISSUED
Item Laboratory serial no.
DMM
DC power supply

RESUME OF THEORY
The light-emitting diode (LED) is, as the name implies, a diode that will give off
visible light when sufficiently energized. In any forward-biased junction p-n there
is, close to the junction, a recombination of holes electrons. This recombination
requires that the energy possessed by unbound free electrons be transferred to
another state. In LED materials, such as gallium arsenide phosphide (GaAsP) or
gallium phosphide (GaP), photo: light energy are emitted in sufficient numbers to
create a visible light source—a process referred to as electroluminescence. For
every LED there is a distinct forward voltage and current that will result in a
bright, clear light: whether it be red, yellow, or green. The diode may, therefore, be
forward biased, but until the distinct level of voltage and current is reached, the
1ight may not be visible. In this experiment the characteristics of an LED will be
plotted and the "firing" levels of voltage and current determined.
The Zener diode is a p-n junction device designed to take full advantage of
the Zener breakdown region. Once the reverse-bias potential reaches Zener region,
the ideal Zener diode is assumed to have a fixed term voltage and zero internal
resistance. All practical diodes have some internal resistance even though,
typically, it is limited to 5 to 20 Ω. The internal resistance is the source of the
variation in Zener voltage with current level The experimental procedure will
demonstrate the variation in term voltage for different loads and resulting current
levels.
The following procedure is used to determine the state of the Zener diode.
For most configurations, the state of the Zener diode can usually be determined
simply by replacing the Zener diode with an open circuit calculating the voltage
across the resulting open circuit. If the open-circuit voltage equals or exceeds the
Zener potential, the Zener diode is "on" and Zener diode can be replaced by a DC
supply equal to the Zener potential. Even though the open-circuit voltage may be
greater than the Zener potential, the diode is still replaced by a supply equal to
the Zener potential. Once the Zener voltage is substituted, the remaining voltages
and currents the network can be determined.

PROCEDURE
Part1 LED Characteristics
a. Construct the circuit of Fig. 7.1. Initially, set the supply voltage 0 V and record
the measured value of the resistor R.
Exp. 6 / Procedure 82

b. Increase the supply voltage E until "first light" is noticed. Record the value of
VD and VR using the DMM. Calculate the corresponding level of ID using ID
=VR/ R and the measured resistance value.

VD (measured) =
VR (measured) =
ID (calculated) =

c. Continue to increase the supply voltage E until "good brightness" is first

established. Don't overload (add too much current to) the circuit and possibly
damage the LED by continuing to raise the voltage beyond this level. Record
the values of VD and VR and calculate the corresponding level of ID using ID =
VR/R and the measured resistance value.
VD (measured) =
VR (measured) =
ID (calculated) =

d. Set the DC supply to the levels appearing in Table 7.1 and measure both VD
and VR. Record the values of VD and VR in Table 7.1 and calculate the
corresponding level of ID using ID = VR/R and the measured resistance value.

TABLE 7.1
E(V) 0 1 2 3 4 5 6
VD(V)
VR(V)
lD= VR/R(mA)

e. Using the data of Table 7.1, sketch the curve of ID vs. VD on the graph of Fig.
7.2.

f. Draw a light dashed horizontal line across the graph of Fig. 7.2 at the current
ID required for "good brightness." In addition, draw a light dashed vertical line
the full height of Fig. 7.2 at the point of intersection between the curve and
the light dashed horizontal line. The intersection of the vertical line with the
horizontal axis should result in a level of VD close to that measured in Part
1(c).
Shade in the region below the ID line and to the left of the VD line and
label the region as the region to be avoided if "good brightness" is to be
obtained. Label the remaining unshaded region of Fig. 7.2 as the region for
"good brightness."
Exp. 6 / Procedure 83

Figure 7-2

g. Construct the circuit of Fig. 7.3. Be sure that both diodes connected properly and
record the measured resistance value.

Figure 7-3

h. Do you expect the LED to burn brightly? Why?

i. Energize the network of Fig. 7.3 and verify your conclusion in part 1(h).

j. Reverse the silicon diode of Fig. 7.3 and repeat Part 1(h).
k. Repeat Part l(i). If the LED is "on" with "good brightness," measure VD and
VR and calculate the level of ID. Find the intersection of ID and VD on the
graph of Fig. 7.2. Is the intersection on the curve part of the "good
brightness" region?
Exp. 6 / Procedure 84

Part 2. Zener Diode Characteristics

a. Construct the circuit of Fig. 7.4. Initially, set the DC supply to 0 V and
record the measured value of R.

Figure 7-4

b. Set the DC supply (E) to the values appearing in Table 7.2 and measure
both Vz and VR. You may have to use the millivolt range of your DMM for
low values of Vz and VR.

TABLE 7.2
E(V) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vz(V)

VR(V)
Iz= VR/Rmeas (mA)

c. Calculate the Zener current Iz in mA at each level of E using Ohm's law as

indicated in the last row of Table 7.2 and complete the table.

d. This step will develop the characteristic curve for the Zener diode. Since the
Zener region is in the third quadrant of a complete diode characteristic
curve, place a minus sign in front of each level of Iz and Vz for each data
point. With this convention in mind plot the data of Table 7.2 on the graph
of Fig. 7.5. Choose an appropriate scale for lz and Vz as determined by the
range of values for each parameter.
Exp. 6 / Procedure 85

Figure 7-5

e. For the range of measurable current IZ in the linear (straight line) region that
drops from the VZaxis, what is the average value of VZ?

VZ(approximated) =
f. For the range of measurable current IZ in the linear region that drops from
the VZ axis, estimate the average resistance of Zener diode using rav = ΔVZ/ΔIZ,
where ΔVZ is the change in Zener voltage for the corresponding change in
Zener current. Choose an interval of at least 20 V on the linear region of the
curve. If necessary, use the data of Table 7.2. Show all work.

RZ (calculated) =

g. Using the results of Parts 2(e) and 2(f), establish the Zener diode equivalent
circuit of Fig. 7.6 for the "on" linear region. Then insert the values of RZ and
VP.

h. For the region from VZ and IZ = 0 to the point where the characteristic curve
drops sharply from the VZ axis, calculate the resistance of the Zener diode
Exp. 6 / Procedure 86

using the equation r = ΔVZ/ΔIZ. Choose ΔVZ = VZ- 0 V = VZ and substitute

the resulting change in current (ΔIZ) for this interval.

RZ (calculated) =

Is the calculated level the level you expected for the region in which the
Zener diode is "off"? What would be an appropriate approximation for the
Zener diode in this region?

Part 3. Zener Diode Regulation

a. Construct the network of Fig. 7.7. Record the measured value of each
resistor.

b. Determine whether the Zener diode of Fig. 7.7 is in the "on" state, that is,
operating in the Zener breakdown region. Use the measured resistor values
and the VZ determined in Part 2(e). Ignore the effects of RZ in your
calculations. For the diode in the "on" state calculate the expected values of
VL, VR, IR, IL, and IZ. Show all calculations.

VL (calculated) = VR (calculated) =

IR (calculated) = IL (calculated) =

IZ(calculated) =

c. Energize the network of Fig. 7.7 and measure VL and VR. Using these values,
calculate the levels of IR, IL, and Iz

VL (measured) = VR measured) =

IR (calculated) = IL (calculated) =

Iz (calculated) =
Exp. 6 / Procedure 87

How do the results of Parts 3(b) and 3(c) compare?

d. Change RL to 3.3 kΩ and repeat Part 3(b). That is, calculate the expected levels
of VL, VR, IR, and Iz using measured resistor values and the VZ determined in
Part 2(e).

VL (calculated) = VR (calculated) =

IR (calculated) = IL (calculated) =

Iz (calculated) =

e. Energize the network of Fig. 7.7 with RL = 3.3 kΩ and R1 = 1 kΩ Measure VL

and VR. Using these values, calculate the levels of IR, IL, and IZ.

Rl (measured) = R3 (measured) =

VL (measured) = VR (measured) =

IR (calculated) = IL (calculated) =

IZ (calculated) =

How do the results of Parts 3(b) and 3(c) compare?

f. Using the measured resistor values and VZ determined from Part 2(e),
determine the minimum value of RL required to ensure that the Zener diode is
in the "on" state.

RLmin (calculated) =

g. Based on the results of Part 3(f), will a load resistor of 2.2 kΩ place the Zener
diode of Fig.7.7 in the "on" state?

Insert RL=2.2 kΩ into Fig. 7.7 and measure VL.

VL (measured) =

Are the conclusions of Parts 3(f) and 3(g) verified?

Exp. 6 / Procedure 88

Part 4. LED-Zener Diode Combination

a. In this part of the experiment we will determine the minimum supply voltage
necessary to turn on ("good brightness") the LED and the Zener diode of Fig.
7.8. The LED will reveal when the Zener diode is "on" and the required supply
voltage will be the minimum value that can be applied if the Zener diode is to
be used to regulate the voltage VL.

Figure 7-8

b. Refer to Part 1(c) and record the level of VD and ID that resulted in a “good
brightness" level for the LED.
VL (measured) =
ID(measured) =

Refer to Part 2(e) and record the level of VZ for your Zener diode.
Vz =

Using the above data, determine the total voltage necessary to turn both the
LED diode and the Zener diode "on" in Fig. 7.8. That is, determine the
required voltage from point a to b.

Vab (calculated) =
c. Using the result of Part 4(b), calculate the voltage VL and resulting current IL.
Use measured resistor values.

VL (calculated) =

IL (calculated) =

d. Calculate IR from IR = IL + IZ = IL + ID using the level of ID from Part 4(b). Then

calculate the voltage VR using Ohm's law.

IR (calculated) =

VR (calculated) =
Exp. 6 / Procedure 89

e. Using Kirchhoff’s voltage law, calculate the required supply voltage E to turn
on the Zener diode and establish "good brightness" by the LED. Use measured
resistor values.

E (calculated) =

f. Turn on the supply of Fig. 7.8 and increase the voltage E until the LED has
"good brightness." Record the required level of E below:
E (measured) =

How does the level calculated in Part 4(e) compare with the measured value?

g. Measure the voltage VD and compare with the level listed in Part 4(b).

VD (measured) =

Measure the voltage VZ and compare with the level listed in Part 4(b).

VZ (measured) =
Exp. 6 / Procedure 90

Name:
Date:
Instructor:

Experiment Bipolar Junction

8
Transistor (BJT)
Characteristics

OBJECTIVES
1. To determine transistor type (npn, pnp), terminals, and material
using a digital multimeter (DMM).
2. To graph the collector characteristics of a transistor using
experimental methods and a curve tracer.
3. To determine the value of the alpha and beta ratios of a transistor.

EQUIPMENT REQUIRED
Instruments

DMM

Components

Resistors
(1) 1-kΩ
(1) 330-kΩ
(1) 5-kΩ potentiometer
(1) 1-MΩ potentiometer

Transistors

(1) 2N3904 (or equivalent)

(1) Transistor without terminal identification

Supplies

DC power supply

93
Exp. 8 / Procedure 94

EQUIPMENT ISSUED

Item Laboratory serial no.

DMM
Curve tracer
DC power supply

RESUME OF THEORY

Bipolar transistors are made of either silicon (Si) or germanium (Ge). Their
structure consists of two layers of n-type material separated by a layer of p- type
material (npn), or of two layers of p-material separated by a layer of n- material
(pnp). In either case, the center layer forms the base of the transistor, while the
external layers form the collector and the emitter of the transistor. It is this
structure that determines the polarities of any voltages applied and the direction
of the electron or conventional current flow. With regard to the latter, the arrow at
the emitter terminal of the transistor symbol for either type of transistor points in
the direction of conventional current flow and thus provides a useful reference
(Fig. 8.2). One part of this experiment will demonstrate how you can determine
the type of transistor and its material, and identify its three terminals.
The relationships between the voltages and the currents associated with a
bipolar junction transistor under various operating conditions determine its
performance. These relationships are collectively known as the characteristics of
the transistor. As such, they are published by the manufacturer of a given
transistor in a specification sheet. It is one of the objectives of this laboratory
experiment to experimentally measure these characteristics and to compare them
to their published values.

PROCEDURE

Part 1. Determination of the Transistor's Type, Terminals, and Material

The following procedure will determine the type, terminals, and material of a
transistor. The procedure will utilize the diode testing scale found on many
modern multimeters. If no such scale is available, the resistance scales of the
meter may be used.
a. Label the transistor terminals of Fig. 8.1 as 1, 2, and 3. Use the transistor
without terminal identification for this part of the experiment.
Exp. 8 / Procedure 95

b. Set the selector switch of the multimeter to the diode scale (or to the 2 kΩ
range if the diode scale is unavailable).
c. Connect the positive lead of the meter to terminal 1 and the negative lead to
terminal 2. Record your reading in Table 8.1.

TABLE 8.1
Meter leads connected to BJT Diode check reading (or highest
resistance range)
Step Positive Negative
c 1 2
d 2 1
e 1 3
f 3 1
9 2 3
h 3 2

d. Reverse the leads and record your reading.

e. Connect the positive lead to terminal 1 and the negative lead to terminal 3.
Record your reading.
f. Reverse the leads and record your reading.
g. Connect the positive lead to terminal 2 and the negative lead to terminal 3.
Record your reading.
h. Reverse the leads and record your reading.
i. . The meter readings between two of the terminals will read high (O.L. or
higher resistance) regardless of the polarity of the meter leads connected.
Neither of these two terminals will be the base. Based on the above, record the
number of the base terminal in Table 8.2.

j. Connect the negative lead to the base terminal and the positive lead to either
of the other terminals. If the meter reading is low (approximately 0.7 V for Si
and 0.3 V for Ge or lower resistance), the transistor type is pnp; go to step k(l).
If the reading is high, the transistor type is npn; go to step k(2)
k. (1) For pnp type, connect the negative lead to the base terminal and the
positive lead alternately to either of the other two terminals. The lower of the
two readings obtained indicates that the base and collector are connected;
thus the other terminal is the emitter. Record the terminals in Table 8.2.(2) (2)
For npn type, connect the positive lead to the base terminal and the negative
lead alternately to either of the other two terminals. The lower of the two
readings obtained indicates that the base and collector are connected; thus the
other terminal is the emitter. Record the terminals in Table 8.2.
Exp. 8 / Procedure 96

1. If the readings in either (1) or (2) of Part l(k) were approximately 700
mV, the transistor material is silicon. If the readings were
approximately 300 mV, the material is germanium. If the meter does
not have a diode testing scale, the material cannot be determined
directly. Record the type of material in Table 8.2.

Part 2. The Collector Characteristics

a. Construct the network of Fig. 8.2.
b. Set the voltage VR to 3.3 V by varying the 1-MΩ potentiometer.
This adjustment will set IB = VRB /RB to 10 μA as indicated in Table 8.3.
c. Then set VCE to 2 V by varying the 5-kΩ potentiometer as required by the first
line of Table 8.3.
d. Record the voltages VRC and VBE in Table 8.3.
e. Vary the 5-kΩ potentiometer to increase VCE from 2 V to the values appearing
in Table 8.3. Note that IB is maintained at 10 μA for the range of VCE levels.
20 V

Figure 8-2 Circuit to determine the characteristics of a BJT.

f. For each value of VCE measure and record VRC and VBE. Use the mV scale for
VBE.
g. Repeat Parts 2(b) through 2(f) for all values of VRB indicated in Table 8.3. Each
value of VRB will establish a different level of IB for the sequence of VCE values
as shown.
h. After all data have been obtained, compute the values of IC from
IC = VRC/RC and IE from IE = IC + IB. Use the measured resistor value for RC.
i. Using the data of Table 8.3, plot the collector characteristics of the transistor
on the graph of Fig. 8.3. That is, plot IC versus VCE for the various values of IB.
Choose an appropriate scale for IC and label each IB curve.
Exp. 8 / Procedure 97

FIGURE 8-3 Characteristic curves from the experimental data of Part 2.

Part 3. Variation of α and β

a. For each line of Table 8.3 calculate the corresponding levels of α and β
using α= IC/IE and β = IC/IB and complete the table.
b. Is there a significant variation in α and β from one region of the
characteristics to another?
Exp. 8 / Procedure 98

In which region are the largest values of β found? Specify using the relative levels of VCE
and IC.

In which region are the smallest values of β found? Specify using the relative levels of
VCE .and IC.
Exp. 8 / Procedure 99

c. Find the largest and smallest levels of β and mark their locations on the plot
of Fig. 8.3 using the notations βmax and βmin.

d. In general, did β increase or decrease with increase in IC?

e. In general, did β increase or decrease with increase in VCE? Was the effect of
VCE on β greater or less than the effect of IC?

Part 4. Determination of the Characteristics of a Transistor

a. Reproduce the characteristics obtained on the graph of Fig. 8.4. Be sure to

label each IB curve and include the scale for each axis.
b. Compare the characteristics to those obtained in Part 2. Be specific in
describing the differences between the two sets of characteristics.

FIGURE 8-4 Characteristic curves obtained from a commercial curve tracer.

Exp. 8 / Procedure 100

Part 5. Exercises

1. Find the average value of β using the data of Table 8.3. That is, find the sum of
the β values and divide by the number of values.

β(av) (calculated) =
Where on the characteristics did the average value of β typically occur?

Is it reasonable to use this value of β for the transistor for most applications?

2. Determine the average value of VBE using the data of Table 8.3. As in Exercise 1
find the sum of the VBE values and divide by the number of values.

VBE (av) (calculated) =

Is it reasonable to use the 0.7 V level in the analysis of BJT transistor
networks where the actual value is unknown?
 Name:
Date:
Instructor:

Experiment Fixed-

9
And Voltage-
Divider Bias
of BJTs

OBJECTIVE
To determine the quiescent operating conditions of the fixed- and voltage-
divider-bias BJT configurations.

EQUIPMENT REQUIRED

Instrument

DMM

Components

Resistors

(1) 680-Ω
(1) 2.7-kΩ
(1) 1.8-kΩ
(1) 6.8-kΩ
(1) 33-kΩ
(1) 1-MΩ

Transistors

(1) 2N3904 or equivalent

(1) 2N4401 or equivalent

Supplies

DC power supply

103
104 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

EQUIPMENT ISSUED

RESUME OF THEORY

Bipolar transistors operate in three modes: cutoff, saturation, and linear. In each of these
modes, the physical characteristics of the transistor and the external circuit connected to
it uniquely specify the operating point of the transistor. In the cutoff mode, there is only a
small amount of reverse current from emitter to collector, making the transistor akin to
an open; switch. In the saturation mode, there is a maximum current flow from collector
to emitter. The amount of that current is limited primarily by the external network
connected to the transistor; its operation is analogous to that of a closed switch. Both of
these operating modes are used in digital circuits.
For amplification with a minimum of distortion the linear region of the transistor
characteristics is employed. A DC voltage is applied to the transistor, forward-biasing the
base-emitter junction and reverse-biasing the base-collector junction, typically
establishing a quiescent point near or at the center of the linear region.
In this experiment, we will investigate two biasing networks: the fixed bias and the
voltage-divider bias configuration. The former has the serious drawback that the location
of the Q-point is very sensitive to the forward current transfer ratio ((3) of the transistor
and temperature. Because there can be wide variations in beta and the temperature of
the device, it can be difficult to predict the exact location of the Q-point on the load line of
a fixed- bias configuration.
The voltage-divider bias network employs a feedback arrangement that makes the
base-emitter and collector-emitter voltages primarily dependent on the external circuit
elements and not the beta of the transistor. Thus, even though the beta of individual
transistors may vary considerably, the location of the Q-point on the load line will remain
essentially fixed. The phrase "beta-independent biasing" is often used for such an
arrangement.

PROCEDURE

Part1. Determining β

a. Construct the network

of Fig. 9.1 using the
2N3904 transistor.
Record the measured
resistance values.
105 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

b. Measure the voltages VBE and VRC.

VBE (measured) =
VRC (measured) =

c. Using the measured resistor values, calculate the resulting base current using the
equation

and the collector current using the equation

The voltage VRB was not measured directly for determining IB

because of the loading effects of the meter across the high resistance RB.

Insert the resulting values of IB and IC in Table 9.1.

d. Using the results of Part 1(c), calculate the value of β and record in Table 9.1. This

value of beta will be used for the 2N3904 transistor throughout this experiment.

Part 2. Fixed-Bias Configuration

a. Using the β determined in Part 1, calculate the currents IB and IC for the networkofFig.
9.1 using the measured resistor values, the supply voltage, and the above measured
value for VBE. That is, determine the theoretical values of IB and IC using the network
parameters and the value of beta.

IB (calculated) =

IC(calculated) =
106 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

How do the calculated levels of IB and IC compare to those determined from measured
voltage levels in Part 1(c)?

b. Using the results of Part 2(a), calculate the levels of VB, VC, VE, and VCE.

VB (calculated) =

VC (calculated) =

VE (calculated) =

VCE (calculated) =

c. Energize the network of Fig. 9.1 and measure VB, VC, VE, and VCE

VB (measured) =

VC (measured) =

VE (measured) =

VCE (measured) =

How do the measured values compare to the calculated levels of Part 2(b)?

Record the measured value of VCE in Table 9.1.

d. The next part of the experiment will essentially be a repeat of a number of the steps
above for a transistor with a higher beta. Our goal is to show the effects of different
beta levels on the resulting levels of the important quantities of the network. First the
beta level for the other transistor, specifically a 2N4401 transistor, must be
determined. Remove the 2N3904 transistor from Fig. 9.1 and insert the 2N4401
transistor, leaving all the resistors and voltage VCC as in Part 1. Then measure the
voltages VBE and VRC using the same equations with measured resistor values.
Calculate the levels of IB and IC. Then determine the level of β for the 2N4401
transistor.
107 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

VBE (measured) =

VRC (measured) =

IB (from measured) =

Ic (from measured) =

β (Calculated) =

Record the levels of IB ,IC, and beta in Table 9.1. In addition, measure the voltage
VCE and insert in Table 9.1.

TABLE 9.1
VCE β
Transistor IC (mA) IB (μA)
(volts)
Type
2N3904
2N4401

e. Using the following equations, calculate the magnitude (ignore the sign) of the
percent change in each quantity due to a change in transistors. The fixed-bias
configuration has a high sensitivity to changes in beta, as will be reflected by the
results. Place the results of your calculations in Table 9.2.

TABLE 9.2
Percent Changes in β, IC,VCE,and
lB
%Δβ %ΔIC %ΔVCE %ΔIB
108 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

Part 3. Voltage-Divider Configuration

a. Construct the network of Fig. 9.2 using the 2N3904 transistor. Insert the measured
value of each resistor.

Figure 9-2

b. Using the beta determined in Part 1 for the 2N3904 transistor, calculate the theoretical
levels of VB, VE, IE, IC, VC, VCE, and IB for the network of Fig. 9.2. Record the results in
Table 9.3.

c. Energize the network of Fig. 9.2 and measure VB, VE, VC, and VCE. Record their values in
Table 9.3. In addition, measure the voltages VR1 and VR2 . Try to measure the quantities
to the hundredths or thousandths place. Calculate the currents IE and IC and the
currents and I1 and I2 (using I1 = VR1 /R1 and /2 = VR2 /R2) from the voltage readings and
measured resistor values. Using the results for I1 and /2, calculate the current IB using
Kirchhoffs current law. Record the calculated current levels for IE, IC, and IB in Table
9.3. How do the calculated and measured values of Table 9.3 compare? Are there any
significant differences that need to be explained?

TABLE 9.3

2N3904
VB VE VC VCE lE (mA) lc( mA) IB(µA)
Calculated [Part 3(b)]
Measured [Part 3(c)]

d. Record the measured value of VCE and calculated values of IC and IB from Part 3(c) in
Table 9.4 along with the magnitude of beta from Part 1.

e. Replace the 2N3904 transistor of Fig. 9.2 with the 2N4401 transistor. Then measure
the voltages VCE, VRC , VR1 , and VR2 . Again, be sure to read VR1 and VR2 to the
109 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

hundredths or thousandths place to ensure an accurate determination of IB. Then

calculate IC, I1 and I2, and determine IB. Complete Table 9.4 with the levels of VCE, IC,
IB, and beta for this transistor.

f.

TABLE 9.4

Transistor Type VCE (volts) lc(mA) IB(µA) β

2N3904
2N4401

f. Calculate the percent change in β, IC, VCE, and from the data of Table 9.4. Use the
formulas appearing in Part 2(e), Eq. 9.1, and record your results in Table 9.5.

TABLE 9.5
g.

Percent Changes in p, lc, VCE, and lB

%Δβ %ΔIC %ΔCE %ΔIB

Part 5. Problems and Exercises

1. a. Compute the saturation current ICsat for the fixed-bias configuration of Fig.
9.1.

ICsat (calculated) =

b. Compute the saturation current ICsat for the voltage-divider bias configuration
of Fig. 9.2.
110 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

ICsat (calculated) =

c. Are the saturation currents of Exercises 1(a) and 1(b) sensitive to the beta of
the transistor or changes thereof?

2. a. Determine the ratio of the change in IC, VCE, and due changes in beta and
complete Table 9.6. Use the results Parts 2 and 3 to obtain the percent
changes indicated.

TABLE 9.6
%ΔIC % Δ VCE %
ΔIB
%Δβ %Δβ % Δβ
Fixed Bias
Voltage-Divider

b. One of the important goals of a good circuit design is to minimize the

sensitivity of various circuit currents and voltages to the beta variability of
transistors. A figure of merit that quantizes the percent change in collector
current for a percent change in beta has been defined by the following
equation. In particular, the smaller S(β), the less the circuit will be affected by
the change in beta.

Referring to the results of Table 9.6, which network has the better stability
factor S(β)? Is there a significant difference in level between the two stability
factors?

S(β)= %ΔIC (9.2)

%Δβ
111 Exp. 9 / Fixed- and Voltage-Divider Bias of BJT

c. Do the remaining sensitivities of Table 9.6 support the fact that one
configuration is more stable than the other? Which one is more stable?

3. a. For the fixed-bias configuration of Fig. 9.1 develop an equation for IB in terms
of the other elements (voltage source, resistors, β) of the network. Then
develop an equation for IC.

b. Assuming I1 and I2 are much larger than IB, permitting the approximation
I1= I2, develop an equation for IC in terms of the other elements of the network
of Fig. 9.2.

c. Referring to the results of Exercises 3(a) and 3(b), is there an obvious reason
why IC is more sensitive to changes in beta in one configuration compared to
the other
Open Ended lab
 Name:
Date:
Instructor:

Experiment Emitter

10
and Collector
Feedback Bias
of BJTs

OBJECTIVE

To determine the quiescent operating conditions of the emitter and collector feedback
bias BJT configurations.

EQUIPMENT REQUIRED

Instrument

DMM

Components

Resistors

(2) 2.2-kΩ
(1) 3-kΩ
(1) 390-kΩ
(1) 1-MΩ
Transistors

(1) 2N3904 or equivalent

(1) 2N4401 or equivalent

Supplies

DC power supply

116
Exp. 10 117

EQUIPMENT ISSUED

RESUME OF THEORY
This experiment is an extension of Experiment 9. Two additional arrangements will
be investigated in this experiment: emitter-bias and collector feedback circuits.
Emitter-Bias Circuit
The emitter-bias configuration in Fig. 10.1 can be constructed using a single: or a
dual power supply. Both configurations offer increased stability over fixed bias of
Experiment 9. In particular, if the beta of the transistor times the resistance of the
emitter resistor is large compared to the resistance of the base resistor, the emitter
current becomes essentially independent of beta of the transistor. Thus, if we
exchange transistors in a properly designed emitter-bias circuit, the changes in IC
and VCE should be small.
Collector Feedback Circuit
If we compare the collector feedback bias circuit configuration in Fig.10.2 with the
fixed bias of Experiment 9 it is noted that for the former, the base resistor is
connected to the collector terminal of the transistor and not to fixed supply voltage
VCC. Thus the voltage across the base resistance of collector feedback configuration
is a function of the collector voltage and collector current. In particular, this circuit
demonstrates the principle negative feedback, in which a tendency of an output
variable to increase decrease will result in a reduction or increase in the input
variable respectively. For instance, any tendency on the part of IC to increase will
reduce the level of VC, which in turn will result in a lower level of IB offsetting the
increasing trend of IC. The result is a design less sensitive variations in its
parameters.

PROCEDURE
Part 1. Emitter-Bias Configuration: Determining β
a. Construct the network of Fig. 9.1 using the 2N3904 transistor
Insert the measured resistor values.

Figure 9-1
Exp. 10 118

b. Measure the voltages VB and VRC .

VB (measured) =

VRC (measured) =

c. Using the results of Part 1(b) and the measured resistor values, calculate the
resulting base currents IB and IC using the following equations:

Record in Table 9.2 on page 122.

IB (calculated from measured) =

Ic (calculated from measured) =

d. Using the results of Part 1(c), calculate the value of P and record in Table
9.2. This value of beta will be used for the 2N3904 transistor throughout
the experiment.

β (calculated) =

Part 2. Emitter-Bias Configuration: Determining Operating Point

a. Using the β determined in Part 1, calculate the values of IB and IC for the
network of Fig. 9.1 using measured resistor values and the supply voltage
VCC. Perform a theoretical analysis of the network. Insert the results in
Table 9.1 on page 122.

IB (calculated) =

IC (calculated) =

How do the calculated values compare with the measured values of Part 1(c)?

b. Using the β determined in Part 1 calculate the levels of VB, VC, VE, VBE, and VCE and
insert in Table 9.1.
Exp. 10 119

c. Energize the network of Fig. 9.1 with the 2N3904 and measure the voltages VB, VC,
VE, VBE, and VCE. Record in Table 9.2.
How do the calculated and measured results of Tables 9.1 and 9.2 compare for
the 2N3904 transistor? In particular, comment on any results that do not compare
well.

TABLE 9.1
Calculated Values
Transistor
VB Vc VE VBE VCE lB IC
Type (volts) (volts) (volts) (volts) (volts) (µA) (mA)
2N3904
2N4401

TABLE 9.2

Transistor Measured Values Calc. from Measured Values)

VB Vc VE VBE VCE lB lc
Type (volts) (volts) (volts) (volts) (volts) (µA) (mA) β
2 N3904
2N4401

d. Replace the 2N3904 transistor of Fig. 9.1 with the 2N4401 transistor and
measure the resulting voltages VB and VRC . Then calculate the currents
IB and IC using measured resistance values. Finally calculate the value
of β for this transistor. This will be the value of beta used for the
2N4401 transistor throughout this experiment. Record the levels of IB, IC,
and β in Table 9.2.

VB (measured) =

VRC (measured) =

e. Using the beta determined in Part 1(d), perform a theoretical

analysis of Fig. 9.1 with the 2N4401 transistor. Calculate the
levels of IB, IC, VB, VC, VE, VBE, and VCE and record in Table 9.1.
Exp. 10 120

f. Energize the network of Fig. 9.1 with the 2N4401 transistor; measure V
,VC,
B

VE, VBE, and VCE; and insert in Table 9.2.

How do the calculated and measured results of Tables 9.1 and 9.2
compare for the 2N4401 transistor? Discuss any results that appear
different by more than 10%.

g. Calculate the percent change in β, IC, VCE, and IB using the equations firstpresented
in Experiment 8 and repeated here for convenience. Record the results in
Table 9.3.

TABLE 9.3
Percent Changes in β, IC, VCE, and lB
%Δβ %Δ lC %ΔVCE %ΔIB

Part 3. Collector Feedback Configuration (RE = 0 Ω )

a. Construct the network of Fig. 9.2 using the 2N3904 transistor. Record the
measured resistor values in Fig. 9.2.

Figure 9-2 Collector Feedback

\
Exp. 10 121

b. Using the beta determined in Part 1, calculate the values of IB, IC, VB, VC,
and VCE and record in Table 9.4.

c. Energize the network of Fig. 9.2; measure VB, VC, and VCE; and insert in
Table 9.5. Calculate the currents IB and IC using measured resistance
values and the fact that IC = VR /RC. Record the current levels in Table 9.5.

How do the calculated and measured results of Tables 9.4 and 9.5 compare
for the 2N3904 transistor?

d. Replace the 2N3904 transistor of Fig. 9.2 with the 2N4401 transistor of
Part 1; calculate the values of IB, IC, VB, VC and VCE; and record in Table9.4.

e. Energize the network of Fig. 9.2 with the 2N4401 transistor and meare VB, VC,
su
and VCE. Insert all measurements in Table 9.5. Calculate IB and IC from
measured values and then record the current levels in Table 9.5.

How do the calculated and measured results of Tables 9.4 and 9.5 compare
for the 2N4401 transistor?

f. Calculate the percent changes in β, IC, VCE, and IB using the equations of Part
1(g). Record the results in Table 9.6.

TABLE 9.4
Theoretical Calculated Values
Transistor
VB Vc VCE lB Ic
Type (volts) (volts) (volts) (μA) (mA)
2 N3904
2N4401
Exp. 10 122

TABLE 9.5
Measured Values (Calc. from Measured Values)

Transistor
VB Vc VCE lB Ic
Type (volts) (volts) (volts) (uA) (mA)
2N3904

2N4401

TABLE 9.6
Percent Changes in β, IC, VCE, and ΔIB
%Δβ %ΔIC %ΔVCE %ΔIB

Part 4. Collector Feedback Configuration (with RE)

a. Construct the network of Fig. 9.3 using the 2N3904 transistor. Record the
measured resistance values in Fig. 9.3.

vcc = 20V

Figure 9-3 Collector feedback circuit.

b. Using the beta determined in Part 1, calculate the values of IB, IC, IE, VB, VC,
and VCE and record in Table 9.7 on page 129.

c. Energize the network of Fig. 9.3; measure VB, VC, VE, and VCE and insert inTable
9.8. In addition, calculate the currents IB, IC and IE from measured
values using measured resistor values Record the current levels in
Table 9.8.
Exp. 10 123

How do the calculated and measured results of Tables 9.7 and 9.8 compare for
the 2N3904 transistor?

d. Replace the 2N3904 transistor of Fig. 9.3 with the 2N4401 transistor.
Using the beta of Part 1, calculate the values of IB, IC, IE, VB, VC, and VCE
and record in Table 9.7.

e. Energize the network of Fig. 9.3 with the 2N4401 transistor measure V,B VC,
VE, and VCE; and insert in Table 9.8. In addition, calculate the currents IB,
IC, and IE from measure values using the measured resistor values.
Record the current levels in Table 9.8.

How do the calculated and measured results of Tables 9.7 and 9.8 compare for
the 2N4401 transistor?

f. Calculate the percent changes in (β, IC, VCE, and IB using the equations
appearing in Part 1(g) and record in Table 9.9.

TABLE 9.7
Theoretical Calculated Values
TRANSISTOR
VB VC VE VCE IB IC IE
TYPE (VOLTS) (VOLTS) (VOLTS) (VOLTS) (µA) (mA) (mA)
2N3904
2N4401
Exp. 10 124

TABLE 9.8

Measured Values Calc. from Measured Values)

TRANSISTOR
VB VC VE VCE IB IC IE
TYPE (VOLTS) (VOLTS) (VOLTS (VOLTS) (µA) (mA) (mA)
)
2N3904
2N4401

TABLE 9.9
Percent Changes in β, IC, VCE, and lB

%Δβ %Δ/C %ΔVCE %ΔIE

 Name
Date
Instructor

11
EXPERIMENT

Design of BJT
Bias Circuits

OBJECTIVE
To design a collector-feedback, emitter-bias, and voltage-divider-bias B
T
J
transistor network.

EQUIPMENT REQUIRED

Instruments

(1) DMM

Components

Resistors

Since this is a design experiment, a number of the required resistors

are not specified in the equipment list. They will have to be requested
from the stockroom once their values are determined.

(1) 300-Ω, 1.2-kΩ, 1.5-kΩ, 3-kΩ, 15-kΩ, 100-kΩ

(1) 1-MΩ potentiometer
Other resistors as required by the designs

Transistors

(1) 2N3904 or equivalent

(1) 2N4401 or equivalent

Supplies
(1) DC power supply

136
Exp. 10 137

EQUIPMENT ISSUED
Item Laboratory serial no.
DMM
DC power supply

RESUME OF THEORY
In this experiment we will make a preliminary design of a collector-feedback, emitter-bias,
and voltage-divider-bias BJT transistor configuration. Unlike analysis, where the circuit is
given and the response of the circuit variables is asked for, in circuit design, the desired
circuit responses are specified and a circuit that yields the desired variables is to be
constructed.
Circuit design is often a series of compromises. The most stable network may not result in
an acceptable level of AC gain. The resistor values that the theoretical calculations suggest
may not be commercially available. One set of resistor values may result in the most stable
system with excellent gain characteristics but result in a low conversion efficiency as
defined by η% = P0(ac)/Pi(dc) x 100%. The designer must be aware of the consequences of
making a certain choice and which characteristics of the design are the most vital for the
particular application.

For a specified Q-point, β, and an appropriate level for VE, the following equations
can be applied as a DC design sequence

Collector-Feedback:
Rc=VCC -VCEQ (11.1)
ICQ

RB=VRB=VCEQ-VBE=β[VCEQ-VBE] (11.2)
IB ICQ/β ICQ/β

Emitter-Bias:

RE= VE (11.3)
ICQ

VC= VCEQ + VE (11.4)

RC= VRC = Vcc – Vc (11.5)

ICQ ICQ

RB= VRB= VCC-VBE-VE = B[VCC- VBE – VE] (11.6)

IB ICQ ICQ
Exp. 10 138

Voltage-Divider Bias

(11.7)

(11.8)

Assuming βR2> 10R2 will result in

11.9)

Design Criteria

For each of the above configurations the following defines the relative stability of
the system.

PROCEDURE
Part 1. Collector – Feedback Configuration

Circuit specifications:

VCC = 15V
ICQ = 5 mA
VCEQ = 7.5 V
Exp. 10 139

Design Procedure:

a. From the given specifications, determine the required value of RC

for the collector-feedback network of Fig.11.1.

Figure 11-1

Determine the closest commercial value (available in the laboratory) and record below and
in Fig. 11.1. Obtain the chosen resistor and insert the measured resistance value in the
space provided in Fig. 11.1.

Rc (calculated) =

Rc (commercial value) =

b. Connect a 100-kΩ resistor and the 1-MΩ potentiometer, set to a maximum, in series, as
in Fig. 11.1. Use the commercial value of Part 1 for RC. With the power on, adjust the
potentiometer until VCE = 7.5 V using the 2N3904 transistor.

c. Turn off the supply and disconnect the 100-kQ resistor from the transistor base
connection and measure the combined resistance of RF1 and RF2 .Select a commercial
resistor close to this combined level (that is available in the laboratory) and record its
nominal value as RB. In addition, include its measured value on Fig. 11.1.

RB (measured) = RF1+ RF2=

RB (commercial value) =

d. Replace RF1 and RF2 in the assembled network with the commercial RB value selected in
Part 1(c). Then make the measurements and calculations listed below. Use measured
values for the resistance levels. Determine ICQ from ICQ = VRC/RC and IB from

IB = (VCE-VBE)/RB

VRC (measured) =
VCEQ (measured =

ICQ (calculated from measured) =

Exp. 10 140

β (calculated) =

e. Referring to the results of Part 1(d), how do the resulting values of ICQ and VCEQ
compare to their specified values?

Calculate the percent deviations between all specified and measured values. Use
specified values as the standard of comparison.

RB
f. The Resume of Theory introduced the ratio βRc as an indication of the relative
stability of the system. Determine the ratio and insert below. It will be examined in a
later part of the experiment.

RB/βRc (calculated) =
g. Rebuild Fig. 11.1 with the 2N4401 transistor and the same value of Rc and repeat
Parts 1(b) and 1(c).

RF1 (measured) + RF2 =

RB (commercial value) =

h. Referring to Part 1(g), did the value of RB change with the use of a transistor with a
higher β?

Why did the value of RC remain the same for both transistors?

i. Repeat Part 1(d) using the 2N4401 transistor.

VRC (measured) =
VCEQ (measured) =
(Calculated from measured) =
β (calculated) =

j. Referring to the results of Part l(i), how do the resulting values ICQ and VCEQ compare
to their specified values?
Exp. 10 141

Calculate the percent deviations as in Part 1(e). Which are large those presently
computed or those in Part 1(e)

k. Determine the ratio RB/ (β RC) for this configuration and compare to the level
calculated for the 2N3904 transistor.
RB/ βRC (calculated) (2N4401) =
RB/ βRC (calculated) (2N3904) =

Compare the results just obtained. What do the results suggest about the two
networks when we discuss their relative stability?

I. Rebuild the network of Fig. 11.1 with the level of RC and RB calculated for the 2N3904
transistor. However, this time insert the 2N4401 transistor so we can measure the
change in IC due to a change in beta. Energize the network and measure the voltage
VRC. Using the measured resistance value for RC, calculate ICQ
and then determine S( β ) = %ΔIC for the first design.
%Δ β

S(β) (calculated) =

Part 2. Emitter-Bias Configuration

Circuit Specifications:
VCC=15V
lCQ =5 mA
VCEQ = 7.5V
Design Procedure:

In this case we will employ the design rule that VE = 0.1 VCC. The Q-point location on the
load line is the same as defined for the collector- feedback configuration.

a. For the given specifications, calculate the required value of RC for the emitter-biased
configuration of Fig. 11.2. Determine the closest commercial value (available in the
laboratory) and record below and in Fig. 11.2. Obtain the resistor and insert its
measured value in the space provided in Fig. 11.2.

RC (calculated) =
Rc (commercial value) =
Exp. 10 142

Figure 11-2

b. Using VE = 0.1 VCC = 1.5 V, calculate the required value of RE for the network of Fig.
11.2. Determine the closest commercial value (available in the laboratory) and record
below and in Fig. 11.2. Obtain the chosen resistor and insert the measured value in
the space provided in Fig. 11.2.
RE (calculated) =
RE (commercial value) =
c. Connect a 100-kΩ resistor and the 1-MΩ potentiometer (set to a maximum) in series,
as in Fig. 11.2. With the power on, adjust the potentiometer until VCE = 7.5 V using
the 2N3904 transistor. Use the commercial values of RC and RE as determined in
Parts 2(a) and 2(b).

d. Turn off the supply and disconnect R2 from the base of the transistor. Measure the
series resistance defined by R1 + R2 and record below. Then determine the closest
available commercial value (available in the laboratory) and insert below and on Fig.
11.2. Obtain the chosen resistor and record the measured value in Fig. 11.2.
RB (measured) = R1 + R2=
RB (commercial value) =

e. Rebuild the network of Fig. 11.2 with the commercial values determined in the above
steps. Measure the voltages VRC and VCE and calculate the current IC using the
measured resistance value for RC.

In addition, measure the voltage VB and calculate the current IB. Finally, calculate
the beta of the transistor.

VRC (measured) =
VCE (measured) =
Ic (calculated from measured) =
IB (from measured) =
β (calculated) =

f. Referring to the results of Part 2(e), how do the resulting values of ICQ and VCEQ
compare to the specified values?
Exp. 10 143

Calculate the percent deviations between all specified and measured values. Use
specified values as the standard of comparison.

g. The Resume of Theory introduced the ratio RB/RE as an indication of the relative
stability of the system. Determine the ratio and record below.

RB/βRE (calculated) =

h. Rebuild Fig. 11.2 with the 2N4401 transistor and the same values OF RC and RE and
repeat Parts 2(c) and 2(d).
RB (calculated) =
RB (commercial value) =

i. Referring to Part 1(h), did the value of RB change with the use the transistor with a
higher beta?

Why did the value of RC and RE remain the same for both transistors?

j. Repeat Part 2(e) using the 2N4401 transistor.

VRC (measured) =
VCEQ (measured) =
ICQ (calculated from measured) =
β(calculated) =

k. Referring to the results of Part 2(j), how do the resulting values ICQ and VCEQ compare
to the specified values? Calculate the percent deviation between the present values
and those specified.

I. Since the Q-point for this design is the same for the collector feedback circuit of Part
1, the magnitudes of beta for each transistor should also be very close for each
configuration. Is this conclusion verified by the results of Parts 2(e) and 2(j)?
Exp. 10 144

m. Determine the ratio RB/ βRE for this configuration and compare to the level calculated
for the 2N3904 transistor.

RB/ βRE (2N4401) (calculated) =

RB/ βRE (2N3904) (calculated) =

Compare the results just obtained. What do the results suggest about the two
networks when we discuss their relative stability?

n. Rebuild the network of Fig. 11.2 with the level of RC, RE, and RB calculated for the
2N3904 transistor. However, this time insert the 2N4401 transistor so we can measure
the change in IC due to a change in beta. Energize the network and measure the voltage
VRC . Using the measured resistance value for Rc, calculate ICQ and then determine
S( β ) = % ΔIC or the first design.
%Δ β

S(β) (calculated) =

Part 3. Voltage-Divider Configuration

Circuit Specifications:
VCC = 15 V, ICC= 5 mA, VCE = 7.5 V

Design Procedure:

The Q-point is the same as defined in Parts 1 and 2. In addition, we will continue to apply
the rule that VE = 0.1 VCC.

a. For the given specifications, calculate the required value of RC for the voltage-
divider configuration of Fig. 11.3. Determine the closest commercial value
(available in the laboratory) and record below and in Fig. 11.3. Record the
measured resistor value in the space provided in Fig. 11.3.
Exp. 10 145

Figure 11-3

RC (calculated) =

RC (commercial value) =

b. Using VE = 0.1 VCC = 1.5 V, calculate the required value of RE for the network of Fig.
11.3. Determine the closest commercial value (available in the laboratory) and
record below and in Fig. 11.3. Insert the measured resistor value in the space
provided in Fig. 11.3.
RE (calculated) =
RE (commercial value) =

c. Assuming βRE > 10R2 permits the use of Eq. 11.9 of the Resume of Theory to define
the relationship between RI and R2, determine that relationship using the circuit
specifications.

Relationship:

d. Using β = 100 and RE as determined in Part 3(b) (commercial value), calculatethe

maximum value of R2 to satisfy the condition β RE > 10R2
R2 (calculated) =

Choose the nearest standard commercial value (available in the laboratory) for R2
and calculate the required value of R1 using the commercial value for R2 in Eq. 11.9

R2 (commercial value) =
R1 (calculated) =

Choose the next lowest standard commercial value (available in the laboratory) for
R1 and list below:
R1 (commercial value) =

e. Using the chosen standard commercial values, construct the network of Fig. 11.3
and insert the measured value for each resistor. Measure the voltages and V R C and
VCEQ and calculate the current ICQ using the measured resistance value for RC.
Finally, make a careful measurement of V R 1 and V R 2 (at least to the hundredths
Exp. 10 146

place) and calculate the currents I1 and I2 to the same level of accuracy using
measured resistor values. Then determine IB and calculate β.

V RC (measured) =
VCEQ(measured) =
ICQ(calculated from measured) =
β(calculated) =

Are the resulting values of ICQ and VCE relatively close to the specified values?
Calculate the percent deviations between the present values and their specified
values.

If not, try to explain why. How would you correct the situation?

f. The Resume of Theory introduced the ratio R1||R2/βRE as an indication of the

relative stability of the design. Determine the ratio and record below.

R1||R2/ΒRE (calculated) =

g. Rebuild Fig. 11.3 with the 2N4401 transistor and repeat Part 3(e).

VRC (measured) =
VCEQ (measured) =
ICQ (calculated from measured) =
β (calculated) =

h. Referring to the results of Part 3(g), how do the resulting values of ICQ and
VCEQ compare to the specified values even though β has been significantly
increased?

i. How do the levels of beta for this part of the experiment compare to the levels
determined in Parts 1 and 2?
Exp. 10 147

j. Determine the ratio of the relative stability for this configuration and compare
to that calculated for the 2N3904 transistor.
R1||R2/βRE (2N4401) (calculated) =
R1||R2/βRE (2N3904) (calculated) =

What do the results suggest about the impact of β on the stability of the
voltage-divider configuration

k. Determine the stability factor S(β) = %ΔIC/ %Aβ using the data of Parts3(e)

and 3(g).

S(β) (calculated) =
Exp. 10 148

Name
Date
Instructor

12
EXPERIMENT

MOSFET DC Bias:
Voltage-Divider
Biasing

OBJECTIVE
To set the Q-point of Common Source Amplifier using voltage divider biasing network.

EQUIPMENT REQUIRED

Instruments

(1) DMM

Components

Resistors
Since this is a design experiment, a number of the required resistors
are not specified in the equipment list. They will have to be requested
from the stockroom once their values are determined.

(1) 300-Ω, 1.2-kΩ, 1.5-kΩ, 3-kΩ, 15-kΩ, 100-kΩ

(1) 1-MΩ potentiometer
Other resistors as required by the designs

Transistors

2N7000 MOSFET

Supplies
(1) DC power supply

EQUIPMENT ISSUED
Item Laboratory serial no.
DMM
DC power supply

136
Exp. 13 137

PROCEDURE

1. Plot the line and the transfer curve to find the Q-point.
2. Using the following equations:

V G  R 2 V DD
R 1  R 2

Input loop : V GS  V G  I D R S
Output loop : V DS  V DD  I D ( R S  R D )

3. Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID = 0 and ID = VG/RS and VGS = 0 and find k.
4. Plot the transfer curve using VGSTh, ID = 0 and VGS (on), ID(on); all given in the specification sheet.

5. Plot the line and the transfer curve like below graph:

6. Using the value of ID at the Q-point, solve for the other variables in the bias circuit.
7. Calculate IDQ and VGSQ and VDS for network above.
Exp. 13 137
138 Exp. 10 /Design of BJT Bias Circuits

IDQ

VGSQ

VDS

8. Measure IDQ and VGSQ and VDS for network above.

IDQ

VGSQ

VDS
 Name
Date
Instructor

13
EXPERIMENT

MOSFET DC Bias

OBJECTIVE
To show the biasing, gain, frequency response and impedance properties of a MOSFET
Common Drain Amplifier.

EQUIPMENT REQUIRED

Instruments

(1) DMM

Components

Resistors
Since this is a design experiment, a number of the required resistors
are not specified in the equipment list. They will have to be requested
from the stockroom once their values are determined.

(1) 300-Ω, 1.2-kΩ, 1.5-kΩ, 3-kΩ, 15-kΩ, 100-kΩ

(1) 1-MΩ potentiometer
Other resistors as required by the designs

Transistors

2N7000 MOSFET

Supplies
(1) DC power supply
EQUIPMENT ISSUED

136
Exp. 10 137

Item Laboratory serial no.

DMM
DC power supply

RESUME OF THEORY
Common Drain CD is one of the most popular configurations of small-signal MOSFET amplifiers. CD has the
characteristic of high input impedance. The value of the input impedance is basically limited only by the biasing
resistors RG1 and RG2. Values of RG1 and RG2 are usually chosen as high as possible to keep the input impedance
high. High input impedance is desirable to keep the amplifier from loading the signal source. One popular biasing
scheme for the CS and CD configurations consists of the voltage divider RG1 and RG2. This voltage divider supplies
the MOSFET gate with a constant DC voltage. The main difference with the BJT biasing scheme is that ideally no
current flows from the voltage divider into the MOSFET.
The CD MOSFET amplifier can be compared to the CC BJT amplifiers. The CD amplifier is comparable to the CC
amplifier with the characteristics of high input impedance, low output impedance, and less than unity voltage gain.
The corner frequencies of the CD frequency response can also be approximated using the short circuit and open circuit
time constant methods.
The 2N7000 MOSFET used in this project is a n-channel enhancement-type MOSFET. For the enhancement-type
MOSFET, the gate to source voltage must be positive and no drain current will flow until VGS exceeds the positive
threshold voltage VT. VT is a parameter of each particular MOSFET and is temperature sensitive. This parameter
sensitivity to temperature is one reason for establishing a stable DC bias. The 2N7000 MOSFET data sheet lists the
minimum and maximum values of VT as 0.8 V and 3.0 V respectively.

Design Criteria

Design a common drain amplifier as shown in Figure 14.1 with the following specifications:
1. Use a 2N7000 MOSFET and a 20 volt DC supply
2. Midband gain VO/VI  0.5
3. Low cutoff frequency FL  100 Hz
4. VO symmetric swing  5.0 volts peak (10 V p - p)
 Load resistor RL = 200 
6. Source resistance RI = 50  (this is in addition to the Tektronix function generator's internal resistance)
138 Exp. 10 /Design of BJT Bias Circuits

PROCEDURE
1. Find the value of the threshold voltage VT and conductivity parameter K from the digital curve
tracer (remember the relation ID = K[VGS - VT]2 in the saturation region).
2. Determine the value of rds from the digital curve tracer. The slope of the transistor ID-VDS curves
in the active region is 1/rds.
3. Construct the CD circuit shown in Figure 14-1. Remember RI is installed in addition to the internal
50  resistance of the function generator.
4. Verify that the specifications have been met by measuring the Q-point, midband voltage gain, and
peak symmetric output voltage swing. Note any distortion in the output signal.
5. Adjust the output signal to obtain the maximum, non-distorted output voltage swing. Is the design
specification met?
6. Observe the loading affect by replacing RL first by 500  and then by 25 k. Note any changes in
the output signal and comment on the loading affect.
7. Use computer control to record and plot the frequency response. Find the corner frequencies and
bandwidth to verify that the specifications have been met.
8. Measure the input impedance seen by the source [look at the current through RI and the node
voltage on the transistor side of RI] and the output impedance seen by the load resistor [look at the
open circuit voltage and the current through and voltage across RL]. Verify that the input
impedance specification has been met.
 Name
Date
Instructor

14
EXPERIMENT

MOSFET Common
Drain Amplifier

OBJECTIVE
To show the biasing, gain, frequency response and impedance properties of a MOSFET
Common Drain Amplifier.

EQUIPMENT REQUIRED

Instruments

(1) DMM

Components

Resistors
Since this is a design experiment, a number of the required resistors
are not specified in the equipment list. They will have to be requested
from the stockroom once their values are determined.

(1) 300-Ω, 1.2-kΩ, 1.5-kΩ, 3-kΩ, 15-kΩ, 100-kΩ

(1) 1-MΩ potentiometer
Other resistors as required by the designs

Transistors

2N7000 MOSFET

Supplies
(1) DC power supply

Item Laboratory serial no.

DMM
DC power supply
EQUIPMENT ISSUED

136
Exp. 10 137

RESUME OF THEORY
Common Drain CD is one of the most popular configurations of small-signal MOSFET
amplifiers. CD has the characteristic of high input impedance. The value of the input impedance is basically
limited only by the biasing resistors RG1 and RG2. Values of RG1 and RG2 are usually chosen as high as
possible to keep the input impedance high. High input impedance is desirable to keep the amplifier from
loading the signal source. One popular biasing scheme for the CS and CD configurations consists of the
voltage divider RG1 and RG2. This voltage divider supplies the MOSFET gate with a constant DC voltage.
The main difference with the BJT biasing scheme is that ideally no current flows from the voltage divider
into the MOSFET.
The CD MOSFET amplifier can be compared to the CC BJT amplifiers. The CD amplifier is
comparable to the CC amplifier with the characteristics of high input impedance, low output impedance,
and less than unity voltage gain. The corner frequencies of the CD frequency response can also be
approximated using the short circuit and open circuit time constant methods.
The 2N7000 MOSFET used in this project is a n-channel enhancement-type MOSFET. For the
enhancement-type MOSFET, the gate to source voltage must be positive and no drain current will flow
until VGS exceeds the positive threshold voltage VT. VT is a parameter of each particular MOSFET and is
temperature sensitive. This parameter sensitivity to temperature is one reason for establishing a stable DC
bias. The 2N7000 MOSFET data sheet lists the minimum and maximum values of VT as 0.8 V and 3.0 V
respectively.

Design Criteria

Design a common drain amplifier as shown in Figure 14.1 with the following specifications:
1. Use a 2N7000 MOSFET and a 20 volt DC supply
2. Midband gain VO/VI  0.5
3. Low cutoff frequency FL  100 Hz
4. VO symmetric swing  5.0 volts peak (10 V p - p)
 Load resistor RL = 200 
6. Source resistance RI = 50  (this is in addition to the Tektronix function generator's internal
resistance)
138 Exp. 10 /Design of BJT Bias Circuits

PROCEDURE
1. Find the value of the threshold voltage VT and conductivity parameter K from the digital curve
tracer (remember the relation ID = K[VGS - VT]2 in the saturation region).
2. Determine the value of rds from the digital curve tracer. The slope of the transistor ID-VDS curves
in the active region is 1/rds.
3. Construct the CD circuit shown in Figure 14-1. Remember RI is installed in addition to the internal
50  resistance of the function generator.
4. Verify that the specifications have been met by measuring the Q-point, midband voltage gain, and
peak symmetric output voltage swing. Note any distortion in the output signal.
5. Adjust the output signal to obtain the maximum, non-distorted output voltage swing. Is the design
specification met?
6. Observe the loading affect by replacing RL first by 500  and then by 25 k. Note any changes in
the output signal and comment on the loading affect.
7. Use computer control to record and plot the frequency response. Find the corner frequencies and
bandwidth to verify that the specifications have been met.
8. Measure the input impedance seen by the source [look at the current through RI and the node
voltage on the transistor side of RI] and the output impedance seen by the load resistor [look at the
open circuit voltage and the current through and voltage across RL]. Verify that the input
impedance specification has been met.
Voltage-Divider Biasing

Fig 1: Voltage-Divider Biasing MOSFET

Part: 1
Plot the line and the transfer curve to find the Q-point.
Using the following equations:

R 2 V DD
V G 
R 1  R 2
Input loop : VGS  VG  I D R S
Output loop : V DS  V DD  I D ( R S  R D )

1. Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID = 0

and ID = VG/RS and VGS = 0
2. Find k
3. Plot the transfer curve using VGSTh, ID = 0 and VGS (on),
ID(on); all given in the specification sheet.
Plot the line and the transfer curve like below graph:

Fig 2:

Part 2:
Voltage-Divider Bias Q-Point
Where the line and the transfer curve intersect is the Q-
Point.
Using the value of ID at the Q-point, solve for the other
variables in the bias circuit.
Part:3
Calculate IDQ and VGSQ and VDS for
network above

IDQ
VGSQ
VDS

Part:4
Measure IDQ and VGSQ and VDS for
network above
IDQ
VGSQ
VDS