Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

Correction TD 3
Circuits séquentiels VHDL

Avril 2024

1 Correction exercice 1 :

— Front montant de clk :

— Si sel = 0 , Q ←− D0
— Si sel = 1 , Q ←− D1
— Absence du Front montant en clk :
— Qn = Qn−1

Figure 1 – Mux2_Syn

Listing 1 – Mux2_sync

1 Library IEEE;
2 use IEEE.std_logic_1164.all;

3 --Definition d'entite
4 entity Mux2_Syn is
5 Port (D0,D1,CLK,Sel : in std_logic;
6 Q : out std_logic);
7 end Mux2_Syn;

8 Architecture Arch1 of Mux2_Syn is

9 --signal de memorisation
10 signal x : std_logic := '0';
11 begin
12 Process (CLK)
13 begin
14 if (clk'event and clk='1') then --Front montant
15 if (sel = '0') then
16 x <= D0;

Correction TD 3 R.Hertelli : [email protected] 1/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

17 elsif (sel='1') then

18 x <= D1;
19 end if;
20 end if;
21 end process;

22 Q <= X; -- update sortie;

23 end Arch1;

Listing 2 – Stimulus Mux2_sync

1 Library IEEE;
2 use IEEE.std_logic_1164.All;

3 Entity test_Mux2_Syn is
4 end test_Mux2_Syn; --Empty entitu

5 architecture testbench of test_Mux2_Syn is

6 --Importation composant
7 Component Mux2_Syn is
8 Port (D0,D1,CLK,Sel : in std_logic;
9 Q : out std_logic);
10 end Component;

11 --Signaux de test
12 signal t_D0,t_D1, t_sel,t_Q : std_logic ;
13 signal t_clk : std_logic := '0';

14 begin
15 --Instantiation et port mapping
16 U1 : Mux2_Syn port map (t_D0,t_D1,t_clk,t_sel,t_Q);
17 t_clk <= not (t_clk) after 50 ns; --Generatation Horloge

18 stimulus : process

19 t_D0 <= '1';

20 t_D1 <= '0';
21 t_sel <= '1';
22 wait for 100 ns;

23 t_sel <= '0';

24 wait for 100 ns;
25 end process;
26 end testbench;

Correction TD 3 R.Hertelli : [email protected] 2/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

2 Correction exercice 2 :
2.1 Conception Reg_8

Figure 2 – Reg8

Listing 3 – Reg_8

1 Library IEEE;
2 use IEEE.std_logic_1164.all;

3 entity Reg8 is
4 port (D : in std_logic_vector (7 downto 0);
5 CLK,reset : in std_logic;
6 Q : out std_logic_vector (7 downto 0));
7 end Reg8;
8 architecture arch of Reg8 is
9 --signal memorisation
10 signal x : std_logic_vector(7 downto 0);
11 begin
12 process (CLK,reset)
13 begin
14 if ( reset = '0') then --Reset Asynchrone
15 x <= (others => '0') ; -- "0000 0000"
16 elsif (clk'event and clk='1') then
17 x <= D;
18 end if;
19 end process;

20 Q <= X; -- update Output;

21 end arch;

22 architecture arch2 of Reg8 is

23 --signal memorisation
24 signal x : std_logic_vector(7 downto 0);
25 begin
26 Q <= X;
27 process (clk) --Reset Synchrone
28 begin
29 if (clk'event and clk ='1') then

Correction TD 3 R.Hertelli : [email protected] 3/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

30 if (reset = '0') then X <= (others => '0'); reset

31 else
32 X <= D ; --Chargement
33 end if;
34 end if;
35 end process;
36 end arch2;

Listing 4 – Simulation Reg_8

1 Library IEEE;
2 use IEEE.std_logic_1164.all;
3 entity TB_Reg8 is
4 end TB_Reg8;

5 Architecture testBench of TB_Reg8 is

6 Component Reg8 is
7 port (D : in std_logic_vector (7 downto 0);
8 CLK,reset : in std_logic;
9 Q : out std_logic_vector (7 downto 0));
10 end Component;

11 signal t_clk : std_logic := '0';

12 signal t_D, t_Q : std_logic_vector (7 downto 0);
13 signal t_reset : std_logic;

14 begin
15 UT : Reg8 port map (t_D,t_clk,t_reset,t_Q);
16 t_clk <= not (t_clk ) after 25 ns;

17 process
18 begin
19 t_D <= (others => '1');
20 t_reset <= '0';
21 wait for 200 ns;
22 t_reset <= '1';
23 wait for 100 ns;
24 end process;
25 end testBench;

2.2 Conception Reg_n

Listing 5 – Reg_n

1 Library IEEE;
2 use IEEE.std_logic_1164.all;

Correction TD 3 R.Hertelli : [email protected] 4/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

Figure 3 – Regn

3 --Entite
4 Entity Reg_n is
5 generic (n : positive);
6 port (D : in std_logic_vector ((n-1) downto 0);
7 clk, reset : in std_logic;
8 Q : out std_logic_vector ((n-1) downto 0) );
9 end Reg_n;

10 --Architecture

11 Architecture arch of Reg_n is

12 --declaration et definition du signal interne de memorisation

13 signal r : std_logic_vector ((n-1) downto 0) := (others => '0');
14 begin
15 process (clk)
16 begin
17 if (clk'event and clk='1') then
18 if (reset = '0') then
19 r <= (others => '0');
20 else
21 r <= D;
22 end if;
23 end if;
24 end process;
25 --mise a jour de la sortie
26 Q <= r;
27 end arch;

Listing 6 – Simulation Reg_n

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;

Correction TD 3 R.Hertelli : [email protected] 5/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

4 entity TB_Reg_n is
5 generic (h : positive := 16);
6 end TB_Reg_n;

7 architecture testbench of TB_Reg_n is

8 --imporation des composasants

9 component Reg_n is
10 generic (n : positive);
11 port (D : in std_logic_vector ((n-1) downto 0);
12 clk, reset : in std_logic;
13 Q : out std_logic_vector ((n-1) downto 0) );
14 end component;

15 -- signaux interne
16 signal t_clk : std_logic := '0';
17 signal t_D,t_Q : std_logic_vector ( (h-1) downto 0);
18 signal t_reset : std_logic;

19 signal x : integer;
20 begin
21 --Instantiation , generic map and port mapping
22 UT : Reg_n generic map(h) port map (t_D,t_clk,t_reset,t_Q);
23 --Genration du signal carre
24 t_clk <= not (t_clk) after 25 ns;

25 process
26 begin
27 t_reset <= '0';
28 x <= 15;
29 t_D <= conv_std_logic_vector (x,h);
30 wait for 100 ns;

31 t_reset <= '1';

32 x <= 15;
33 t_D <= conv_std_logic_vector (x,h);
34 wait for 100 ns;

35 t_reset <= '1';

36 x <= 10;
37 t_D <= conv_std_logic_vector (x,h);
38 wait for 100 ns;
39 end process;
40 end testbench;

3 Correction exercice 3 :

Listing 7 – Shifter 4

Correction TD 3 R.Hertelli : [email protected] 6/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

— Si Load = 0 , On charge le registre

Q(n) ←− R(n)
— Si Load = 1 , le décalage est autorisé.

— Pour Lef t = 1 , on fait décalage à gauche.

— Pour Right = 1 , on fait décalage à droite.
— Le cas Lef t = Right = 1 n’est pas autorisé.
Figure 4 – Shifter4

1 Library IEEE;
2 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_arith.all;
4 --Conv_Std_logic_vetor(X,n)
5 -- X : entier
6 -- n taille std_logic_vector
7 --Convertie un entier X vers un std_logic_vector coded
8 -- sur n bits
9 entity shifter4 is
10 port (R : in std_logic_vector(3 downto 0);
11 clk, load,left,right : in std_logic;
12 Q : out std_logic_vector(3 downto 0));
13 end shifter4;

14 Architecture Arch of shifter4 is

15 --signal de memorisation
16 signal x : std_logic_vector(3 downto 0) ;
17 begin
18 process (clk, load)
19 begin
20 Q <= x; --Update sortie
21 if (load = '0') then x <= R ; --Chargement
22 elsif (load ='1') then -- Pas de chargement
23 if (clk'event and clk= '1') then
24 if (left ='1' and right ='0') then
25 --Decalage a gauche
26 x(3) <= x(2);
27 x(2) <= x(1);
28 x(1) <= x(0) ;
29 x(0) <= '0';
30 elsif (left ='0' and right ='1') then
31 x(0) <= x(1);
32 x(1) <= x(2);
33 x(2) <= x(3);
34 x(3) <= '0';
35 end if;
36 end if;
37 end if;
38 end process;
39 end Arch;

Correction TD 3 R.Hertelli : [email protected] 7/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

40 Architecture Arch2 of shifter4 is

41 --signal de memorisation
42 signal x : std_logic_vector(3 downto 0) ;
43 begin
44 process (clk, load)
45 begin
46 Q <= x; --Update sortie
47 if (load = '0') then x <= R ; --Chargement
48 elsif (load ='1') then -- Pas de chargement
49 if (clk'event and clk= '1') then
50 if (left ='1' and right ='0') then --Decalage
,→ gauche

51 for I in 3 downto 1 loop -- I= 0,1,2,3

52 x(I) <= X(I-1);
53 end loop;
54 X(0) <= '0';
55 elsif (left ='0' and right ='1') then

56 for I in 0 to 2 loop
57 X(I) <= X(I+1);
58 end loop;
59 X(3) <= '0';
60 end if;
61 end if;
62 end if;
63 end process;
64 end Arch2;

65 -- Arch3
66 Architecture Arch3 of shifter4 is

67 signal x : std_logic_vector(3 downto 0);

68 signal v : unsigned (3 downto 0); --Entier non signe code sur 4 bits
69 signal deux : unsigned (3 downto 0) := 2;
70 signal d : std_logic_vector (3 downto 0) := "0010";
71 begin

72 process (clk,load)
73 begin
74 if (load ='0') then
75 x <= R;
76 elsif (load ='1') then
77 if (clk'event and clk = '1') then
78 if (left = '1' and right ='0')then
79 -- decalage gauche
80 --X convertie en unsigned puis affecter a V
81 v <= unsigned (x);
82 --Decalage
83 --v <= v * unsigned (3 downto 0) (2);
84 -- v <= v * unsigned(d);
85 v <= v * deux;
86 x <= Conv_Std_logic_vetor (V,4);
87 elsif (left ='0' and right ='1') then
88 -- Decalage Droite
89 v <= unsigned(x);

Correction TD 3 R.Hertelli : [email protected] 8/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

90 v <= v/deux;
91 x <= Conv_Std_logic_vetor (V,4);
92 end if;
93 end if;
94 end if;
95 end process;
96 Q <= x; -- Update output
97 end Arch3;

Listing 8 – Simulation Shifter4

1 Library IEEE;
2 use IEEE.std_logic_1164.all;

3 entity test_Shifter4 is
4 end test_Shifter4;

5 architecture testbech of test_Shifter4 is

6 component shifter4 is
7 port (Load ,left,right,clk : in std_logic;
8 R : in std_logic_vector (3 downto 0);
9 Q : out std_logic_vector (3 downto 0) );
10 end component;

11 signal clock : std_logic := '0';

12 signal ld, lt, rt : std_logic;

13 signal Rin ,Qout : std_logic_vector (3 downto 0);

14 begin
15 clock <= not (clock) after 25 ns;

16 UT : shifter4 port map (ld,lt,rt,clock,Rin,Qout);

17 process
18 begin
19 Rin <= "0000";
20 Ld <= '1';
21 Lt <= '1';
22 Rt <= '1';

23 wait for 50 ns;

24 -- chargement d'un mot

25 Rin <= "0101";
26 Ld <= '0';
27 Lt <= '1';
28 Rt <= '1';

Correction TD 3 R.Hertelli : [email protected] 9/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

29 wait for 100 ns;

30 --Decalge Left
31 Rin <= "0001";
32 Ld <= '1';
33 Lt <= '1';
34 Rt <= '0';

35 wait for 100 ns;

36 --Decalge Droite
37 Rin <= "0010";
38 Ld <= '1';
39 Lt <= '0';
40 Rt <= '1';

41 wait for 100 ns;

42 end process;
43 end testbech;

4 Correction exercice 4 :

Figure 5 – ROM_128_8

Listing 9 – Conception ROM_128_8

1 Library IEEE;
2 use IEEE.std_logic_1164.all;
3 use ieee.numeric_std.all;

4 entity ROM_128_8 is
5 port ( ADD : in std_logic_vector (6 downto 0);

Correction TD 3 R.Hertelli : [email protected] 10/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

6 DATA : out std_logic_vector (7 downto 0));

7 end ROM_128_8;

8 architecture arch_ROM of ROM_128_8 is

9 -- Definition d'un sous type appele mot

10 subtype mot is std_logic_vector ( 7 downto 0);
11 --definition de la matrice du memoire
12 type matrice is array ( 0 to 127) of mot;

13 signal memoire : matrice; -- Declaration de l'espace memoire

14 begin
15 process ( ADD)
16 begin
17 -- Convertir ADD en entier qui sera exploite comme indice de matrice.
18 DATA <= memoire (TO_INTEGER(unsigned(ADD)));
19 end process;
20 end arch_ROM;

5 Correction exercice 5 :

— Si Enable = 0 , la mémoire est verrouillée

. La sortie est à haute impédance.

— Si Enable = 1 , on peut lire et écrire dans

la mémoire

— Pour R/W = 0 : write ; R/W = 1 : Read

Figure 6 – Simple RAM

Listing 10 – Conception Simple Port RAM

1 Library IEEE;
2 use IEEE.std_logic_1164.all;
3 use ieee.numeric_std.all;

4 entity RAM_SP_32_8 is
5 port ( H,RW, Enable : in std_logic;
6 ADD : in std_logic_vector ( 4 downto 0);
7 DATA_IN : in std_logic_vector ( 7 downto 0);
8 DATA_OUT : out std_logic_vector ( 7 downto 0));
9 end RAM_SP_32_8;

Correction TD 3 R.Hertelli : [email protected] 11/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

10 architecture compr_SP_RAM of RAM_SP_32_8 is

11 -- Definition d'un sous type "mot"

12 subtype mot is std_logic_vector ( 7 downto 0);
13 --definition de la matrice du memoire
14 type matrice is array ( 0 to 31) of mot;

15 signal memoire : matrice;

16 begin
17 process (H,Enable,ADD,RW)
18 begin
19 if (Enable = '0')then
20 DATA_OUT <= (others => 'Z');
21 elsif (Enable ='1') then
22 if ( H = '1' and H'event ) then
23 if (RW = '0') then --Write
24 memoire(TO_INTEGER (unsigned (ADD))) <= DATA_IN;
25 elsif (RW = '1') then --Read
26 DATA_OUT <= memoire(TO_INTEGER (unsigned (ADD)));
27 end if ;
28 end if;
29 end if;
30 end process;
31 end compr_SP_RAM;

Listing 11 – Test Simple Port RAM

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;

4 entity tB_SP_RAM is
5 end tB_SP_RAM;

6 architecture testbench of tB_SP_RAM is

7 component RAM_SP_32_8 is
8 port ( H,RW, Enable : in std_logic;
9 ADD : in std_logic_vector ( 4 downto 0);
10 DATA_IN : in std_logic_vector ( 7 downto 0);
11 DATA_OUT : out std_logic_vector ( 7 downto 0));
12 end component;

13 --Sigaux Internes
14 Signal clock : std_logic := '0';
15 signal t_RW, t_Enable : std_logic;
16 signal t_ADD : std_logic_vector ( 4 downto 0);
17 signal t_DATA_IN, t_DATA_OUT : std_logic_vector ( 7 downto 0);

Correction TD 3 R.Hertelli : [email protected] 12/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

18 constant PERIOD : time := 10 ns;

19 begin

20 U1 : RAM_SP_32_8 port map (clock,t_RW,t_Enable,t_ADD,t_DATA_IN, t_DATA_OUT);

21 clock <= not(clock) after PERIOD;

22 process
23 begin
24 t_Enable <= '0';
25 t_RW <= '0';
26 t_ADD <= (t_ADD'range => '0');
27 t_DATA_IN <= ( t_DATA_IN'range => '0');

28 wait for 4* PERIOD;

29 -- Test Write
30 t_enable <= '1';
31 for i in 0 to 31 loop
32 t_DATA_IN <= t_DATA_IN + "10";

33 wait for PERIOD;

34 t_ADD <= t_ADD + '1';

35 end loop;

36 t_Enable <= '0';

37 t_RW <= '0';
38 t_ADD <= (t_ADD'range => '0');
39 t_DATA_IN <= ( t_DATA_IN'range => '0');

40 -- Test Read
41 t_enable <= '1';
42 t_RW <= '1';
43 for i in 0 to 31 loop

44 wait for 2*PERIOD;

45 t_ADD <= t_ADD + '1';
46 wait for 2*PERIOD;

47 end loop;

48 end process;
49 end testbench;

Correction TD 3 R.Hertelli : [email protected] 13/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

6 Correction exercice 6 :

— La lecture est toujours permise contraire-

ment à l’écriture qui est conditionné par
le signal write_enable = 1.

— Pour éviter un conflit de ressource lors de

lecture et écriture dans la même case mé-
moire, on considère que l’écriture se fait
au front montant de l’horloge cependant
la lecture en front descendant.
Figure 7 – Double Port RAM

Listing 12 – Conception Double Port RAM

1 Library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;

4 entity RAM_DP_32_8 is
5 port (H,Write_Enable : in std_logic;
6 WRITE_ADD,READ_ADD : in std_logic_vector (4 downto 0);
7 DATA_IN : in std_logic_vector (7 downto 0);
8 DATA_OUT : out std_logic_vector(7 downto 0));
9 end RAM_DP_32_8;

10 architecture Arch of RAM_DP_32_8 is

11 -- Definition d un sous type MOT
12 subtype mot is std_logic_vector (7 downto 0);
13 --definition de la matrice du memoire (2^5 case)
14 type matrice is array ( 0 to 31) of mot;

15 --Declaration Espace memoire

16 signal memoire : matrice;

17 begin
18 process (H,Write_Enable)
19 begin
20 if (Write_Enable = '1') then --Ecriture dans RAM
21 if (H'event and H='1')then
22 memoire(TO_INTEGER(unsigned(WRITE_ADD))) <= DATA_IN;
23 end if;
24 else --Lecture du RAM
25 if (H'event and H='0') then
26 DATA_OUT <= memoire(TO_INTEGER(unsigned (READ_ADD)));
27 end if;
28 end if;
29 end process;
30 end Arch;

Correction TD 3 R.Hertelli : [email protected] 14/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

Listing 13 – Testbench Double Port RAM

1 Library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;

4 entity RAM_DP_32_8_tb is
5 end RAM_DP_32_8_tb;

6 architecture TESTBENCH of RAM_DP_32_8_tb is

7 Component RAM_DP_32_8 is
8 port (H,Write_Enable : in std_logic;
9 WRITE_ADD,READ_ADD : in std_logic_vector (4 downto 0);
10 DATA_IN : in std_logic_vector (7 downto 0);
11 DATA_OUT : out std_logic_vector(7 downto 0));
12 end Component;

13 --Sigaux Internes
14 Signal clock : std_logic := '0';
15 signal t_Write_Enable : std_logic;
16 signal t_WRITE_ADD, t_READ_ADD : std_logic_vector (4 downto 0);
17 signal t_DATA_IN, t_DATA_OUT : std_logic_vector (7 downto 0);
18 constant PERIOD : time := 25 ns;
19 begin
20 U1 : RAM_DP_32_8 port map (clock,t_Write_Enable,t_WRITE_ADD,
21 t_READ_ADD,t_DATA_IN, t_DATA_OUT);
22 clock <= not(clock) after PERIOD;

23 process
24 begin
25 --initialisation
26 t_Write_Enable <= '0';
27 t_WRITE_ADD <= (others => '0');
28 t_READ_ADD <= (others => '0');
29 t_DATA_IN <= (others => '0');

30 wait for 2*PERIOD;

31 t_Write_Enable <= '1';

32 for i in 0 to 31 loop
33 t_DATA_IN <= t_DATA_IN + "100";
34 wait for 2*PERIOD;
35 t_WRITE_ADD <= t_WRITE_ADD + '1';
36 end loop;

37 t_Write_Enable <= '0';

38 for i in 0 to 31 loop
39 wait for 2*PERIOD;
40 t_READ_ADD <= t_READ_ADD + '1';

Correction TD 3 R.Hertelli : [email protected] 15/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2023 / 2024 Iset Sousse

41 end loop;
42 end process;

43 end TESTBENCH;

Correction TD 3 R.Hertelli : [email protected] 16/16