Digital Systems Design Using Verilog 1st Edition Roth Solutions Manual instant download
Digital Systems Design Using Verilog 1st Edition Roth Solutions Manual instant download
https://testbankfan.com/product/digital-systems-design-using-
verilog-1st-edition-roth-solutions-manual/
https://testbankfan.com/product/digital-systems-design-using-
vhdl-3rd-edition-roth-solutions-manual/
https://testbankfan.com/product/advanced-digital-design-with-the-
verilog-hdl-2nd-edition-ciletti-solutions-manual/
https://testbankfan.com/product/digital-design-with-an-
introduction-to-the-verilog-hdl-vhdl-and-systemverilog-6th-
edition-mano-solutions-manual/
https://testbankfan.com/product/fundamentals-of-logic-design-7th-
edition-roth-solutions-manual/
Digital Design 5th Edition Mano Solutions Manual
https://testbankfan.com/product/digital-design-5th-edition-mano-
solutions-manual/
https://testbankfan.com/product/communication-systems-analysis-
and-design-1st-edition-stern-solutions-manual/
https://testbankfan.com/product/digital-signal-processing-using-
matlab-3rd-edition-schilling-solutions-manual/
https://testbankfan.com/product/microwave-circuit-design-a-
practical-approach-using-ads-1st-edition-yeom-solutions-manual/
https://testbankfan.com/product/digital-design-and-computer-
architecture-2nd-edition-harris-solutions-manual/
Chapter 6: Designing with Field Programmable Gate Arrays
6.1 (a) 4 Cells, if N is used as the clock enable. When N = 1 then
X0+ = S' D0 + S X1 (3 variable function) (two 3 variable functions
X1+ = S' D1 + S X2 (3 variable function) will fit into one cell)
If the clock enable is not used each bit requires a separate cell: 8 cells total.
X0+ = N S' D0 + N S X1 + N' X0 (5 variable function)
(b)
6.2 (a) QA0+ = En (Ld U + Ld' QA0') + En' QA0 = En (X) + En' QA0
QA1+ = En (Ld V + Ld' (QA0 QA1) + En' QA1 = En (Y) + En' QA1
(b)
X = Ld U + Ld' QA0'
Y = Ld V + Ld' (QA0 QA1)
123
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Q0+ = EN' Q0 + EN (Ld D0 + Ld' Q1)
(b) Two cells
(c) Y = Ld D3 + Ld' Si
X = Ld D2 + Ld' Q3
6.4 (a) The next state equation of Q1 can be implemented using the X function generator with the inputs
R, S, Q1, and Q2. The next state equation of Q2 can be implemented using the Y function
generator with the inputs T, Q1, and Q2. The output P can be implemented using the Z function
generator with the inputs T (C input) and the X function generator.
(b)
6.5 (a) M = S2'S1'S0'I0 + S2'S1'S0I1 + S2'S1S0'I2 + S2'S1S0I3 + S2S1'S0'I4 + S2S1'S0I5 + S2S1S0'I6 + S2S1S0I7
The 8-to-1 MUX can be decomposed into seven 2-to-1 MUXes, and implemented in four Figure
6-1(a) logic blocks.
124
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
M = S2'MX + S2MY
Mx = S1'M1 + S1M2
MY = S1’M3 + S1M4
M1 = S0'I0 + S0I1
M2 = S0'I2 + S0I3
M3 = S0'I4 + S0I5
M4 = S0'I6 + S0I7
The X and Y functions for each block each implement one 2-to-1 mux as labeled:
125
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(b) Three 2-to-1 MUXes (or a 4-to-1 mux) can be implemented in each Figure 6-3 logic block. In
total, three blocks are required to implement seven 2-to-1 MUXes. The X, Y, and Z function
generators for each block implement a 2-to-1 MUX as labeled:
(c) Each function generator used implements a 2-to-1 mux, and has the same LUT contents:
0, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1
126
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
6.6 (a) module Figure6_1a(X_in, Y_in, clk, CE, Qx, Qy, X, Y, XLUT, YLUT);
input [1:4] X_in, Y_in;
input clk, CE;
input [0:15] XLUT, YLUT;
inout X, Y;
output Qx, Qy;
initial begin
Qx = 1'b0;
Qy = 1'b0;
end
6.7 (a) module Figure6_3(X_in, Y_in, clk, CE, C, Qx, Qy, X, Y, XLUT, YLUT,
ZLUT,
SA, SB, SC, SD);
input [1:4] X_in, Y_in;
input clk, CE, C;
input [0:15] XLUT, YLUT;
input [0:7] ZLUT;
input SA, SB, SC, SD;
output X, Y;
output reg Qx, Qy;
127
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
initial begin
Qx = 1'b0;
Qy = 1'b0;
end
assign X = MuxB;
assign Y = MuxD;
endmodule
Figure6_3 B0(D_in, D_in, clk, 1'b1, 1'b0, Q3, Q2, T1, T2,
16'b0001111111000000,
16'b0110000001000000, 8'b00000000, 1'b0, 1'b0, 1'b0,
1'b0);
Figure6_3 B1(D_in, D_in, clk, 1'b1, 1'b0, Q1, T3, T4, Zout,
16'b1010001110000000,
16'b1010010110011000, 8'b00000000, 1'b0, 1'b0, 1'b0,
1'b0);
endmodule
6.8 (a) A 4-to-16 decoder requires 16 outputs, and each function needs no more than 4-variables. 8
Figure 6-1 (a) logic blocks are required.
6.10 Expanding F around X6 results in 4 variable functions which can be realized using one function
generator each.
F = X6 (X1' X2 X3 + X2 X3' X4' + X2 X3 X4') + X6' (X2' X3' X4 + X2 X3' X4' + X3' X4 X5) + X7
F = X6 (F1) + X6' (F2) + X7
For block one: X LUT has inputs X1, X2, X3, and X4 and realizes F1 = X1' X2 X3 + X2 X3' X4' + X2 X3
X4'.
Y LUT has inputs X2, X3, X4, and X5 and realizes F2 = X2' X3' X4 + X2 X3' X4' + X3' X4 X5
For block two: X LUT has the outputs of block one’s X LUT (F 1) and Y LUT (F2), X6, and X7 as
inputs. The X LUT realizes F = X6 (F1) + X6' (G1) + X7. The Y LUT is unused.
6.11 Expanding Q+ around U Q results in 4 variable equations which can be realized using one function
generator each.
For block one: X LUT has inputs V, W, X, and Y and realizes V' W + X' Y + V W'
Y LUT has inputs V, X, and Y and realizes V X' Y' + V' Y + X Y + V' X
129
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
For block two: X LUT has U, Q, and block one’s Xfunc and Yfunc as inputs and realizes
Q+ = U Q (Xfunc) + U' Q'(Yfunc)
6.12 To realize the next-state equations, we need to use at least four Kintex logic slices (Figure 6-13).
One Kintex logic slice is ¼ CLB. Therefore, only 1 CLB is needed.
6.13 One cell. Expanding around X5 results in 4 variable equations which can be realized using one
function generator each and X5 can be used as the C input.
X = X5 (X1' X2' X3' X4' + X1 X2 X3 X4) + X5' (X6 X7' X8' X9 + X6' X7 X8 X9')
Xfunc = (X1' X2' X3' X4' + X1 X2 X3 X4)
Yfunc = (X6 X7' X8' X9 + X6' X7 X8 X9')
Zfunc = X5 (Xfunc) + X5' (Yfunc)
130
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
6.14
6.15 (a) Expanding Z around Y results in 4 variable equations which can be realized using one function
generator each.
Z = Y (V W' X + U' V' W) + Y' (V W' X + T V' W)
Z = Zfunc = Y (Xfunc) + Y' (Yfunc)
131
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Implement internal logic cell connections in a manner similar to Problem 6.12 Solution with U,
V, W, and X as inputs to the X-function generator, T, V, W, and X as inputs to the Y-function
generator and Y as the C input.
Block 2: X-LUT has Y and Block 1’s Xfunc and Yfunc as inputs and realizes Z = Y (Xfunc) + Y'
(Yfunc)
Y-LUT is unused
6.16 F = X6 (X1' X2 X3' X4 + X2' X4' + X3 X4 X5 + X1 X3) + X6' (X2' X3' X4 + X2 X4 + X3' X4 + X1 X3)
132
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
6.18 Y = e'f ' Y00 + e'f Y01 + ef ' Y10 + efY11
Y00 = 0
Y01 = abcd
Y10 = a' bc'd ' + b'c'
Y11 = ab'cd + a'bc'd'
6.19 (a) Y = a' (bc'd'e + b'c'e) + a (b'cd'e + b'c'e + bcde) = a' (Y1) + a (Y2)
Y1 = bc'd'e + b'c'e
Y2 = b'cd'e + b'c'e + bcde
(b)
133
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(c)
bcde Y1 (Xfunc) Y2 (Yfunc)
0000 0 0
0001 1 1
0010 0 0
0011 1 1
0100 0 0
0101 0 1
0110 0 0
0111 0 0
1000 0 0
1001 1 0
1010 0 0
1011 0 0
1100 0 0
1101 0 0
1110 0 0
1111 0 1
6.20 (a) Eight LUTs are required. Each bit of the adder requires one LUT to generate the sum and one
LUT to generate the carry-out.
(b) Four LUT4s are required. Each bit of the adder requires one LUT4 to generate the sum.
Dedicated carry chain logic generates the carry-out.
134
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(c) When Su is 1, the circuit should add a to the 2’s complement of b by inverting each bit of b and
setting bit 0’s Cin to.
Su ai bi Cin Outi
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
135
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
136
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
6.21 (a) 14 cells total.
(b) 14 cells total: 6 for adders and 8 for AND gates but propagation delay is less.
6.22 (a) Z = A'(BC 'D ' EF ' + B'C 'E ' F + BC ' E ' F ') + A(B'CD ' E ' F + B'C ' E ' F + BCDE)
Z = A'(Z0) + A(Z1)
Z0 = D'(Y00) + D(Y01)
Y00 = BC ' EF ' + B'C ' E ' F + BC ' E ' F
Y01 = B'C ' E ' F + BC ' E ' F '
Z1 = D'(Y10) + D(Y11)
Y10 = B'C ' E ' F + B'CE ' F
Y11 = B'C ' E ' F + BCE
137
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(b)
138
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
6.23 (a) No solution available
(b)
(c)
139
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(d)
6.25 The sequential circuit requires 3 Virtex slices. For the first slice, the G inputs are Q2, C, D, and E (G
= Q2' C D E). The F inputs are Q2, A, B, and C (F = Q2 A B C). The BX input is Q1. Then the X flip-
flop implements the Q1 flip-flop. Also, if the FXA input is 1, the FXB input is 0, and the BY input is
Q1, then the Y flip-flop implements Q2. For the second slice, the G inputs are Q2, A, and B (G = Q2'
A B + Q2' A' B'). The F inputs are Q2, A, B, and C (F = Q2' A B' + Q2 (A' + B + C)). The BX input is
Q1. Then the output to the F5 MUX implements Z1. For the third slice, the G inputs are Q1, Q2, A,
and B (G = Q1 A' + Q1 B + Q2'). Then the Y combinational output implements Z2.
6.27 Stratix V logic module is similar to Stratix IV logic module, except that there are four flip flops
existing per logic module instead of the two in Stratix IV.
140
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
6.28
6.29 (a)
141
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(c)
6.30 S0: Q0Q1Q2Q3 = 1000, S1: 0100, S2: 0010, S3: 0001
Q0+ = St'Q0 + Q3
Q1+ = StQ0 + K 'M 'Q1 + K 'Q2
Q2+ = MQ1
Q3+ = KM 'Q1 + KQ2
Load = StQ0
Done = Q3
Sh = M'Q1 + Q2
Ad = MQ1
6.31 S0: Q0Q1Q2Q3Q4Q5Q6 = 1000000, S1: 0100000, S2: 0010000, S3: 0001000, S4: 0000100, S5:
0000010,
S6: 0000001
142
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Su = CQ5 + CQ6
V = CQ4
Cm1 = C 'QnegQ6
6.32 S0: Q3Q2Q1Q0 = 0000, S1: 1100, S2: 1010, S3: 1001
To create a one-hot encoding, if Q3 is 0 in the reset state it must be 1 in all other states.
(b) 5 Total:
1 Slice: Q0 (one LUT4 and FF), Q1 (one LUT4 and FF)
2.5 Slices: Q2: (each AND term in one half-slice, one half-slice combines 4 product terms, one
FF)
1 Slice: Q3 (one LUT4 and FF), Z1 (one LUT4)
½ Slice: Z2 (one LUT4)
6.34 To ensure proper synthesis, amend the code for Figure 4-15 as follows:
- Within the first process, ensure that all If-Then statements include an Else portion.
143
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Figure 4-40 uses fewer resources then Figure 4-35, and each synthesis option uses about the same
amount of resources. The solution to this problem may change depending on what synthesis tool
and target device is used.
A1 A0 B1 B0
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0 1
(b)
144
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
C1 C0 D1 D0
0 0 1 1
0 1 1 0
1 0 0 0
1 1 - -
D0 = C1'C0'
D1 = C1'
(c)
6.38 (a) Naïve implementation uses an 8-to-1 mux, 3 inverters (for not A), a 3-bit adder, and a 3-bit
register. The arithmetic right shift can be accomplished by feeding in C2C2C1.
An alternate implementation is possible if Co, Ad, and Sh will not become active at the same
time: use 3 tri-state buffers with tri-state controls Co, Ad, and Sh instead of the mux.
(b) The circuit is a basic ALU, with register. If Co is true, A is complemented and loaded into
register C. If Ad is true, A and B are added and loaded into C. If Sh is true, C is shifted right by
1. Sh has the highest priority, followed by Ad, and then by Co. Note that else clauses are not
used.
145
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
6.39 (a) Unoptimized: Two 4-to-1 muxes
a1 a0 b1 b0
0 0 1 0
0 1 0 0
1 0 1 1
1 1 0 1
b1 = a0'
b 0 = a1
(b)
6.40
6.41
146
© 2016 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Exploring the Variety of Random
Documents with Different Content
The Project Gutenberg eBook of Kepponen:
Huvinäytelmä kahdessa näytöksessä
This ebook is for the use of anyone anywhere in the United States
and most other parts of the world at no cost and with almost no
restrictions whatsoever. You may copy it, give it away or re-use it
under the terms of the Project Gutenberg License included with this
ebook or online at www.gutenberg.org. If you are not located in the
United States, you will have to check the laws of the country where
you are located before using this eBook.
Language: Finnish
KEPPONEN
Huvinäytelmä kahdessa näytöksessä
Kirj.
ERNST LUNDQUIST
Mukailtu suomennos
Haminassa,
Alfred Lagerbomin kustantama,
Kansankirjapainossa 1898.
HENKILÖT:
Ensimäinen näytös.
Ensimäinen kohtaus,
(Nousee ylös).
Gerda. En, vaan eiköhän se ole jotain hullutusta.
(Nousee ylös).
Malla. Sinä viekastelija! Mutta kun sinä nyt tiesit kuinka vaarallista
makaaminen minulle on, niin miksi et minua herättänyt?
Malla. Niin kyllä. Sinä voit kyllä niin sanoa — kun sinulla ei ole
sydämen rasvettumista. Mutta sen minä vain sanon, että ei ole
hauskaa alituisessa kuolettavassa levottomuudessa, ja tiedänpä
kyllä, miten tässä tulee lopuksi käymään.
Toinen kohtaus.
Tiina. Koko ajan kun minä katan ruokaa pöytään, niin istuu hän ja
sihtaa Gerda-ryökkinää, kun tämä istuu riippumatossaan ja lukee.
Kurman. Ahaa! — Ei, Tiina! Rouva tarkoittaa, että, eikö hänellä ole
tapana lyödä tarjotinta säpäleiksi, eli heittää sokeriastiata sinun
päähäsi?
Tiina. E-ei! Herra jesta kuitenkin. Eihän hän nyt mikään hullu ole.
Tiina. Voi herra jesta, mitä rouva puhuu. Minä otankin pois
tulitikut, niin että hänellä on vain kaksi tikkua päivässä
käytettävänään.
Kolmas kohtaus.
Neljäs kohtaus.
Kurman. Aksel.
(Käypi istumaan).
Aksel. Ei, eikä oikein minunkaan, voin vakuuttaa. Jos olisi sitä
ahtanut päivässä kymmenen tuntia päähänsä, niin sittenhän se ehkä
olisi mennyt — mutta silloin ei olisi sopinut Helsingissä olla ainakaan
niin kauvan, kun maa ei olisi niellyt sisäänsä Gambrinia ja Königiä,
sillä katsokaas, ne ovat minun heikkoja puoliani.
Viides kohtaus.
Kuudes kohtaus.
Aksel. Kurman.
Kurman. Jaa, mutta teenkö sen tai en? Siinäpä kysymys onkin.
Aksel. Kuulkaas, herra Kurman! Kun kaikki käy ympäri, niin olette
te yhtäläinen vekkuli kuin ystäväni Herman!
(Lyö näppiä).