21EC603- CMOS VLSI DESIGN

Class: III ECE

Academic Year:2023-2024 (EVEN Sem)

Module I: Issues and Challenges in Digital IC Design

Course handling faculty: Dr. M. Priyatharishini

 STATIC CMOS
• Designers accustomed to AND & OR functions
must learn to think in terms of NAND and NOR
to take advantage of static CMOS.
• In manual circuit design, this is often done
through bubble pushing.
• Compound gates are particularly useful to
perform complex functions with relatively low
logical efforts.
• In processes with multiple threshold voltages,
multiple flavors of gates can be constructed
with different speed/leakage power trade-offs
 Example 1
module mux(input S, D0, D1,
output Y);

assign Y = S ? D1 : D0;
endmodule

Sketch a design using AND, OR, and NOT gates.

D0
S
Y
D1
S

10: Combinational Circuits 3

 Bubble Pushing
• Start with network of AND / OR gate
• Convert to NAND / NOR + inverters
• Remember De-Morgan’s Law
Design a circuit to compute F = AB + CD using
i. NANDs and ii.NORs.
 Compound Gates
• The static CMOS also efficiently handles compound
gates computing various inverting combinations of
AND/OR functions in a single stage.
• In general, logical effort of compound gates can be
different for different inputs.
• The logical effort of each input is the ratio of the input
capacitance of that input to the input capacitance of
the inverter.
• For the AOI21 gate, this means the logical effort is
slightly lower for the OR terminal (C) than for the two
AND terminals (A, B).
 Compound Gates
Logical effort for compound gates:
 PSEUDO NMOS Logic
• Even though CMOS logic gates have very low
power dissipation, they have the following
limitations:
1.They occupy larger area than NMOS gates.
2.Due to the larger area, they have larger
capacitance.
3.Larger capacitance leads to longer delay in
switching.
• These limitations of the CMOS gates can be
reduced by several alternative structures
• Pseudo-NMOS logic, dynamic NMOS logic,
and domino logic are some of these special
CMOS structures.
pseudo-nMOS inverter
• The channel resistance of the pseudo-NMOS devices
is higher than that of the NMOS devices. Hence,
power dissipation is lower for the pseudo devices.
• Pseudo-NMOS circuits are useful in applications
where the output remains in logic-1 state most of
the time.
pseudo-nMOS NAND & NOR Logic:
Logical effort pseudo-nMOS Logic:
• The logical effort for a falling transition of the
pseudo-nMOS inverter gd is the ratio of its input
capacitance (4/3) to that of a unit complementary
CMOS inverter (3), i.e., 4/9. gu is three times as great
because the current is 1/3 as much
DYNAMIC LOGIC:
• Dynamic gates uses a clocked pMOS pull up
• The drawbacks of ratioed circuits include slow rising
transitions, contention on the falling transitions, static power
dissipation, and a nonzero VOL.
• Dynamic circuits circumvent these drawbacks by using a
clocked pull-up transistor
• Dynamic circuit operation is divided into two modes.
Pre-charge and evaluation.
• During pre-charge, the clock ɸ is 0, so the clocked
pMOS is ON and initializes the output Y high.
• During evaluation, the clock ɸ is 1 and the clocked
pMOS turns OFF.
• The output may remain high or may be discharged
low through the pull down network.
Footed and un-footed dynamic Logic:
Domino logic:
• Domino logic is a CMOS-based evolution of dynamic
logic techniques consisting of a dynamic logic gate cascaded
into a static CMOS inverter.
• Domino logic contrasts with other solutions to the cascade
problem where cascading is interrupted by clocks or other
means.
• Domino logic was developed to speed up circuits, solving the
premature cascade problem, typically by inserting static
CMOS inverters between domino stages to avoid premature
discharge of further cascaded dynamic logic gates.
• Domino logic allows a rail-to-rail logic swing, with the output
being able to switch from the power supply voltage to the
ground voltage.
Structure of Domino logic
• Consider the generalized circuit diagram of a
domino CMOS logic gate shown in Fig.
• A dynamic CMOS logic stage, such as the one
shown in Fig., is cascaded with a static CMOS
inverter stage.
• The addition of the inverter allows us to
operate a number of such structures in
cascade, as explained in the following.
Structure of Domino logic
• During the pre-charge phase (when CK = 0), the output
node of the dynamic CMOS stage is pre-charged to a high
logic level, and the output of the CMOS inverter (buffer)
becomes low.
• When the clock signal rises at the beginning of the
evaluation phase, there are two possibilities:
• The output node of the dynamic CMOS stage is either
discharged to a low level through the nMOS circuitry (1 to 0
transition), or it remains high.
• Consequently, the inverter output voltage can also make at
most one transition during the evaluation phase, from 0 to
1.
• Regardless of the input voltages applied to the dynamic
CMOS stage, it is not possible for the buffer output to make
a 1 to 0 transition during the evaluation phase.
Cascaded domino CMOS logic gates
• Complex logic gate, realized using
(a) conventional CMOS logic and
(b) domino CMOS logic.
• Domino CMOS logic gates allow a significant
reduction in the number of transistors required
to realize any complex Boolean function.
• The implementation of the 8-input Boolean
function, Z = AB + (C + D)(C + D) + GH, using
standard CMOS and domino CMOS, is shown in
Fig., where the reduction of circuit complexity is
obvious.
• The distribution of the clock signal within the
system is quite straightforward, since a single
clock can be used to pre-charge and evaluate any
number of cascaded stages, as long as the signal
propagation delay from the first stage to the last
stage does not exceed the time span of the
evaluation phase.
• Cascading domino CMOS logic gates with
static CMOS logic gates