Wideband Warfare receiver

An Internship Report (21EC76I)

Submitted by,
Pratham G 1RV21EC128

Under the guidance of

Deepika. P
Assistant Professor
Dept. of Electronics and Communication Engineering
RV College of Engineering

In partial fulfillment of the requirements for the degree of

Bachelor of Engineering in

Electronics and Communication Engineering

2024-25
 RV College of Engineering®, Bengaluru
(Autonomous institution affiliated to VTU, Belagavi )
Department of Electronics and Communication Engineering
.

CERTIFICATE
Certified that the Internship (21EC76I) work titled Wideband Warfare receiver is
carried out by Pratham G (1RV21EC128) who is bonafide student of RV Col-
lege of Engineering, Bengaluru, in partial fulfillment of the requirements for the degree
of Bachelor of Engineering in Electronics and Communication Engineering of
the Visvesvaraya Technological University, Belagavi during the year 2024-25. It is cer-
tified that all corrections/suggestions indicated for the Internal Assessment have been
incorporated in the internship report deposited in the departmental library. The intern-
ship report has been approved as it satisfies the academic requirements in respect of
internship work prescribed by the institution for the said degree.

Guide Head of the Department Principal

Deepika. P Dr. H V Ravish Aradhya Dr. K. N. Subramanya

External Viva

Name of Examiners Signature with Date

1.

2.
 DECLARATION

I, Pratham G students of seventh semester B.E., Department of Electronics and Com-

munication Engineering, RV College of Engineering, Bengaluru, hereby declare that the
internship titled ‘Wideband Warfare receiver’ has been carried out by me and sub-
mitted in partial fulfilment for the award of degree of Bachelor of Engineering in
Electronics and Communication Engineering during the year 2024-25.

Further I declare that the content of the dissertation has not been submitted previously
by anybody for the award of any degree or diploma to any other university.

I also declare that any Intellectual Property Rights generated out of this project carried
out at RVCE will be the property of RV College of Engineering, Bengaluru and we will
be one of the authors of the same.

Place: Bengaluru

Date:

Name Signature

1. Pratham G(1RV21EC128)
 ACKNOWLEDGEMENTS

I am indebted to my guide, Deepika. P, Assistant Professor, RV College of

Engineering . for the wholehearted support, suggestions and invaluable advice throughout
my project work and also helped in the preparation of this thesis.
I am greatly indebted to my external guide, Dr. N.Ramavenkateswaran, for
her expert guidance, professional insight and experience throughout the duration of my
internship. Without his support, this internship would not have taken place.
My gratitude to Prof. Narashimaraja P for the organized latex template which
made report writing easy and interesting. My sincere thanks to Dr. H V Ravish Arad-
hya, Professor and Head, Department of Electronics and Communication Engineering,
RVCE for the support and encouragement. I express sincere gratitude to our beloved
Principal, Dr. K. N. Subramanya for the appreciation towards this project work. I
thank all the teaching staff and technical staff of Electronics and Communication Engi-
neering department, RVCE for their help.

Lastly, I take this opportunity to thank my family members and friends who provided
all the backup support throughout the project work.
CERTIFICATE OF COMPLETION
 SYNOPSIS

The internship focused on understanding, designing, and optimizing an Electronic

Warfare (EW) Receiver as part of the Defence Research and Development Organisa-
tion’s (DRDO) initiatives to advance India’s defense technologies. Conducted within the
Electronics and Communication Systems (ECS) cluster, the internship provided an op-
portunity to explore state-of-the-art techniques in EW systems, emphasizing their role in
modern battlefield environments.
The primary objectives of the internship were to study the principles and operation of
electronic warfare systems, design receiver modules capable of wideband signal detection
and jamming, and optimize these systems for efficient hardware performance. Through
a systematic approach, the internship involved reviewing existing EW technologies, de-
veloping simulation models for receiver modules, and refining the system’s design using
High-Level Synthesis (HLS) tools to enhance performance and resource utilization.
Key tasks included the analysis of signal processing pipelines and the application of
advanced optimization techniques such as loop unrolling, pipelining, and dataflow meth-
ods. These techniques were instrumental in improving the speed, accuracy, and efficiency
of the EW receiver’s operations. The use of AMD Vitis™ HLS enabled the development of
scalable FPGA-based models that simulated real-world conditions, ensuring adaptability
across various platforms like aircraft, ships, and ground vehicles.
The outcomes of the internship were significant, including a deeper understanding
of electronic warfare principles, enhanced system performance metrics such as reduced
response times and improved throughput, and optimized hardware designs that effectively
addressed resource constraints. The project underscored the importance of wideband EW
receivers in ensuring the survivability and operational superiority of defense systems.
This experience not only strengthened technical skills in hardware design and high-
performance computing but also highlighted the critical role of innovation in electronic
warfare. By contributing to DRDO’s vision of achieving self-reliance in defense technolo-
gies, the internship laid a strong foundation for future work in the field of advanced EW
systems.

i
 CONTENTS

Synopsis i

List of Figures iv

List of Tables v

1 Profile of the Organisation 1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Defence Research Development Organisation . . . . . . . . . . . . . . . 2
1.2.1 Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Mission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Electronics and Communication Systems . . . . . . . . . . . . . . . . . . 3
1.3.1 Vision of ECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.2 Mission of ECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Activities of the Organisation 5

2.1 Research Laboratories . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 AJANTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 Air Defence Tactical Control Radar (ADTCR) . . . . . . . . . . . 7
2.2.3 Revathi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.4 D-29 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.5 Antenna Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Tasks Performed 10
3.1 Project Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Week-wise Tasks Performed . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Week 1: Literature Review and Theoretical Foundation . . . . . . 12
3.2.2 Week 2: Familiarization with Design Tools . . . . . . . . . . . . 12
3.2.3 Week 3: Design and Simulation of Low Noise Amplifier (LNA) . . 12
3.2.4 Week 4: Exploration of Signal Processing Techniques . . . . . . . 13
3.2.5 Week 5: System Integration and Multi-Channel Operation . . . . 13

ii
 3.2.6 Week 6: Performance Evaluation and Final Review . . . . . . . . 13
3.3 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Low Noise Amplifier Design in Verilog-A . . . . . . . . . . . . . . 15
3.3.2 Gilbert Cell Design for Frequency Mixer . . . . . . . . . . . . . . 19

4 Results and Analysis 23

4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.1 Key Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.2 Performance Metrics of LNA vs. gm /ID . . . . . . . . . . . . . . . 25
4.1.3 Schematic Component Details . . . . . . . . . . . . . . . . . . . . 27
4.1.4 Reflections on Methodology . . . . . . . . . . . . . . . . . . . . . 27

5 Reflections 29
5.1 Reflections on the Design Process . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Learning Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

iii
 LIST OF FIGURES

1.1 DRDO logo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 AJANTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 ADTCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Cascode LNA with Inductive Degeneration . . . . . . . . . . . . . . . . . 16

3.2 Behavioral modeling setup for LNA . . . . . . . . . . . . . . . . . . . . . 18
3.3 Gilbert Cell as Frequency Mixer schematic . . . . . . . . . . . . . . . . . 19

4.1 Perfomance metrics Of LNA-1 . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Performance metrics of LNA-2 . . . . . . . . . . . . . . . . . . . . . . . . 26

iv
 LIST OF TABLES

4.1 Performance Summary and Comparison with Related Work . . . . . . . . 24

4.2 Components Used for the LNA Schematic . . . . . . . . . . . . . . . . . 27

[sym]symbolListsym1sym2List of Symbols
AuxFiles/Glossaries

v
 RV College of Engineering® , Bengaluru - 560059

Chapter 1
Profile of the Organisation

UG Internship Report Department of ECE 2024-25

 RV College of Engineering® , Bengaluru - 560059

CHAPTER 1
PROFILE OF THE ORGANISATION
1.1 Introduction
The internship was carried out for a period of six weeks which was completed in
Electronics and Communication Systems (ECS). It is a Technology Cluster established
under the prestigious (DRDO), India. capabilities.The Vision, Mission, Objectives,
Outcomes and Benefits of the Organization are put forth in this chapter.

Figure 1.1: DRDO logo

1.2 Defence Research Development Organisation

The Defence Research and Development Organisation (DRDO) is an agency under
the Department of Defence Research and Development in Ministry of Defence of the Gov-
ernment of India, charged with the military’s research and development, headquartered
in Delhi, India. It is the RD wing of Ministry of Defence, Govt of India, with a vision
to empower India with cutting-edge defence technologies and a mission to achieve self-
reliance in critical defence technologies and systems, while equipping our armed forces
with state-of-the-art weapon systems and equipment in accordance with requirements
laid down by the three Services.
DRDO’s strategic objectives include reducing foreign dependency in defense equip-
ment, developing cost-effective indigenous technologies, and maintaining technological

UG Internship Report Department of ECE, 2024-25 2

 RV College of Engineering® , Bengaluru - 560059

superiority for India’s defense preparedness. Its research laboratories and centers con-
duct fundamental and applied research, prototype development, and technology transfer
to Indian defense manufacturing ecosystems.
Key achievements of DRDO include the development of the Tejas Light Combat Air-
craft, BrahMos supersonic cruise missile, advanced electronic warfare systems, and sig-
nificant contributions to India’s missile and space programs. The organization continues
to be a cornerstone of India’s technological self-reliance and defense innovation strategy.

1.2.1 Vision
The vision of DRDO is to empower the nation with state-of-the-art indigenous Defence
technologies and systems.

1.2.2 Mission
The mission of DRDO is as follows

• Design, develop and lead to production state-of-the-art sensors, weapon systems,

platforms and allied equipment for our Defence Services.

• Provide technological solutions to the Services to optimise combat effectiveness and

to promote well-being of the troops.

• Develop infrastructure and committed quality manpower and build strong indige-
nous technology base.

1.3 Electronics and Communication Systems

The ECS Cluster has a mandate to design and develop electronic, electro-optical and
laser based sensors and systems. The Cluster consists of laboratories DARE, DEAL,
DLRL, IRDE, LASTEC, LRDE and the Cognitive Technology Lab.
The cluster laboratories have developed state of art technologies in the fields of EW
Systems, Radars, Electro-optic Equipment, Laser Sources sensors, Directed Energy
Weapon Systems and Communication Systems used in various Flagship Programmes and
platforms of DRDO and ADA viz., Missile programmes, Unmanned Air Vehicles, Air-
borne Early Warning Control System, Aerostats, Main Battle Tank, Integrated Coastal
Surveillance System and Light Combat Aircraft etc. Apart from this, many of the systems
and sensors developed by the Cluster Labs are deployed and are being used by Indian
Armed forces and paramilitary services.

UG Internship Report Department of ECE, 2024-25 3

 RV College of Engineering® , Bengaluru - 560059

1.3.1 Vision of ECS

To become a Centre of Excellence in the field of EW, DEW, EO, Laser, Radar and
Communication Systems and related technologies.

1.3.2 Mission of ECS

Design, Development, Evaluation and ToT leading to Productionisation and Induction
of Advanced EW, DEW, EO, Laser, Radar and Communication Systems and to establish
self-reliance in these Critical Technologies.
This chapter highlighted the organisation’s importance and profile, the vision and
mission of the organisation and some of its achievements. The next chapter will focus on
the activities of the organisation. The chapter is organised as follows:

• Chapter 2 discusses the activities of the organisation.

• Chapter 3 enumerates the methodology and tasks performed during the internship.

• Chapter 4 reflects upon the the knowledge and experience gained during the course
of the internship with specific reference to the tasks carried out.

UG Internship Report Department of ECE, 2024-25 4

 RV College of Engineering® , Bengaluru - 560059

Chapter 2
Activities of the Organisation

UG Internship Report Department of ECE 2024-25

 RV College of Engineering® , Bengaluru - 560059

CHAPTER 2
ACTIVITIES OF THE ORGANISATION
This chapter discusses the activities of ECS, a technology cluster established under
DRDO. The cluster consists of several state-of-the-art laboratories, engaging in research
and development of cutting-edge technologies to advance India’s defence capabilities.

2.1 Research Laboratories

The cluster laboratories have developed state of art technologies in the fields of EW
Systems, Radars, Electro-optic Equipment, Laser Sources sensors, Directed Energy
Weapon Systems and Communication Systems used in various Flagship Programmes and
platforms of DRDO and ADA viz., Missile programmes, Unmanned Air Vehicles, Air-
borne Early Warning Control System, Aerostats, Main Battle Tank, Integrated Coastal
Surveillance System and Light Combat Aircraft etc. Apart from this, many of the sys-
tems and sensors developed by the Cluster Labs are deployed and are being used by
Indian Armed forces and paramilitary services. The different labs set-up under ECS are
as below.

1. Defence Electronics Application Laboratory (DEAL): Aims to develop Software

Based Radios, Anti-Jam Data Links, Secure Satcom Systems, Millimeter Wave
Communication Surveillance Systems.The lab has developed several military, surveil-
lance as well as communication products such as Combat Net Radio (CNR), Nishant
UAV, MM Wave Collision Avoidance Sensor for UGV.

2. Defence Electronics Research Laboratory (DLRL): The lab is working in the area of
electronic warfare (electronic intelligence, communications intelligence, radar and
communication jamming systems) systems covering the radar and communication
frequency bands on various types of platforms like vehicles, ships, submarines, he-
licopters, aircraft, airborne PODs and static installations. The laboratory is ISO
9001-2015 certified. Its products include AJANTA (a ship-borne electronic war-
fare system), COIN-A (a vehicle mounted Communication Intelligence (COMINT)
system developed for the Indian Air Force) amonf others.

3. DRDO Young Scientist Laboratory (DYSL-CT): The lab emphasises on Cognitive

technologies, works in the area of design and development of Cognitive Radio and

UG Internship Report Department of ECE, 2024-25 6

 RV College of Engineering® , Bengaluru - 560059

Cognitive Radar Systems, realising through Deep Neural Networks and Reinforce-
ment learning algorithms. DYSL (CT) lab was formed for providing cutting edge
technology to DRDO in the cognitive field. The lab is constituted of young sci-
entists to do extensive research and development in the cognitive radio, cognitive
radar, Smart antenna and cognitive Surveillance fields.

4. Electronics Radar Development Establishment (LRDE): LRDE was setup un-

der DRDO to address the Services’ needs in the field of Radars, Communication
Systems and related technologies. LRDE is a premier Radar Systems laboratory
with Core Competence and established expertise to build advanced Radar Systems,
which include short to long-range radars for ground based, ship borne and air borne
surveillance, tracking and weapon control.

5. Instruments Research Development Establishment (IRDE): The lab is is devoted to

research, design, development and technology transfer in optical and electro-optical
instrumentation primarily for the defence Services. Its aim is to achieve excellence in
the fields of Optics Electro-optical Instrumentation with a commitment to provide
high quality Instruments.

2.2 Products
This section emphasises on some of the cutting-edge products developed as a result
of committed effort and research of the labs in the ECS cluster under DRDO.

2.2.1 AJANTA
AJANTA is a shipborne Electronic Warfare (EW) system. The system is a single
operator, computer controlled Integrated Electronic Support Measure (ESM) Electronic
Counter Measures (ECM) system, designed for installation on frigates.The ESM system
covers wide frequency range and has capability to process both pulse and CW type of
emissions. The ECM system of Ajanta Operates in noise and deception jamming modes.
Twenty systems have been successfully inducted into the Navy since 1991. The product
is depicted in Figure 2.1

2.2.2 Air Defence Tactical Control Radar (ADTCR)

Air Defence Tactical Control Radar (ADTCR)is used for volumetric surveillance, de-
tection, tracking and friend/foe identification of aerial targets of different types, and

UG Internship Report Department of ECE, 2024-25 7

 RV College of Engineering® , Bengaluru - 560059

Figure 2.1: AJANTA

transmission of prioritised target data to multiple command posts/ weapon systems.

The radar is capable of detecting very small targets and low flying targets. The system
employs Active Phased Array Technology with Digital Beam Forming, distributed Dig-
ital Receivers and IFF Mark XII. The Radar System, power cooling systems, operator
shelter, communication equipment etc. is configured on two High Mobility Vehicles. The
Radar can be deployed in plain lands, deserts and in the mountain regions for the purpose
of tactical early warning for Ground based Weapon Systems. The ADTCR is shown in
Figure 2.2

2.2.3 Revathi
Revathi is a 3D Surveillance Radar for Indian Navy. It is a ship-borne Radar. The
radar has digital receiver, programmable signal processor providing high resolution, ac-
curacy, response and information availability. The radar can auto track upto 150 targets
including tracking with IFF (Mk XI) association. There are three Antenna Rotation
Rates (ARR) of 6, 12, 24 RPMs.

2.2.4 D-29 System

D-29 is an integrated EW system for Radar warning and jamming that encompasses
RWR, ECM, ESM functions and utilizes state-of-the-art active phased arrays for selec-

UG Internship Report Department of ECE, 2024-25 8

 RV College of Engineering® , Bengaluru - 560059

Figure 2.2: ADTCR

tively jamming the multiple threat radars. The D-29 system serves primarily as a self-
protection jammer that will boost survivability, enhance situation awareness and increase
mission effectiveness.
D-29 system detects and gives the information about the position of the RF sources
illuminating the aircraft and applies the appropriate jamming technique. The system
mainly consists of Unified Receiver Exciter Processor (UREP modified to suit the re-
quirements of D-29), Solid State Transmit / Receive Unit (SSTRU) with Active Array
Unit (AAU) and a liquid cooling system.

2.2.5 Antenna Systems

DRDO has developed the capability in designing antennas for various ground-based
and airborne radar systems, communication systems, electronic warfare, and underwater
scenarios.

This section discusses the activities of the organisation. The various research projects
and products developed by the organisation were also discussed in detail. The following
chapter lists and describes the tasks performed during the period of the internship.

UG Internship Report Department of ECE, 2024-25 9

 RV College of Engineering® , Bengaluru - 560059

Chapter 3
Tasks Performed

UG Internship Report Department of ECE 2024-25

 RV College of Engineering® , Bengaluru - 560059

CHAPTER 3
TASKS PERFORMED
This chapter outlines the tasks undertaken during the internship on the Electronic
Warfare (EW) Receiver, detailing the objectives, methodology, and weekly progression of
activities. The focus was on the design, simulation, and optimization of the EW receiver
to ensure robust functionality and adaptability across defense platforms.

3.1 Project Objectives

The primary objective of this project was to design, simulate, and validate key compo-
nents of an electronic warfare (EW) receiver subsystem capable of processing wideband
electromagnetic signals. The approach used to design the EW reciever was developed
with reference to the methods outlined by ghosh2023rf and rao2023ml. This high-
performance system was tailored for robust defense applications and was developed with
the following functionalities:

• Multi-Channel Operation:

– The receiver was designed to operate across four distinct frequency bands:

∗ Low-frequency (0.5–2.5 GHz)

∗ Mid-frequency (2–6 GHz)

∗ High-frequency (6–18 GHz)

∗ Ultra-high frequency (18–40 GHz)

– Dynamic channel switching capability based on detected signals.

• Signal Amplification: Amplification of weak signals using a Low Noise Amplifier

(LNA) to enhance signal strength while minimizing noise contribution.

• Frequency Down-Conversion: Conversion of high-frequency signals to Intermediate

Frequency (IF) using a mixer, simplifying further processing.

• Signal Filtering: Bandpass filters were employed to isolate desired signals, removing
out-of-band interference and noise.

• Analog-to-Digital Conversion (ADC): Digitization of IF signals for real-time pro-

cessing, including frequency domain analysis and radar pattern recognition

UG Internship Report Department of ECE, 2024-25 11

 RV College of Engineering® , Bengaluru - 560059

3.2 Week-wise Tasks Performed

This section discusses the tasks performed in the week during the internship.

3.2.1 Week 1: Literature Review and Theoretical Foundation

• Conducted a detailed literature survey on electronic warfare (EW) concepts, fo-
cusing on RF receivers, wideband communication systems, and signal processing
techniques.

• Studied multi-channel receiver designs and their operation across diverse frequency
bands.

• Gained foundational knowledge about critical RF subsystems like Low Noise Ampli-
fiers (LNA), mixers, bandpass filters, and analog-to-digital converters (ADC). Back-
ground information on the topic was primarily referenced from watanabe2024rf
and miller2023sdr

3.2.2 Week 2: Familiarization with Design Tools

• Acquired hands-on experience with Cadence design software, including schematic
creation and simulation workflows.

• Learned to utilize Process Design Kits (PDKs) for RF subsystem design using 65nm
transistor models.

• Simulated basic RF circuit components to understand their behavior and verify

compatibility with the project requirements.

3.2.3 Week 3: Design and Simulation of Low Noise Amplifier

(LNA)
• Designed an LNA using a cascode configuration with inductive degeneration for
optimal gain and noise performance.

• Implemented key equations and parameters in Verilog-A for accurate modeling of

the 65nm transistor characteristics.

• Conducted simulations in Cadence Spectre to evaluate the LNA’s performance un-

der varying conditions, achieving a high gain ( 15 dB) with a low noise figure ( 2
dB).

UG Internship Report Department of ECE, 2024-25 12

 RV College of Engineering® , Bengaluru - 560059

3.2.4 Week 4: Exploration of Signal Processing Techniques

• Focused on designing the signal down-conversion stage using a Gilbert cell mixer
for frequency translation. Background information on the topic was primarily ref-
erenced from gupta2023adaptive and patel2024ai.

• Simulated the mixer in Cadence, analyzing its conversion gain and linearity for
wideband RF signals.

• Ensured effective frequency down-conversion while maintaining system-level signal

integrity and minimizing nonlinearities.

3.2.5 Week 5: System Integration and Multi-Channel Opera-

tion
• Integrated the LNA and mixer subsystems to create a functional RF front-end for
multi-channel operation.

• Designed and simulated bandpass filters to isolate desired signals and remove noise
or out-of-band interference.

• Incorporated an ADC module to digitize intermediate frequency signals for further

processing, enabling real-time signal analysis. Background information on ADC
design was primarily referenced from b2009 and reddy2020.

3.2.6 Week 6: Performance Evaluation and Final Review

• Conducted a comprehensive system-level analysis to validate the integrated receiver
design across all target frequency bands.

• Evaluated key metrics such as gain, noise figure, linearity, and signal fidelity to
ensure compliance with the project objectives. The approach used to analyze these
parameters was developed with reference to the methods outlined by micr2019

• Prepared the final report documenting design methodologies, results, and recom-
mendations for future work, including potential improvements in ADC and digital
signal processing modules.

UG Internship Report Department of ECE, 2024-25 13

 RV College of Engineering® , Bengaluru - 560059

3.3 Methodology
The methodology for designing and validating the electronic warfare (EW) receiver
subsystem in the Cadence Spectre environment followed a systematic and structured ap-
proach. The process began with the configuration of the Cadence Spectre tool, including
the installation of the required Process Design Kits (PDKs) for 65nm CMOS technol-
ogy. Simulation libraries for Verilog-A modeling and schematic simulations were set up
to enable the accurate design and analysis of circuit components. The approach used
to propose the architecture of the reciever was developed with reference to the methods
outlined by singh2024fpga.
Individual subsystems, such as the Low Noise Amplifier (LNA) and the Gilbert cell
mixer, were designed using schematic entry in Cadence. The approach used in the LNA
design was developed with reference to the methods outlined by david2019. The LNA
employed a cascode configuration with inductive degeneration to achieve high gain and
low noise performance. The Gilbert cell mixer was developed to enable effective frequency
down-conversion, focusing on achieving stable conversion gain and maintaining linearity.
The approach used to analyze gilbert cell parameters was developed with reference to
the methods outlined by turn0search1. Key design parameters, such as fT (transit
frequency), gm /ID (transconductance efficiency), and Cgs (gate-source capacitance), were
extracted from the PDKs and modeled using Verilog-A functions to ensure accurate
simulation results.
Once the subsystems were designed, DC, AC, and transient simulations were per-
formed to validate their functionality across the target frequency bands. For the LNA,
simulations focused on achieving a gain of approximately 15 dB and a noise figure of
around 2 dB. The approach used to analyze LNA parameters was developed with ref-
erence to the methods outlined by turn0academia11 The Gilbert cell mixer was sim-
ulated to evaluate its conversion gain, linearity, and spurious signal rejection, ensuring
optimal signal processing performance. The approach used to design the gilbert cell was
developed with reference to the methods outlined by turn0search5.These simulations
provided insights into the performance of individual components and guided necessary
refinements.
The next phase involved integrating the LNA and mixer subsystems into a unified
receiver schematic. This integrated design included bandpass filters to isolate desired

UG Internship Report Department of ECE, 2024-25 14

 RV College of Engineering® , Bengaluru - 560059

signals and remove out-of-band interference, as well as ADC modules to digitize inter-
mediate frequency signals for further processing. The approach used to design Bandpass
filter was developed with reference to the methods outlined by turn0search6. The inte-
grated receiver was simulated to ensure proper multi-channel operation across the entire
target frequency range (0.5–40 GHz), with a focus on maintaining signal fidelity and
minimal distortion.
Finally, a comprehensive performance analysis was conducted on the integrated sys-
tem. Metrics such as gain stability, noise figure, conversion gain, and signal-to-noise ratio
(SNR) were evaluated to ensure the receiver met the required performance benchmarks.
Transient and AC simulations were used to analyze time-domain behavior and frequency
response, respectively. The results were documented, and areas for further optimization,
such as improving ADC performance for enhanced digital signal processing, were iden-
tified. The approach used in this report was developed with reference to the methods
outlined by zhang2024high.
This detailed and iterative execution in the Cadence Spectre environment ensured the
development of a robust and efficient EW receiver subsystem, optimized for wideband
operation and advanced defense applications. The process provided valuable insights
into designing high-performance RF systems while maintaining a focus on practical and
scalable solutions.

3.3.1 Low Noise Amplifier Design in Verilog-A

The Low Noise Amplifier (LNA) was designed using a top-down methodology, leverag-
ing Verilog-A for modeling and Cadence Spectre for circuit simulation. The design process
ensured accurate representation of the circuit’s analog behavior and seamless integration
into the simulation environment. The approach used in this report was developed with
reference to the methods outlined by Sajjad2018.

Overview of the LNA Schematic

The schematic for the LNA, as shown in Figure 3.1 the from the paper, employs a
cascode topology with inductive degeneration. This schematic was recreated in
Verilog-A by modeling its key performance equations for gain, noise, and linearity. The
Verilog-A model aimed to replicate the functionality of this circuit to allow for early-stage
performance analysis and parameter tuning.

UG Internship Report Department of ECE, 2024-25 15

 RV College of Engineering® , Bengaluru - 560059

Figure 3.1: Cascode LNA with Inductive Degeneration

Why Use Inductive Degeneration?

The LNA design leverages inductive degeneration in the source of the input transistor
for the following advantages:

• Input Impedance Matching: The degeneration inductor increases the input

impedance, facilitating better matching to the 50Ω source impedance.

• Improved Linearity: Degeneration enhances linearity by stabilizing the input

transistor’s transconductance over a range of operating conditions.

• Noise Reduction: The source inductor contributes minimally to thermal noise

while effectively boosting linearity, leading to a lower overall noise figure.

Verilog-A Implementation
The LNA was modeled in Verilog-A to represent its key performance characteristics,
such as voltage gain (AV ), noise figure (NF), and input third-order intercept point (IIP3).
The approach used to design LNA using Verilog-A was developed with reference to the
methods outlined by topdown. These metrics were expressed through equations derived
from the LNA topology:

UG Internship Report Department of ECE, 2024-25 16

 RV College of Engineering® , Bengaluru - 560059

Voltage Gain (AV ): The voltage gain was expressed as:

fT Q2
AV = · Rin · LD (3.1)
f0 RLD

where fT is the transit frequency of the transistor, f0 is the operating frequency, and QLD
and RLD are the quality factor and series resistance of the load inductor.

Noise Figure (NF): The noise figure was modeled using:

2
 
8kT γgm Rin
N F = 10 · log10 1 + (3.2)
fT2

where k is Boltzmann’s constant, T is the temperature, γ is the transistor noise coefficient,

and gm is the transconductance.

Linearity (IIP3): The IIP3 metric was calculated using:

2
 
14 gm
IIP 3 = 10 · log10 · (3.3)
3 W · Cgs

where W is the transistor width, and Cgs is the gate-source capacitance.

The Verilog-A implementation encoded these equations into an analog behavioral
model. For instance:

analog begin
gm = gm_id * W / L; // Transconductance
gain = (f_T / f_T) * R_in * Q_LD^2 / R_parallel; // Voltage gain
noise_figure = 10 * $log10(1 + (8 * kT * gm * R_in^2)); // NF
iip3 = 10 * $log10((14 / 3) * gm * gm / (W * C_gs)); // IIP3
V(v_out) <+ gain * V(v_in); // Output signal
end

Transistor Characterization
To accurately represent the circuit behavior, transistor characteristics were extracted
from the 65nm process design kit (PDK). The following parameters were obtained:

• Width (W ): Set to 41 µm to optimize gain and linearity.

UG Internship Report Department of ECE, 2024-25 17

 RV College of Engineering® , Bengaluru - 560059

• Length (L): Fixed at 0.06 µm for high-speed operation.

• Gate-Source Capacitance (Cgs ): Used to calculate fT and linearity metrics.

• Transconductance (gm ): Derived using the gm /ID methodology to balance power,

gain, and noise.

These parameters were ported into the Verilog-A model, enabling the model to sim-
ulate real-world transistor behavior.

Integration into Cadence Spectre

The Verilog-A module was imported into the Cadence Spectre simulation environment
as a behavioral block. This allowed seamless integration with schematic-level components,
such as inductors, capacitors, and resistors, modeled in Spectre. The steps were as follows:

• The Verilog-A file was compiled and linked to the Spectre environment asn show in
Fig 3.2

• Transistor characteristics were tuned directly in the Verilog-A code to match PDK
specifications.

• Schematic-level passive components were added for load inductors, source degener-
ation inductors, and coupling capacitors.

The combined setup enabled accurate simulations of the LNA’s performance metrics,
including gain, noise figure, and linearity, in a single environment.

Figure 3.2: Behavioral modeling setup for LNA

UG Internship Report Department of ECE, 2024-25 18

 RV College of Engineering® , Bengaluru - 560059

3.3.2 Gilbert Cell Design for Frequency Mixer

The Gilbert cell was designed to function as a frequency mixer in the wideband elec-
tronic warfare receiver. This topology was chosen for its high conversion gain, excellent
linearity, and inherent ability to suppress unwanted harmonics. Background information
on the topic was primarily referenced from turn0search2. The design process leveraged
both behavioral modeling and schematic-level simulation to ensure performance across a
wide frequency range.

Figure 3.3: Gilbert Cell as Frequency Mixer schematic

Overview of the Gilbert Cell Mixer

The Gilbert cell is a double-balanced mixer comprising:

• Transconductance Stage: Converts the input RF voltage signal into a current

signal.

• Switching Core: A differential pair that multiplies the RF signal with the Local
Oscillator (LO) signal, producing the sum and difference frequencies.

• Load Stage: Provides the mixed output signal and sets the output impedance.

The Gilbert cell schematic is as shown in the Fig 3.3 and the configuration inherently
cancels even-order harmonics, making it well-suited for wideband applications.

UG Internship Report Department of ECE, 2024-25 19

 RV College of Engineering® , Bengaluru - 560059

Why Gilbert Cell Mixers?

Gilbert cell mixers are preferred for wideband applications due to:

• High Conversion Gain: Ensures strong signal output even with low input power
levels.

• Linearity: Provides excellent linearity and suppresses even-order harmonics effec-

tively.

• Wideband Operation: Performs well across a wide range of frequencies, making

it ideal for electronic warfare receivers.

Design Equations for the Mixer

Conversion Gain: The conversion gain is given by:

IRF
Gc = · RL (3.4)
ILO

where:

• IRF : Input RF current.

• ILO : Input LO current.

• RL : Load resistance.

Linearity (IIP3): The linearity of the mixer is defined as:

 
4 gm
IIP 3 = 10 · log10 · (3.5)
3 W · Cgs

where gm is the transconductance of the input transistors, W is the transistor width, and
Cgs is the gate-source capacitance.

Noise Figure (NF): The noise figure is expressed as:

 
kT γ
N F = 10 · log10 1+ + (3.6)
RL gm

where γ is the noise coefficient of the transistors, and RL is the load resistance.

UG Internship Report Department of ECE, 2024-25 20

 RV College of Engineering® , Bengaluru - 560059

Transistor-Level Design
The Gilbert cell mixer was implemented with the following design considerations:

• Input Transistors:

– Width (W ): 20 µm for high-speed operation.

– Length (L): 65 nm to match the PDK technology node.

– Bias current optimized to ensure a high gm /ID ratio.

• Switching Core:

– Matched transistors for differential switching to suppress even-order harmon-

ics.

– Symmetry ensured to maintain balance in the differential operation.

• Load Stage:

– Load resistance (RL ): 500 Ω to set the output impedance and maintain a high
conversion gain.

– Coupling capacitors added for RF isolation.

Integration into Cadence Spectre

The Gilbert cell was modeled in Verilog-A to simulate its functional behavior and
later implemented at the transistor level in Cadence Spectre for verification. The design
process involved:

• Porting transistor characteristics from the 65 nm PDK to define gm , W , and L.

• Behavioral modeling of the switching core to validate the differential operation.

• Integration with passive components for the load stage and input/output matching
networks.

Applications in Wideband Receivers

The Gilbert cell mixer plays a critical role in the wideband electronic warfare receiver
by down-converting RF signals to an intermediate frequency (IF). Its wide frequency
range and high linearity ensure robust performance in detecting and processing signals
in complex RF environments.

UG Internship Report Department of ECE, 2024-25 21

 RV College of Engineering® , Bengaluru - 560059

This chapter focused on the tasks that were performed during the course of the 4
weeks of the internship, and also a detailed explanation regarding the project that was
carried out during the period of the internship.
The next chapter will be dedicated to the results obtained from the project and their
detailed analysis.

UG Internship Report Department of ECE, 2024-25 22

 RV College of Engineering® , Bengaluru - 560059

Chapter 4
Results and Analysis

UG Internship Report Department of ECE 2024-25

 RV College of Engineering® , Bengaluru - 560059

CHAPTER 4
RESULTS AND ANALYSIS
This chapter will provide a detailed overview of the final results obtained in the
internship.
The design and implementation of the Low Noise Amplifier (LNA) were validated
through simulations in the Cadence Spectre environment. This section discusses the
results, provides a comparison with related work, and reflects on the design methodology.

4.1 Simulation Results

The performance metrics of the LNA, derived from both the Verilog-A model and
schematic simulations, are summarized in Table 4.1. The results demonstrate strong
alignment with the target specifications and closely match those of the model.

Table 4.1: Performance Summary and Comparison with Related Work

Specs Model Schematic [4] [5]

Process 65nm 65nm 65nm 90nm
AV (dB) 18 18.56 22 12.4
NF (dB) 0.9 0.94 3.2 3.66
IIP3 (dBm) -5.7 -8.01 -5.7 1.24
Power (mW) 3.57 3.71 0.56 1.44

4.1.1 Key Observations

• Voltage Gain (AV ): The gain achieved in the schematic simulation (18.56 dB)
exceeds the target (18 dB) and is close to the model predictions.

• Noise Figure (NF): The noise figure (0.94 dB) is significantly lower than compa-
rable designs in [4] and [5], showcasing the effectiveness of the chosen topology and
design methodology.

• Linearity (IIP3): The schematic simulation achieved an IIP3 of -8.01 dBm,

slightly below the target. This deviation is attributed to non-linear effects and
parasitics not fully captured in the Verilog-A model.

• Power Consumption: The power consumption (3.71 mW) aligns well with the
model predictions and demonstrates the efficiency of the design.

UG Internship Report Department of ECE, 2024-25 24

 RV College of Engineering® , Bengaluru - 560059

4.1.2 Performance Metrics of LNA vs. gm /ID

The plots in Fig ?? illustrate the trade-offs between the key performance metrics of the
LNA—voltage gain (AV ), noise figure (NF), IIP3 (linearity), and power consumption—as
a function of the transconductance-to-current ratio (gm /ID ) of the input transistor (M0 ).
Two design implementations were compared to analyze the performance trends.

Figure 4.1: Perfomance metrics Of LNA-1

Voltage Gain and Noise Figure Analysis

• Voltage Gain (AV ): - As shown in the left plot of Fig 4.2, the voltage gain in-
creases at lower values of gm /ID . This trend is attributed to the improved transcon-
ductance efficiency of the transistor in weak inversion or moderate inversion regions.
- Beyond a certain point, the gain decreases as gm /ID increases due to the higher
gate-source capacitance (Cgs ) and reduced gm efficiency.

• Noise Figure (NF): - The noise figure decreases as gm /ID is reduced. This behav-
ior is due to the reduction in the transistor’s intrinsic noise contribution. - However,
extremely low gm /ID values lead to diminished linearity and reduced overall per-
formance.

• Observation: - For an optimal trade-off, a gm /ID value in the range of 6–8 provides

UG Internship Report Department of ECE, 2024-25 25

 RV College of Engineering® , Bengaluru - 560059

Figure 4.2: Performance metrics of LNA-2

both high gain and a low noise figure, as indicated by the intersection of the curves
in the figure.

IIP3 and Power Consumption Analysis

• IIP3 (Input Third-Order Intercept Point): - The right plot of Fig. 3 demon-
strates that the IIP3 improves with increasing gm /ID . Higher gm /ID results in
improved linearity due to reduced non-linear distortion effects. - This improvement
in IIP3 comes at the cost of higher power consumption.

• Power Consumption: - Power consumption increases almost exponentially as

gm /ID increases. This behavior occurs due to the higher bias currents required to
operate in strong inversion.

• Observation: - A balance must be struck between linearity and power consump-

tion. For moderate power consumption and acceptable linearity, a gm /ID value
around 7–8 offers a reasonable compromise.

Insights from the Plots

The plots in Fig. 3 provide critical insights into the performance trade-offs:

UG Internship Report Department of ECE, 2024-25 26

 RV College of Engineering® , Bengaluru - 560059

• High Gain and Low Noise: Achieved at lower gm /ID values but with reduced
linearity.

• Improved Linearity: Requires higher gm /ID , which increases power consumption.

• Optimal gm /ID Region: A range of gm /ID ∼ 7 − 8 provides an optimal trade-off

between gain, noise figure, linearity, and power consumption.

This analysis highlights the importance of selecting an appropriate gm /ID ratio during
transistor biasing and sizing to achieve the desired LNA performance.

4.1.3 Schematic Component Details

The components used in the schematic simulation are listed in Table 4.2. These
components were critical in achieving the performance metrics and were designed based
on extracted transistor characteristics.

Table 4.2: Components Used for the LNA Schematic

Component Width (W) Length (L) Remarks
M0, M1 41 µm 0.06 µm 5 fingers, NMOS
M2 3.75 µm 0.06 µm 1 finger, NMOS
R0 3 µm 5 µm 1.2 kΩ, unsliced P+ poly
R1 3 µm 4.5 µm 1 kΩ, unsliced P+ poly
CD, Cblock 222 x 187 - 4 pF, MOM, placed in parallel for 16 pF
Cext 40 x 44 - 172 fF, MOM
LD 54 µm 609 µm 271 pH, Q = 13, octagonal PGS
LS 22 µm 623 µm 418 pH, Q = 7, octagonal PGS
LG 13 µm 748 µm 0.6 nH, Q = 12, octagonal PGS, external series Lof f −chip = 20 nH

4.1.4 Reflections on Methodology

Strengths of the Approach
• Early Trade-Off Analysis: Verilog-A modeling enabled rapid exploration of the
performance trade-offs, providing insights into gain, noise, and power optimization.

• Accurate Parameter Porting: The 65 nm PDK parameters ensured consistency

between behavioral and schematic-level simulations.

• Comprehensive Design Flow: The integration of Verilog-A with Spectre simu-

lations reduced the design cycle by enabling simultaneous optimization and valida-
tion.

UG Internship Report Department of ECE, 2024-25 27

 RV College of Engineering® , Bengaluru - 560059

Challenges Encountered
• Parasitic Effects: Unmodeled parasitics in Verilog-A impacted schematic-level
IIP3 performance.

• Layout Dependencies: Post-layout parasitic extraction could improve accuracy

but was not included in this phase.

Potential Improvements
• Incorporate layout-aware parasitic extraction earlier in the design flow.

• Extend Verilog-A modeling to include second-order non-linearities for more accurate

predictions.

UG Internship Report Department of ECE, 2024-25 28

 RV College of Engineering® , Bengaluru - 560059

Chapter 5
Reflections

UG Internship Report Department of ECE 2024-25

 RV College of Engineering® , Bengaluru - 560059

CHAPTER 5
REFLECTIONS
5.1 Reflections on the Design Process
The design and simulation of the Low Noise Amplifier (LNA) provided a compre-
hensive understanding of high-frequency analog circuit design and the importance of a
systematic methodology. A top-down design approach was adopted to streamline the
design process and ensure efficiency. This began with a behavioral model implemented
in Verilog-A, where key performance metrics such as gain, noise figure, and IIP3 were
expressed using analytical equations. The Verilog-A model allowed for rapid iterations
and quick trade-off analysis without resorting to time-consuming transistor-level simu-
lations. Once an optimal behavioral design was achieved, transistor parameters such as
transconductance-to-current ratio (gm /ID ), gate-source capacitance (Cgs ), and parasitics
were extracted from the 65 nm PDK and integrated into the model. This transition from
behavioral modeling to transistor-level simulations ensured that the design accounted for
realistic process characteristics.
One of the critical steps in the design process was optimizing the transistor biasing
using gm /ID analysis. This method provided an intuitive understanding of how gain,
noise, and linearity behaved under different transistor bias conditions. At lower gm /ID
values, the voltage gain and noise figure showed significant improvement due to enhanced
transconductance efficiency. However, increasing gm /ID to achieve better linearity re-
sulted in higher power consumption and reduced gain. This analysis revealed that a
gm /ID value in the range of 7–8 offered an optimal trade-off between performance met-
rics, balancing high gain, low noise, and acceptable linearity with manageable power con-
sumption. Additionally, schematic simulations introduced real-world complexities, such
as parasitic effects in inductors and non-ideal behavior of capacitors, which caused slight
deviations from the behavioral model. These challenges underscored the importance of
refining the schematic design iteratively to address non-linearities and losses.
The process of achieving input impedance matching using inductive source degenera-
tion presented another significant challenge. The source inductor (LS ) and gate inductor
(LG ) values required careful tuning to minimize reflection losses while maintaining lin-
earity and noise performance. Simulations at the operating frequency of 2.4 GHz demon-

UG Internship Report Department of ECE, 2024-25 30

 RV College of Engineering® , Bengaluru - 560059

strated the sensitivity of the design to parasitic capacitances and resistances, emphasiz-
ing the importance of careful component optimization. Overall, the iterative refinement
process—starting from behavioral modeling, integrating realistic PDK parameters, and
validating through schematic simulations—proved to be both challenging and enlighten-
ing. It reinforced the need for a systematic design flow and the importance of addressing
parasitic effects early in the design process.

5.2 Learning Outcomes

The design and analysis of the LNA resulted in several key learning outcomes. From a
technical perspective, the use of Verilog-A for behavioral modeling provided a significant
advantage in early-stage design. By implementing equations for gain, noise figure, and
IIP3, the Verilog-A model allowed for rapid performance analysis and design trade-offs
without resorting to full schematic simulations. This methodology highlighted the impor-
tance of abstracting circuit behavior to guide subsequent transistor-level implementation.
The gm /ID methodology emerged as a powerful tool for optimizing transistor biasing, pro-
viding a clear understanding of the trade-offs between gain, noise, and linearity. Through
this analysis, it was observed that transistor biasing plays a pivotal role in achieving the
desired performance, and the selection of gm /ID impacts all major performance metrics.
The design process also emphasized the impact of parasitic effects on high-frequency
analog circuits. Parasitics in inductors, resistors, and transistors introduced non-idealities
that affected gain, IIP3, and input/output matching. Accounting for these effects in
schematic simulations proved critical for ensuring accurate performance predictions. The
use of inductive source degeneration demonstrated its effectiveness in achieving input
impedance matching while simultaneously improving the amplifier’s linearity with min-
imal noise degradation. Furthermore, the design process reinforced the importance of
iterative refinements, where discrepancies between behavioral and schematic results were
systematically addressed to achieve the target performance.
From a methodological perspective, the top-down design approach provided a clear
and efficient workflow. Starting with a behavioral model and transitioning to schematic-
level design allowed for early identification of trade-offs and bottlenecks, minimizing the
need for excessive iterations at the transistor level. The integration of 65 nm PDK param-
eters ensured that the final design accounted for realistic transistor behavior, enabling
accurate simulations and validations. Additionally, the iterative refinement process high-

UG Internship Report Department of ECE, 2024-25 31

 RV College of Engineering® , Bengaluru - 560059

lighted the importance of balancing theoretical analysis with practical implementation to

address real-world design challenges.

5.3 Conclusion
In this work, a Low Noise Amplifier (LNA) was designed and simulated for a wideband
electronic warfare receiver operating at 2.4 GHz. The design achieved significant success
in meeting the target performance specifications while addressing the inherent challenges
of RF analog circuit design. Using a top-down methodology, the LNA design began with a
behavioral model in Verilog-A, where performance metrics such as gain, noise figure, and
linearity were analyzed and optimized. This model provided a foundation for subsequent
transistor-level simulations in Cadence Spectre. By leveraging the gm /ID methodology,
the transistor biasing was optimized to balance gain, noise figure, and power consumption.
The final design achieved a voltage gain of 18.56 dB, a noise figure of 0.94 dB, an IIP3
of -8.01 dBm, and a power consumption of 3.79 mW.
The performance analysis versus gm /ID revealed that a gm /ID value around 7–8 pro-
vided the optimal trade-off between high gain, low noise, and acceptable linearity. Ad-
ditionally, inductive degeneration proved effective for input impedance matching while
enhancing linearity with minimal degradation in noise figure. Despite challenges such
as parasitic effects and non-ideal component behavior, iterative refinements ensured that
the design closely matched the target specifications.
Overall, the design demonstrates the effectiveness of a systematic design flow that
combines behavioral modeling, realistic transistor characterization, and schematic-level
validation. The insights gained from this work lay a strong foundation for designing
high-performance RF front-end circuits for wideband communication systems.

5.4 Future Work

While the LNA design achieved its performance goals, several opportunities for further
improvements and extensions remain. Post-layout simulations incorporating parasitic
extraction are essential to evaluate the design’s performance after fabrication. This step
will provide insights into layout-dependent effects and ensure performance consistency.
A natural next step would be to proceed with the fabrication and measurement of the
LNA to validate its real-world performance through experimental testing. Additionally,
the LNA can be integrated with other blocks such as mixers, filters, and oscillators to

UG Internship Report Department of ECE, 2024-25 32

 RV College of Engineering® , Bengaluru - 560059

realize a complete wideband RF front-end for electronic warfare receivers.

Future work could also explore advanced LNA topologies such as differential ampli-
fiers, noise-canceling architectures, and feedback-based designs to further improve noise
performance, gain, and linearity. Optimizing the design for ultra-low power applications
without compromising performance will also be an important area of focus. Overall,
the insights and methodologies developed in this work provide a strong basis for future
research and development in high-performance RF circuits.

UG Internship Report Department of ECE, 2024-25 33