Output Stages and Power Amplifiers (Chapter 12)

12.5 Biasing the Class AB Circuit

12.5.1 Biasing Using Diodes
Fig. shows a class AB circuit in which the bias
voltage VBB is generated by passing a constant
current IBIAS through a pair of diodes, or diode-
connected transistors, D1 and D2.
the quiescent current IQ established in QN and QP
will be IQ = nIBIAS, where n is the ratio of the
emitter–junction area of the output devices to the
junction area of the biasing diodes.
i.e. the saturation (or scale) current IS of the output
transistors is n times that of the biasing diodes.
Example 12.4
Consider the class AB output stage under the conditions that VCC = 15 V, RL = 100 Ω, and the
output is sinusoidal with a maximum amplitude of 10 V. Let QN and QP be matched with
IS = 10−13 A and β = 50.
Assume that the biasing diodes have one-third the junction area of the output devices.
1. Find the value of IBIAS that guarantees a minimum of 1 mA through the diodes at all times.
2. Determine the quiescent current and the quiescent power dissipation in the output transistors
(i.e., at vO = 0). Also
3. find VBB for vO = 0, +10 V, and −10 V.
Solution
1. The maximum current through QN is approximately equal to
iLmax = vo / RL = 10 V/0.1 kΩ = 100 mA.
IBASEMAX = iLmax / (𝛽 + 1) ≈ 2 𝑚𝐴 in QN
Then IBIAS = IBASEMAX + ID = 2 mA + 1 mA = 3 mA.
2. The area ratio of 3 yields a quiescent current of 9 mA through QN and QP.
The quiescent power dissipation is
3. For vO = 0, the base current of QN is 9/51 ≈ 0.18 mA, leaving a current of 3 − 0.18 = 2.82 mA
to flow through the diodes. Since the diodes have
1
𝐼𝑆 = × 10−13 𝐴 ,
3

the voltage VBB will be

At vO = +10 V, the current through the diodes will decrease to 1 mA, resulting in VBB ≈ 1.21 V.
At the other extreme of vO = −10 V, QN will be conducting a very small current; thus its base
current will be negligibly small and all of IBIAS (3 mA) flows through the diodes, resulting in
VBB ≈ 1.26 V.

12.5.2 Biasing Using the VBE Multiplier: is more flexibility in both discrete and integrated
designs.
The bias circuit consists of transistor Q1 with a resistor R1 connected between base and emitter
and a feedback resistor R2 connected between collector and base.
The resulting two-terminal network is fed with a constant-current source IBIAS. If we neglect the
base current of Q1, then R1 and R2 will carry the same current IR, given by
IR = VBE1 / R1
VBB = IR(R1+R2)
𝑉𝐵𝐸1 𝑅2
𝑉𝐵𝐵 = (𝑅1 + 𝑅2 ) = 𝑉𝐵𝐸1 (1 + )
𝑅1 𝑅1
Thus, the circuit multiplies VBE1 by the factor
(1+R2/R1) and is known as the VBE multiplier.
Find VBE1:
Example 12.5
Consider the class AB output stage under the conditions that VCC = 15 V, RL = 100 Ω, and the
output is sinusoidal with a maximum amplitude of 10 V. Let QN and QP be matched with
IS = 10−13 A and β = 50. the value of IBIAS that guarantees a minimum of 1 mA.
It is required to redesign the output stage utilizing a VBE multiplier for biasing. Use a small-
geometry for Q1 with IS = 10−14 A and design for a quiescent current IQ = 2 mA.
Solution
1. The maximum current through QN is approximately equal to
iLmax = vo / RL = 10 V/0.1 kΩ = 100 mA.
IBASEMAX = iLmax / (𝛽 + 1) ≈ 2 𝑚𝐴 in QN
Then IBIAS = IBASEMAX + ID = 2 mA + 1 mA = 3 mA.
thus providing the multiplier with a minimum current of 1 mA. Under quiescent conditions (vO =
0 and iL = 0) the base current of QN can be neglected and all of IBIAS flows through the multiplier.
We now must decide on how this current (3 mA) is to be divided between IC1 and IR. If we select
IR greater than 1 mA, the transistor will be almost cut off at the positive peak of vO.
Therefore, we shall select IR = 0.5 mA, leaving 2.5 mA for IC1.
To obtain a quiescent current of 2 mA in the output transistors, VBB should be
Ex 12.8. Consider a VBE multiplier with R1= R2 =1.2 k Ω, utilizing a transistor that has VBE
= 0.6 Vat IC = 1 mA, and a very high β.
(a) Find the value of the current I that should be supplied to the multiplier to obtain a terminal
voltage of 1.2 V.
(b) Find the value of I that will result in the terminal voltage changing (from the 1.2-V value) by
+50 mV, +100 mV, +200 mV, –50 mV, –100 mV, –200 mV.
Sol. a. Since a terminal voltage 𝑉𝐵𝐵 = 1.2 𝑉 and
since β is very large. Then
𝑉𝑅1 = 𝑉𝑅2 = 0.6 𝑉 thus
𝐼𝐶1 = 1 𝑚𝐴
𝑉𝐵𝐵 = 𝐼𝑅 (𝑅1 + 𝑅2 )
𝑉𝐵𝐵 1.2
𝐼𝑅 = = = 0.5 𝑚𝐴
𝑅1 + 𝑅2 2.4 𝑘
𝐼𝐵𝑖𝑎𝑠 = 𝐼𝑅 + 𝐼𝑐 = 0.5 𝑚 + 1 𝑚 = 1.5 𝑚𝐴
b.
i. ∆𝑉𝐵𝐵 = +50 𝑚𝑉
𝑉𝐵𝐵 = 1.2 + 0.05 = 1.25 𝑉
𝑉𝐵𝐵 1.25
𝐼𝑅 = = = 0.52 𝑚𝐴
𝑅1 + 𝑅2 2.4 𝑘
1.25
𝑉𝐵𝐸 = = 0.625 𝑉
2
𝑉𝐵𝐸1
𝐼𝑐1 = 𝐼𝑠 𝑒 𝑉𝑇
𝑉𝐵𝐸2
𝐼𝑐2 = 𝐼𝑠 𝑒 𝑉𝑇
𝑉𝐵𝐸2−𝑉𝐵𝐸1 ∆𝑉𝐵𝐸 0.025
𝐼𝑐2 = 𝐼𝑐1 𝑒 𝑉𝑇 = 𝐼𝑐1 𝑒 𝑉𝑇 = 1 𝑒 0.025
𝐼𝑐2 = 2.72 𝑚𝐴
𝐼 = 2.72 + 0.52 = 3.24 𝑚𝐴
ii. ∆𝑉𝐵𝐵 = −50 𝑚𝑉
𝑉𝐵𝐵 = 1.2 − 0.05 = 1.15 𝑉
 𝑉𝐵𝐵 1.15
𝐼𝑅 = = = 0.48 𝑚𝐴
𝑅1 + 𝑅2 2.4 𝑘
1.15
𝑉𝐵𝐸 = = 0.575 𝑉
2
∆𝑉𝐵𝐸 −0.025
𝐼𝑐3 = 𝐼𝑐1 𝑒 𝑉𝑇 =1𝑒 0.025

𝐼𝑐2 = 0.37 𝑚𝐴
𝐼 = 0.37 + 0.48 = 0.85 𝑚𝐴

12.6 Variations on the Class AB Configuration

12.6.1 Use of Input Emitter Followers
Figure 12.17 shows a class AB circuit biased
using transistors Q1 and Q2, which also
function as emitter followers, thus providing the
circuit with a high input resistance.
In effect, the Q1–Q2 circuit functions as a unity-
gain buffer amplifier. Since all four transistors
are usually matched, and neglecting the effect
of R3 and R4, we see that the quiescent current
(vI = 0, RL = ∞) in Q3 and Q4 is equal to that in
Q1 and Q2.
Resistors R3 and R4 are usually very small and
are included to compensate for possible
mismatches between Q3 and Q4 and to guard
against the possibility of thermal runaway due to temperature differences between the input and
output-stage transistors.
𝐼𝐸3 ↑→ 𝑉𝑅3 ↑→ 𝑉𝐵𝐸3 ↓→Thus, R3 provides negative feedback that helps stabilize the current
through Q3.
Because the circuit requires high-quality pnp transistors, it is not suitable for IC technology.
12.6.2 Use of Compound Devices
To increase the current gain of the output-stage
transistors, and thus reduce the required base
current drive, the Darlington configuration used to
replace the npn transistor of the class AB stage.
The Darlington configuration is equivalent to a
single npn transistor having 𝛽 ≈ 𝛽1 𝛽2 , but almost
twice the value of VBE.
The Darlington configuration can be also used for pnp transistors, and this is indeed done in
discrete-circuit design.
12.7.1 The Classical CMOS Class AB Output Stages Configuration
CMOS class AB output stage which is similar to
the bipolar circuit with the biasing diodes.
IBIAS flowing through Q1 and Q2 establishes a dc
bias voltage VGG between the gates of QN and QP.
VGG establishes the quiescent current IQ in QN and
QP (at vO = 0).
Unlike the BJT, 𝐼𝐺𝑄𝑁 = 𝐼𝐺𝑄𝑃 = 𝐼𝐺𝑄1 = 𝐼𝐺𝑄2 = 0

For 𝑣𝑜 = 0 𝑎𝑛𝑑 𝑅𝐿 = ∞

(𝑊/𝐿)𝑛
𝐼𝑄 = 𝐼𝐵𝐼𝐴𝑆 𝑟𝑒𝑚𝑒𝑚𝑏𝑒𝑟: 𝑖𝑡 𝑖𝑠 𝑎 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑚𝑖𝑟𝑟𝑜𝑟 𝑠𝑜 𝑛𝑜 𝑛𝑒𝑒𝑑 𝑡𝑜 𝑑𝑒𝑟𝑖𝑣𝑒 𝑎𝑏𝑜𝑣𝑒
(𝑊/𝐿)1
A drawback of the CMOS class AB circuit is the restricted range of output voltage swing.

The maximum value of vO

The minimum value

12.7.2 An Alternative Circuit Utilizing Common-Source Transistors
1. Increase the Output Range
vO can be increased by replacing
QN, QP pair source followers with QN, QP pair common-
source as shown.
For positive vO, QP supplies the load current and allows vO to
go as high as (VDD −|vOVP|), a much higher value than previous.
For negative vO, QN sinks the load current and allows vO to go
as low as −VSS + vOVN. a much larger value than previous.
The circuit provides an output voltage range that is within an overdrive voltage of QN and QP.
The disadvantage of the circuit, however, is its high output resistance,
Rout = ron || rop
To reduce the output resistance, negative feedback is employed as shown.
an amplifier is inserted for each of QN and QP.
verifying the negative feedback:
Assume 𝑣𝑂 ↑→ the top amplifier will cause
𝑉𝐺𝑄𝑃 ↑→ 𝑣𝑆𝐺 ↓ and iDP decreases.

The decrease in iDP causes vO to decrease,

which is opposite to the initially assumed
change, thus, the feedback is negative.
A similar process for the bottom amp.
The two feedback loops are a series–shunt
type (voltage amplifier).
The feedback will reduce the output resistance of the amplifier.
If the loop gain is large, the voltage difference between the two input terminals of each feedback
amplifier, the error voltage, will be small, resulting in vO ≈ vI. For this reason, the two amplifiers
𝜇 are known as error amplifiers.
Both the low output resistance and the near-unity dc gain are highly desirable properties for an
output stage.
Output Resistance:
To derive an expression for Rout.
Consider each half of the circuit separately,
find Routp and Routn and then obtain the overall Rout.

i. Fig. (a) shows the top half of the circuit.

ii. the feedback network is the two-port is a
series-shunt (voltage amplifier) shown in
Fig. (b) and the feedback factor is
𝑣𝑓
𝛽= =1
𝑣𝑜
iii. 𝑅11 = 0 (𝑠ℎ𝑜𝑟𝑡 𝑐𝑐𝑡 𝑝𝑜𝑟𝑡 2) 𝑎𝑛𝑑 𝑅22 = 𝑅𝐿 (𝑜𝑝𝑒𝑛 𝑐𝑐𝑡. 𝑝𝑜𝑟𝑡 1)
iii. The A circuit: include the loading effects of the feedback network 𝑅11 𝑎𝑛𝑑 𝑅22 is in Fig. (c).
The open-loop gain A is found from the circuit in Fig. (c)

𝑣𝑜 = −𝜇𝑣𝑖 (−𝑔𝑚𝑝 (𝑟𝑜𝑝 ||𝑅𝐿 ))

𝑣𝑜
𝐴= = 𝜇𝑔𝑚𝑝 (𝑟𝑜𝑝 ||𝑅𝐿 )
𝑣𝑖

which can be quite low. A similar development applied to the bottom half
The Voltage-Transfer Characteristic
Derive an expression for the DC voltage transfer characteristic, vO vs vI , of the class AB common-
source buffer.
1. Calculate IQ class AB operation quiescent
current with vI = 0 and vO = 0 as in Fig. (a).

Matched transistors

2. vI is applied
The voltage at the output of each of the
error amplifiers increases by 𝜇(𝑣𝑂 − 𝑣𝐼 )
vSGP decreases by 𝜇(𝑣𝑂 − 𝑣𝐼 ) and
vGSN increases by 𝜇(𝑣𝑂 − 𝑣𝐼 )

, iL = vO/RL

Usually (VOV /4𝜇IQRL) << 1, enabling us to express vO

Since at the quiescent point,

Example 12.6
Design a class AB common-source output stage of the type shown in Fig. 12.25, required to
operate from a ±2.5 𝑉 power supply to feed a load resistance RL =100Ω. The transistors available
have Vtn = −Vtp = 0.5 V and kn = 2.5kp = 250 μA/V2. The gain error is required to be less than
2.5% and IQ = 1 mA. VOV = 0.1 V
Solution
The gain error is

μ = 10
which is within the typically recommended range.
Figure (a) shows the circuit in the quiescent
state with dc voltages and currents.
i. 𝑣𝐼 = 0 𝑎𝑛𝑑 𝑣𝑂 = 0
|𝑉𝑆𝐺𝑃 | = |𝑉𝑂𝑉 + 𝑉𝑡𝑝 | = 0.1 + 0.5 = 0.6

𝑉𝐺𝑆𝑁 = 𝑉𝑂𝑉 + 𝑉𝑡𝑛 = 0.1 + 0.5 = 0.6

𝑉𝐺𝑝 = 𝑉𝐷𝐷 − 𝑉𝑆𝐺𝑃 = 2.5 − 0.6 = 1.9 𝑉

𝑉𝐺𝑁 = −𝑉𝐷𝐷 + 𝑉𝐺𝑆𝑁 = −2.5 + 0.6 = −1.9 𝑉

The required (W/L) ratios of QN and QP is

iii. Determine the maximum and minimum allowed values of vO.

Since the circuit is symmetrical, consider only the positive-output or the negative-output case.
a. For vO > 0, QP turns ON and QN turns off and QP conducts all of iL.
the voltage at QN gate drops from the quiescent value of−1.9 V to −2 V, at which point vGSN = Vtn.
An equal change of− 0.1 V appears at the output of the top amplifier, as shown in Fig. 12.28(b).
Analysis of the circuit in Fig. 12.28(b) shows that

For vO > 0.4 V, QP must conduct all the

current iL. and vO = vOmax as shown in Fig.
(c).
12.8 IC Power Amplifiers
A variety of IC power amplifiers are available. Most consist of
1. a high-gain,
2. small-signal amplifier followed by a class AB output stage.
3. Some have overall negative feedback resulting in a fixed closed-loop voltage gain.
4. Others do not have on-chip feedback and are op amps with large output-power capability.
In fact, the output current-driving capability of any general-purpose op amp can be increased by
cascading it with a class B or class AB output stage and applying overall negative feedback. The
additional output stage can be either a discrete circuit or a hybrid IC.

12.8.1 A Fixed-Gain IC Power Amplifier

Our first example is the LM380 (a product of National Semiconductor Corporation), which is a
fixed-gain monolithic power amplifier. A simplified version is shown in Fig. a
The circuit consists of
1. An input differential amplifier Q1 and Q2 as emitter followers for input buffering, and
2. R4 and R5 provide dc paths to ground for the base currents of Q1 and Q2, thus enabling the
input signal source to be capacitively coupled to either of the two input terminals.
2. Q3 and Q4 are a differential pair with an emitter resistor R3 which are biased by two separate
currents:
Q3 is biased by a current from the dc supply VS through the diode-connected transistor Q10, and
R1.
Q4 is biased by a dc current from the output terminal through R2.
Under quiescent conditions (i.e., with no input signal applied) the two bias currents will be equal,
and the current through and the voltage across R3 will be zero.
For the emitter current of Q3 we can write

Assume all VBE are equal

For the emitter current of Q4

VO is the dc voltage at the output, and neglecting the small drop across R5.
Equating I3 and I4 and using the fact that R1 = 2R2 results in

1
VO is biased at approximately 𝑉𝑆 , as desired for maximum output voltage swing.
2

The dc feedback from the output to the emitter of Q4, through R2 acts to stabilize the output dc
bias voltage VO.
the dc feedback functions as:
If for some reason 𝑉𝑂 ↑→ 𝐼𝑅2 ↑→ 𝐼𝐶𝑄4 ↑→ 𝑉𝐵𝑄12 > 0 ↑→ 𝐼𝐶𝑄12 ↑→ 𝑉𝐵𝑄8 ↓→ 𝑉𝑂 ↓
the differential amplifier (Q3, Q4) has a current-mirror load composed of Q5 and Q6.
The single-ended output voltage signal of the first stage appears at the collector of Q6 and thus is
applied to the base of the second-stage common-emitter amplifier Q12.
Transistor Q12 is biased by the constant-current source Q11, which also acts as its active load.
the load of Q12 will be dominated by the reflected resistance due to RL. Capacitor C provides
frequency compensation.
 • The output stage is class AB, utilizing a compound pnp transistor (Q8 and Q9).
• Negative feedback is applied from the output to the emitter of Q4 via resistor R2.

• To find the closed-loop gain consider the small-signal equivalent circuit shown in Fig.
12.30.
Replacing the second-stage common-emitter amplifier and the output stage with an inverting
amplifier block with gain A.
Assume that the amplifier A has high gain and high input resistance, and thus the input signal
current into A is negligibly small.
Under this assumption, an input signal vi applied to the inverting input terminal.
Note that since the input differential amplifier has a relatively large resistance, R3, in the emitter
circuit, most of the applied input voltage appears across R3.
In other words, the signal voltages across the emitter–base junctions of Q1, Q2, Q3, and Q4 are
small in comparison to the voltage across R3.
Accordingly, the voltage gain can be found by writing a node equation at the collector of Q6:

12.8.2 The Bridge Amplifier

It is a popular high-power Amp. It is the bridge amplifier configuration shown in Fig. 12.32
utilizing two power op amps, A1 and A2.
A1 is connected in the noninverting configuration with a gain K = 1 + (R2/R1),
A2 is connected as an inverting amplifier with a gain of equal magnitude K = R4/R3.
The load RL is floating and is connected between the output terminals of the two op amps.
If vI is a sinusoid with amplitude Vi, the voltage swing at the output of each op amp will
be ‫}پ‬K ˆVi, and that across the load will be 2}‫پ‬K ˆVi. Thus, with op amps operated from 15}‫پ‬-
V
supplies and capable of providing, say, a 12}‫پ‬-V output swing, an output swing of 24}‫ پ‬V can
be obtained across the load of the bridge amplifier.
In designing bridge amplifiers, note should be taken of the fact that the peak current drawn
from each op amp is 2K ˆVi/RL. This effect can be taken into account by considering the load
seen by each op amp (to ground) to be RL/2.

Example: Consider the circuit of Fig. 12.32 with R1 = R3 =10 kΩ, R2 = 5 kΩ, R4 =15 kΩ, and
RL = 8Ω.
1. Find the voltage gain and the input resistance. The power supply used is ±18 𝑉.
2. If vI is a 20-V peak-to-peak sine wave, what is the peak-to-peak output voltage?
3. What is the peak load current?
4. What is the load power?
Sol.
𝑉𝑂1 𝑅2
𝐾1 = =1+ = 1.5 𝑔𝑎𝑖𝑛 𝑜𝑓 𝐴1
𝑉𝐼 𝑅1
𝑉𝑂2 𝑅4
𝐾2 = =− = −1.5 𝑔𝑎𝑖𝑛 𝑜𝑓 𝐴2
𝑉𝐼 𝑅3
𝑉𝑂1 − 𝑉𝑂2
𝐾1 = =3
𝑉𝐼