Microprocessor Imp Question
Microprocessor Imp Question
1
Ans:
i. READY :
It is used as acknowledgement from slower I/O device or memory. It is
Active high signal, when high; it indicates that the peripheral device is
ready to transfer data.
ii. ALE :
stands for address Latch Enable, as address and data bus are multiplexed;
ALE is used to lock either Address or Data.
4. List any four instructions from the bit manipulation instructions of 8086 ?
{ 4 marks }
Ans: Bit Manipulation Instructions These instructions are used to perform operations
where data bits are involved, i.e. operations like logical, shift, etc.Following is
the list of instructions under this group –
Instructions to perform logical operation
o NOT − Used to invert each bit of a byte or word.
o AND − Used for adding each bit in a byte/word with the corresponding bit
in another byte/word.
o OR − Used to multiply each bit in a byte/word with the corresponding bit
in another byte/word.
o XOR − Used to perform Exclusive-OR operation over each bit in a
byte/word with the corresponding bit in another byte/word.
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ii. SEGMENT:
It is used to indicate the start of a logical segment. It is the name given to the
segment. Example: the code segment is used to indicate to the assembler the
start of logical segment.
INTR: This is a level triggered interrupt request input, checked during last
clock cycle of each instruction to determine the availability of request.
If any interrupt request is occurred, the processor enters the interrupt
acknowledge cycle.
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9. Draw flag register of 8086 and explain any four flags. { 4 marks }
Ans:
C-Carry Flag : It is set when carry/borrow is generated out of MSB of result. (i.e D7
bit for 8-bit operation, D15 bit for a 16 bit operation).
P-Parity Flag This flag is set to 1 if the lower byte of the result contains even number
of 1’s otherwise it is reset.
AC-Auxiliary Carry Flag This is set if a carry is generated out of the lower nibble,
(i.e. From D3 to D4 bit)to the higher nibble Z-Zero Flag This flag is set if the result
is zero after performing ALU operations. Otherwise it is reset.
S-Sign Flag This flag is set if the MSB of the result is equal to 1 after performing
ALU operation , otherwise it is reset.
O-Overflow Flag This flag is set if an overflow occurs, i.e. if the result of a signed
operation is large enough to be accommodated in destination register.
Control Flags
T-Trap Flag If this flag is set ,the processor enters the single step execution mode.
I-Interrupt Flag it is used to mask(disable) or unmask(enable)the INTR interrupt.
When this flag is set,8086 recognizes interrupt INTR. When it is reset INTR is
masked.
D-Direction Flag It selects either increment or decrement mode for DI &/or SI
register during string instructions.
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10.Explain logical instructions of 8086. (Any Four) { 4 marks }
Ans:
AND- Logical AND
Syntax : AND destination, source
Operation
Destination ←destination AND source
Flags Affected :CF=0,OF=0,PF,SF,ZF
This instruction AND’s each bit in a source byte or word with thesame number bit
in a destination byte or word. The result is put indestination.
Example: AND AX, BX
• AND AL,BL
• AL 1111 1100
• BL 0000 0011
---------------------
• AL 0000 0000 (AND AL,BL)
2) OR – Logical OR
Syntax :OR destination, source
Operation
Destination OR source
Flags Affected :CF=0,OF=0,PF,SF,ZF
This instruction OR’s each bit in a source byte or word with thecorresponding bit in
a destination byte or word. The result is put in a
specified destination.
Example :
• OR AL,BL
• AL 1111 1100
• BL 0000 0011
---------------------
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• AL 1111 1111
3) NOT – Logical Invert
Syntax : NOT destination
Operation: Destination NOT destination
Flags Affected :None
The NOT instruction inverts each bit of the byte or words at the
specified destination.
Example
NOT BL
BL = 0000 0011
NOT BL gives 1111 1100
4) XOR – Logical Exclusive OR
Syntax : XOR destination, source
Operation : Destination XOR source
Flags Affected :CF=0,OF=0,PF,SF,ZF
This instruction exclusive, OR’s each bit in a source byte or wordwith the same
number bit in a destination byte or word.
Ans:
o In 8086, pipelining is the technique of overlapping instruction fetcand
execution mechanism
.
o To speed up program execution, the BIU fetches as many as sixinstruction
bytes ahead of time from memory. The size ofinstruction prefetching queue in
8086 is 6 bytes.
o BIU stores the fetched instructions in a 6 level deep FIFO . TheBIU can be
fetching instructions bytes while the EU is decoding aninstruction or
executing an instruction which does not require use ofthe buses.
o When the EU is ready for its next instruction, it simply reads the instruction
from the queue in the BIU.
o This is much faster than sending out an address to the system memory and
waiting for memory to send back the next instruction byte or bytes.This
improves overall speed of the processor
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13. What is role of XCHG instruction in assembly language program ? Give
example. { 2 marks }
Ans:
Role of XCHG: This instruction exchanges the contents of a register with the
contents of another register or memory location.
Example:
XCHG AX, BX ; Exchange the word in AX with word in BX.
14. State the use of STC and CMC instructions of 8086. { 2 marks }
Ans:
STC – This instruction is used to Set Carry Flag.
CF ~ CF
5. More stack locations are required Less stack locations are required
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16. Explain assembly language program development steps.
Ans:
1. Defining the problem: The first step in writing program is to think very
carefully about the problem that the program must solve.
Ans:
Data Segment
STRG DB 'GOOD MORNING$'
LEN DB ?
DATA ENDS
CODE SEGMENT
START:
ASSUME CS: CODE, DS : DATA
MOV DX, DATA
MOV DS,DX
LEA SI, STRG
MOV CL,00H
MOV AL,'$'
NEXT: CMP AL,[SI]
JZ EXIT
ADD CL,01H
9
INC SI
JMP
NEXT EXIT: MOV LEN,CL
MOV AH,4CH
INT 21H
CODE ENDS
Ans:
DATA SEGMENT
10
NUM1 DB 10H,20H,30H,40H,50H
RESULT DB 0H
CARRY DB 0H
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA
START: MOV DX,DATA
MOV DS, DX
MOV CL,05H
MOV SI, OFFSET NUM1
UP: CALL SUM
INC SI
LOOP UP
MOV AH,4CH
INT 21H
SUM PROC; Procedure to add two 8 bit numbers
MOV AL,[SI]
ADD RESULT, AL
JNC NEXT
INC CARRY
NEXT: RET
SUM ENDP
CODE ENDS
END START
21. Define logical and effective address. Describe physical address generation
process in 8086. If DS=345AH and SI=13DCH. Calculate physical address.
{ 4 marks }
Ans:
A logical address: is the address at which an item (memory cell, storage element)
appears to reside from the perspective of an executing application program. A logical
address may be different from the physical address due to the operation of an address
translator or mapping function.
Effective Address or Offset Address: The offset for a memory operand is called the
operand's effective address or EA. It is an unassigned 16 bit number that expresses
the operand's distance in bytes from the beginning of the segment in which it resides.
In 8086 we have base registers and index registers.
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22.Write an ALP to add two 8 bit numbers. { 4 marks }
Ans:
model small
.data
a db 06h
b db 12h
ends
.code
start:
mov ax,@data
mov ds,ax
mov al,a
mov bl,b
add al,bl
int 3
ends
end start
Ans: The DAA (Decimal Adjust after Addition) instruction makes the result in
Packed BCD from after BCD addition is performed. It works only on AL register.
Ans:
model small
.data
A db 2222h
B db 1111h
Ends
.code
Mov ax,@data
Mov ds,ax
Mov AX,a
Mov BX,b
IMul BX
12
Int 03h
Ends
End
25. Write an ALP to count odd numbers in the array of 10 numbers. { 4 marks }
Ans:
. Model Small
.data
BLK DB 10h,40h,30h,60h
e db ?h
o db ?h
ends
.code
mov ax, @data
mov ds, ax
lea si, BLK
mov bl, 00h
mov bh, 00h
mov cl, 04h
up: mov al, [si]
ror al, 1
jc go
inc bl
jmp next
go: inc bh
next: inc si
dec cl
jnz up
mov e,bl
mov o,bh
int 3
ends
end
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26. Write a MACRO to perform 32 bit by 16 bit division of unsigned numbers.
{ 4 marks }
Ans:
.model small
Div1 macro no1,no2
mov ax,no1
div no2
endm
.data
num1 dw 12346666h
num2 dw 2222h
.code
mov ax,@data
mov ds,ax
div1 num1,num2
ends
end
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Example
Assume DS= 2632H, SI=4567H
DS : 26320H ……...0 added by BIU(or Hardwired 0)
+ SI : 4567H
----------------------------
2A887H
Ans:
DATA SEGMENT
ARRAY DB 15H,05H,08H,78H,56H
DATA ENDS
CODE SEGMENT
START:ASSUME CS:CODE,DS:DATA
MOV DX,DATA
MOV DS,DX
MOV BL,05H
STEP1: MOV SI,OFFSET ARRAY
MOV CL,04H
STEP: MOV AL,[SI]
CMP AL,[SI+1]
JNC DOWN
XCHG AL,[SI+1]
XCHG AL,[SI]
DOWN:ADD SI,1
LOOP STEP
DEC BL
JNZ STEP1
MOV AH,4CH
INT 21H
CODE ENDS
END START
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