EXPERIMENT NO: - 1

A. Design of Half Adder circuit by using Nand gates only: A Half adder circuit is used to add two binary bits at a time. It
has got two inputs as say A and B and two outputs as S (Sum ) and C (Carry).The logical expression for Sum(S) and
Carry( C ) are S = A ⋅⎯B + ⎯A ⋅ B = A ⊕ B and C = A ⋅ B respectively. The truth table of Half Adder circuit is shown in
Table (1). Connect the circuit as shown in Fig (a) (using NAND gates only i.e. by using 7400 IC) to verify the truth
table of Half Adder circuit. Connect the inputs A and B of Fig (a) through two input switches and connect the two
outputs S and C of the circuit of Fig (a) to the two LED’s present on the CDS. Connect pin no 14 of all 7400 IC’s to
VCC = 5V and pin no 7 of all 7400 IC’s to ground. (for Fig (a) ). Now apply various combinations of inputs at A and B
by varying the two input switch position and observe the corresponding LED outputs of Fig (a) to verify the truth table
of Half Adder circuit.
B. Design of Half Subtractor circuit by using Nand gates only: A Half subtractor circuit is used to subtract two binary
bits at a time. It has got two inputs as say A and B and two outputs as D (Difference) and β (Borrow). The logical
expression for Difference and Borrow are D = A ⋅⎯B + ⎯A ⋅ B = A ⊕ B and β = ⎯A.⋅ B respectively. The truth table of
Half Subtractor circuit is shown in Table (2). Connect the circuit as shown in Fig (b) (using NAND gates only i.e. by
using 7400 IC) to verify the truth table of Half subtractor circuit (keep intact the Sum part realisation of Half Adder
circuit of Fig (a) as both S and D satisfy XOR logic between the inputs A and B and modify only the carry part of the
circuit of Fig (a) to realise Borrow β). Connect the inputs A and B of Fig (a) through two input switches and connect
the two outputs D and β of the circuit of Fig (a) to the two LED’s present on the CDS. Connect pin no 14 of all 7400
IC’s to VCC = 5V and pin no 7 of all 7400 IC’s to ground. (for Fig (b) ). Now apply various combination of inputs at A
and B by varying the two input switch position and observe the corresponding LED outputs of Fig (b) to verify the
truth table of Half Subtractor circuit.
Truth Table of Half Adder Circuit. Truth Table of Half Subtractor Circuit.
Dec A B S C Dec A B D β
0 0 0 0 0 0 0 0 0 0
1 0 1 1 0 1 0 1 1 1
2 1 0 1 0 2 1 0 1 0
3 1 1 0 1 3 1 1 0 0
Table (1) Table (2)
C. Design of Five bit Even / Odd parity checker circuit: Connect the circuit as shown in Fig (c) using four two input XOR
gates (i.e. using a single 7486 IC) and one NOT gate (i.e. using a one NOT gate of a single 7404 IC). Connect pin no 14
and pin no 7 to VCC =5 V and Gnd respectively for both 7486 and 7404 IC’s. Apply the five inputs through five input
switches and connect the Yeven output of Fig (c) to one LED of CDS. Then verify that the output LED will glow when
the inputs contain even number of 1’s or all inputs are o’s to indicate even parity of the 5 input bits. If the output LED
does not glow for any inputs which contain odd number of 1’s indicate Odd parity of five input bits. Write down the
truth table showing the relationship between Yeven and the five inputs A, B, C, D and E. The logical expression for the
out put Yeven is :
_________________
Yeven = A ⊕ B ⊕ C ⊕ D ⊕ E
D. Design of the logical function f (A, B, C) = ⎯A ⋅ B + A ⋅⎯C + B ⋅⎯C without minimization by using combination
of AND, OR and NOT gates. Write down the truth table for this logical function and verify this truth table by
connecting the circuit as shown in Fig (d). Connect pin no 14 of all IC’s of Fig (d) to Vcc = 5V and pin no 7 of all IC’s
of Fig (d) to GND. Connect inputs A, B and C to three input switches and the output f (A, B, C) to one LED of the
CDS. Minimize the given logical function by using Karnaugh Map method and then realise this minimized logical
expression by using combination of AND, OR and NOT gates. Comment on the realisation of the same logical function
without or with minimization.

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E. Design a combinational circuit having three inputs M, A, B and two outputs f1 and f2 which satisfy the following
truth table (Table (3)). Use whatever gates you want. Identify the functions of this circuit for two different values of M
i.e. for M=0 and for M=1.
Table (3)
Dec M A B f1 f2
0 0 0 0 0 0
1 0 0 1 1 0
2 0 1 0 1 0
3 0 1 1 0 1
4 1 0 0 0 0
5 1 0 1 1 1
6 1 1 0 1 0
7 1 1 1 0 0
U1B CIRCUIT DIAGRAMS FOR EXPERIMENT NO -1
4 U1B
6 4
U1A 5 6
A 1 U1D U1A 5
3 12 S A 1 U1D
B 7400 D
2 11 3 12
Sum B 7400
13 2 11
U1C 13
7400 U1C
9
7400 7400 Difference
8 9
7400
10 8
10
7400
U2A U2B C 7400 U2C
1 4 9 β
3 6 Carry 8
2 5 U2B 10
U2A 4 Borrow
1 6
7400 7400 7400
3 5
Fig (a) Half Adder Circuit 2
U1A 7400
7400
Α 1
3 Fig (b) Half Subtractor Circuit
Β 2
U1B
4
7486
6
C 5
U1C
9
7486
8
D 10
U1D U1A
12
7486 Yeven
11 1 2
E 13

7486 7404

Fig (C) 5 bit Even Parity Checker Circuit.

U1A
U1A
1 2 1
7404
3
7408
2
A U1A
1
B 3
U1B 2
C 4
6
U1B 7432
5
7408 U1B
3 4
7404 f(A,B,C)
4
6
U1C 5
9
8
7432
10
7408
Fig (d) Realisation of the given logical function

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 EXPERIMENT NO: - 2
A. Realisation of Multiplexer as a universal logic: Connect the circuit as shown in Fig a (1) to Fig a (4) to realise the
truth table of NOT, OR and NOR, AND and NAND, XOR and XNOR gates respectively by using a 74153 (a dual 4:1
multiplexer) multiplexer IC. Connect the input(s) through input switches and outputs to the LED’s present in CDS for
each of the above circuit shown in Fig a(1) to Fig a(4). For realising any logic gates take the one of the two 4:1
multiplexer as shown in each circuit of Fig a(1) to Fig a(4). Connect pin no 16 and pin no 8 to VCC = 5V and GND
respectively for all the above circuits. Connect the strobe/enable input (pin no 1 & 15 of 74153 IC) of the multiplexer
through a switch to enable or disable the multiplexer. To verify the truth table of any gate you have to connect the
strobe/enable input to logical 0. Verify that when strobe/enable input is connected to logical 1 the output of the
multiplexer is always 0 i.e. output being independent of select/address inputs.

B. Design of Full Adder and Full Subtarctor circuit using a 4:1 multiplexer (74153 IC) and a not gate:
Convert the three input truth table for Full Adder and Full Subtractor circuit into two input truth table as shown in
Table-1 and Table-2 respectively by expressing the outputs as a function of third inputs. Connect the circuit as shown in
Fig b (1) and Fig b (2). Connect the input of FA and FS circuit through three input switches and the two outputs to two
LED’s present in CDS for each of the above circuit shown in Fig b(1) to Fig b(2). To verify the truth table of Full adder
and Full Subtarctor circuit connect pin no 16 and pin no 8 to VCC = 5V and GND respectively for all the circuits shown
in Fig b (1) to Fig b (2). Be careful to connect the strobe/enable inputs of both the multiplexer (i.e. pin no 1 and pin no
15) of Fig b (1) and Fig b (2) to logical 0 to enable both the multiplexer of 74153 IC for any select/address inputs.
Connect pin no 14 and pin no 7 of 7404 IC to VCC = 5V and GND respectively for the circuit of Fig b (1) and Fig b (2).
Truth table of Full Adder Table-1 Truth table of Full Subtractor Table-2
A B Ci-1 S Ci S Ci A B βi-1 D βi D βi
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 Ci-1 0 0 0 1 1 1 βi-1 βi-1
0 1 0 1 0 0 1 0 1 1
0 1 1 0 1 ⎯CI-1 Ci-1 0 1 1 0 1 ⎯βi-1 1
1 0 0 1 0 1 0 0 1 0
1 0 1 0 1 ⎯CI-1 Ci-1 1 0 1 0 0 ⎯βi-1 0
1 1 0 0 1 1 1 0 0 0
1 1 1 1 1 Ci-1 1 1 1 1 1 1 βi-1 βi-1

Two input truth table of FA circuit. Two input truth table of FS circuit.
A B S Ci A B D βi
0 0 Ci-1 0 0 0 βi-1 βi-1
0 1 ⎯Ci-1 Ci-1 0 1 ⎯βi-1 1
1 0 ⎯Ci-1 Ci-1 1 0 ⎯βi-1 0
1 1 Ci-1 1 1 1 βi-1 βi-1

C. Design the following logical function by using a 8:1 Multiplexer and one NOT gate:
f (A, B, C, D) = Σ m ( 3,4,5,6,9,11,14,15)

D. Design the following incompletely specified logical function by using multiplexer:

f (A, B, C) = ΠM (0, 2, 4) ⋅ Πd (1, 3, 5).

E. Theoretically realise a 16:1 multiplexer by using several lower order multiplexers only and hence
theoretically realise the logical function f (A,B,C,D)=ΠM (0,1,3,4,6,8,12,14,15): Show the design using
appropriate IC’s and their interconnections with appropriate pins of different IC’s.

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F. Analyse the circuit of Fig (c) and hence determine the functional relationship between inputs (A, B, C, D,
E) and output Y. Express Y in Min term or Max term form and also write down the truth table for the circuit of Fig
(c).

CIRCUIT DIAGRAMS FOR EXPERIMENT NO -2

Vcc = 5V
Vcc = 5V Vcc = 5V Vcc = 5V
U1 U1 U1 U1
6 7
Ynot 6 7
Yor 6 7
Yand 6 7
Yxo
5 1C0 1Y 5 1C0 1Y 5 1C0 1Y 5 1C0 1Y
4 1C1 4 1C1 4 1C1 4 1C1
NC 3 1C2 3 1C2 3 1C2 3 1C2
NC 1C3 1C3 1C3 1C3
10 9 10 9
Ynor 10 9
Ynand 10 9
Yxn
11 2C0 2Y 11 2C0 2Y 11 2C0 2Y 11 2C0 2Y
12 2C1 12 2C1 12 2C1 12 2C1
13 2C2 13 2C2 13 2C2 13 2C2
2C3 2C3 2C3 2C3
14
B 14
B 14
B 14
A 2 A 2 A 2 A 2 A
1 B 1 B 1 B 1 B
15 1G A 15 1G A 15 1G A 15 1G
2G 2G 2G 2G

74153 74153 74153 74153

Fig a(1) Fig a(2) Fig a(3) Fig a(4)

U1A U1A
U1 U1
1 2 6 7 S 1 2 6 7 D
5 1C0 1Y 5 1C0 1Y
4 1C1 4 1C1
3 1C2 3 1C2
7404 1C3 7404 1C3
10
11 2C0 2Y
9 Ci 10
11 2C0 2Y
9
βi
12 2C1 12 2C1
2C2 2C2
Ci-1 13
2C3 β i-1 13
2C3
B 14 B 14
2 A 2 A
1 B A 1 B
A 15 1G 15 1G
2G 2G

74153 74153
Vcc = 5V Vcc = 5V

Fig b(1) Fig b(2)

Full Adder circuit using multiplexer (74153) Full Subtractor circuit using multiplexer (74153)
U1A
1
A 3
7486 U1C
2
B 9
8
7408 U1A
10
U1A 1
1 3
C 3 U1B 2
7432 Y
7408
2 4
D U1A 6
7408
1 2 5
E 7404
Fig(C)

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 EXPERIMENT NO: - 3
A. Realising a BCD to decimal decoder circuit using decoder driver IC 7447 (with active low outputs) and common
anode seven segment LED display LTS – 542: Connect the circuit as shown in Fig (a) Apply any BCD inputs at A, B,
C and D inputs connected through four switches (where A is MSB and D is the LSB input) and check whether you can
able to display all decimal numbers from 0 to 9. Connect RBO output (pin no 4) to one LED’s of he CDS and verify
that RBO output is 1 always for normal decoding and becomes 0 only during zero blanking interval. Also verify the
function table of 7447-decoder driver IC shown in Table-1.
Function Table of Decoder Driver IC 7447. Table –1.
LT RBI BI / RBO BCD inputs Display Mode
0 × × × Display 8 to verify
all 7 segments.
1 1 Normally 1 as output, but output Any BCD Normal decoding.
becomes 0 during 0 blanking interval. inputs. Display 0 to 9.
1 0 Normally 1 as output, but output Any BCD Normal decoding, 0
becomes 0 during 0 blanking interval. inputs. is not displayed.
× × 0 as input × Display blank.
B. Verify the following function table of 74138(a 3 to 8 line decoder with active low outputs) and hence realise the
following multiple output logical function by using this decoder IC and the gates shown: For verifying the function
table of 74138 use the circuit of Fig b (1) and to realise the given multiple output function use the circuit of Fig b (2).
For both these circuits connect the inputs A, B and C applied to the decoder inputs through three input switches.
Connect the two outputs f1 and f2 to two output LED’s of CDS.
f1( A, B, C ) = ∑ m ( 1, 2, 4, 7) and f2 ( A, B, C ) = ∑ m (3, 5, 6, 7). Identify the function f1 and f2 .
Function table of 74138 decoder Table – 2.
G1 ⎯G2A ⎯G2B A B C ⎯Y0 ⎯Y1 ⎯Y2 ⎯Y3 ⎯Y4 ⎯Y5 ⎯Y6 ⎯Y7
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 1 1 1 1 1
1 0 0 0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
0 × × × × × 1 1 1 1 1 1 1 1
× 1 × × × × 1 1 1 1 1 1 1 1
× × 1 × × × 1 1 1 1 1 1 1 1
C. Verify the function table (Table-3) of 74148 (an octal to binary priority encoder with active low inputs and outputs)
using the circuit of Fig (c): Also verify that this can also be used as an ordinary octal to binary encoder when only one
input is activated at any instant of time. Connect the circuit as shown in Fig (c). Connect the inputs 3, 4, 5, 6 and 7
through 5 input switches and connect all the five outputs ⎯A2, ⎯A1, ⎯A0, ⎯GS, ⎯EO to five LED’s of CDS. Connect
inputs 0, 1 and 2 to Vcc= 5 V. Connect the supply pins of all IC’s to 5 V and Gnd pins of all IC’s to power supply GND.
Truth table of 74148 Table –3.
⎯EI ⎯0 ⎯1 ⎯2 ⎯3 ⎯4 ⎯5 ⎯6 ⎯7 ⎯A2 ⎯A1 ⎯A0 ⎯GS ⎯EO
1 × × × × × × × × 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 × 0 1 1 1 1 1 1 1 1 0 0 1
0 × × 0 1 1 1 1 1 1 0 1 0 1
0 × × × 0 1 1 1 1 1 0 0 0 1
0 × × × × 0 1 1 1 0 1 1 0 1
0 × × × × × 0 1 1 0 1 0 0 1
0 × × × × × × 0 1 0 0 1 0 1
0 × × × × × × × 0 0 0 0 0 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0

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D. Design a Normal Encoder (with active high inputs and outputs) having four inputs 0, 1, 2 and 3 and two outputs b1 and b0
satisfying the following truth table. Use whatever chips or device you require. How this circuit can be modified to realise a
priority encoder having four inputs and two outputs.
Table – 4.
0 1 2 3 b1 b0
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1

CIRCUIT DIAGRAMS FOR EXPERIMENT NO -3

R = 330
CA
U1 Vcc = 5 V
D 7 13 a
1 1 A 12 b
C 2 2 B 11 c
B 6 4 C 10 d
A 4 8 D 9 e
NC 5 BI/RBO E 15 f
3 RBI F 14
LT G g .
7447
LTS-542

A=MSB, D=LSB Fig (a)

Vcc = 5V

1 U1A
2
U1 U1 6
15 15 4
f1( A,B,C)
1 Y 0N 14
Y0 1 Y 0N 14 5
C 2 A Y 1N 13
Y1 C 2 A Y 1N 13
B 3 B Y 2N 12
Y2 B 3 B Y 2N 12
7420
A 6 C Y 3N 11
Y3 A 6 C Y 3N 11
4 G1 Y 4N 10
Y4 4 G1 Y 4N 10
5 G2AN Y 5N 9
Y5 5 G2AN Y 5N 9
G2BN Y 6N 7
Y6 G2BN Y 6N 7
Y 7N Y7 Y 7N
9 U1B
74138 74138
10
VCC = 5V VCC = 5V 8 f2( A,B,C)
12
13
7420
Fig b (1) Fig b (2)
A=MSB, C=LSB A=MSB, C=LSB
Vcc = 5V
U1
10 9
11 0 A0 7
12 1 A1 6
13 2 A2
3 1 3 14
4 2 4 GS
5 3 5
6 4 6
7 7
5 15
EI EO

74148

A2=MSB Output, A0=LSB Output

Fig ( C )

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 EXPERIMENT NO: - 4

A. Design of four bit one’s complement binary Adder/Subtractor Circuit: Connect the circuit as shown in Fig (a).
Connect A4 (MSB), A3, B4 (MSB), B3, M (the control input) through five input switches and connect the four outputs
S4, S3, S2, S1 which represent 4 bit SUM or DIFFERENCE in 1’s complement to the four output LED’s of CDS. A4 A3
A2 A1 represent the four Augends or Minuend bits in 1’s complement and B4 B3 B2 B1 represent the four Addend or
B B

Subtrahend bits in 1’s complement. The inputs A2, A1, B2, and B1 are left unconnected i.e. NC (means no connection
B

which is equivalent to logical 1 input for TTL IC). Connect pin no 5 and pin no 12 for 7483 IC to Vcc = 5V and GND
respectively. Connect also pin no 14 and pin no 7 of 7486 IC to Vcc = 5V and GND respectively. Show a table
containing different values of control input M, 4 bit Augend / Minuend bits (A4A3A2A1), 4 bit Addend /Subtrahend bits
(B4B3B2B1) and 4 bit Sum / Difference (S4S3S2S1) bits in 1’s complement, operation performed, and remarks in
B B B

different column. Indicate the operation performed for each input and check whether the results are OK (as required for
1’s complement addition / subtraction operation) or not and check when overflow occurs.

B. Design of four bit two’s complement binary Adder/Subtractor Circuit: Connect the circuit as shown in Fig (b).
For this do not remove the circuit of Fig (a). From circuit of Fig a remove the short circuit between C0 and C4 and
connect the control input M to C0 input. Connect A4 (MSB), A3, B4 (MSB), B3, M (the control input) through five input
switches and connect the four outputs S4, S3, S3, S0 which represent 4 bit SUM or DIFFERENCE in 2’s complement to
the four output LED’s of CDS. A4 A3 A2 A1 represents the four Augend or Minuend bits in 2’s complement and B4 B3
B2 B1 represent the four Addend or Subtrahend bits in 2’s complement. The inputs A2, A1, B2, and B1 are left
B B B

unconnected i.e. NC (means no connection which is equivalent to logical 1 input for TTL IC). Connect pin no 5 and pin
no 12 for 7483 IC to Vcc = 5V and GND respectively. Connect also pin no 14 and pin no 7 of 7486 IC to Vcc = 5V and
GND respectively. Show a table containing different values of control input M, 4 bit Augend / Minuend bits
(A4A3A2A1), 4 bit Addend / Subtrahend bits (B4B3B2B1) and 4 bit Sum / Difference (S4S3S2S1) bits in 2’s complement,
B B B

operation performed, and remarks in different column. Indicate the operation performed for each input and check
whether the results are OK (as required for 2’s complement addition / subtraction operation) or not and check when
overflow occurs.

C. Use of four bit digital magnitude comparator IC 7485 to design 4-bit, 5-bit 16-bit magnitude comparator:
a) Use of 7485 IC (a 4 bit digital magnitude comparator) as a 4-bit magnitude comparator. For this connect the
circuit as shown in Fig c (1). Connect A3, B3 and A>B, A<B, A=B (the three cascading inputs) inputs of 7485 through
five input switches and connect the three outputs OA>B, Oa<B and OA=B to three output LED’s of CDS. Connect pin
no 16 and pin no 8 to Vcc = 5 V and GND respectively. Connect A2, A1, A0 and B2, B1, B0 to logical 1 or left it
unconnected. By varying the five inputs verify the function table – 1 for the 7485 IC and also verify how this 7485 IC
can be used as a 4-bit magnitude comparator.
b) Use of 7485 IC (a 4 bit digital magnitude comparator) as a 5-bit magnitude comparator: For this connect the
circuit as shown in Fig c (2). Connect A4, B4, A0, B0 inputs of 7485 through four input switches and connect the three
outputs OA>B, Oa<B and OA=B to three output LED’s of CDS. Connect pin no 16 and pin no 8 to Vcc = 5 V and GND
respectively for 7485 IC and Connect pin no 14 and pin no 7 to Vcc = 5 V and GND respectively for the IC 7486 and
7404. By varying the inputs (5 bits of A4A3A2A1A0 and B4B3B2B1B0 of which A4, B4, A0 and B0 can be varied by
B B B B

varying these four switch position) verify how this 7485 IC can be used as a 5-bit digital magnitude comparator.
D. Study of 74180 IC (a 8 bit parity Generator/Checker IC):
a) Use of 74180(an 8 bit parity Generator/Checker IC 74180) as an 8 bit EVEN or ODD parity checker circuit. For this
connect the circuit as shown in Fig d (1). Connect the three inputs F, G, H and two cascading inputs EI and OI through
five input switches. Connect the other five inputs A, B, C, D, E to logical 1 (means no connection are made to these 5
inputs). Connect the two outputs EO (Even output) and OO (Odd output) to two output LED’s of CDS. Connect pin no
14 and pin no 7 to Vcc = 5V and GND respectively for 74180IC. By varying the inputs verify the function table – 2 of
74180 IC.
b) Use of 74180(an 8 bit parity Generator/Checker IC 74180) as a 9 bit EVEN or ODD parity checker circuit. For this
connect the circuit as shown in Fig d (2). The ninth input (I) for the 9 bit even parity checker circuit is connected to OI
input, thus the nine inputs to the 74180 IC are A, B, C, D, E, F, G, H and I. Connect the five inputs E, F, G, H and I
through five input switches. Connect the other four inputs A, B, C and D to logical 1 (means no connections are made

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 to these 4 inputs). Connect the two outputs EO (Even output) and OO (Odd output) to two output LED’s of CDS.
Connect pin no 14 and pin no 7 to Vcc = 5V and GND respectively for 74180 and 7404 IC. By varying 9 (nine) input
verify that LED connected to EO output of 74180 IC glows only when the 9 input bits have Even parity and LED
connected to OO output of 74180 IC glows only when the 9 input bits have Odd parity. Verify that only one out of two
output LED’s will glow at a time and when LED at EO glows ⇒ Even parity (for 9 inputs) and when LED at OO glows
⇒ODD parity (for 9 inputs).
c) Use of 74180 (an 8 bit parity Generator/Checker IC 74180) as a 10-bit EVEN parity generator circuit. For
this connect the circuit as shown in Fig d (3) The ninth input (I) for the 9 bit even parity generator circuit is connected
to EI cascading input (as shown in Fig d (3), thus the nine inputs to the 74180 IC are A, B, C, D, E, F, G, H and I.
Connect the five inputs E, F, G, H and I through five input switches. Connect the other four inputs A, B, C and D to
logical 1 (means no connections are made to these 4 inputs). Connect the output EPGO (the 10 th Even parity generated
bit) to one output LED’s of CDS. Connect pin no 14 and pin no 7 to Vcc = 5V and GND respectively for 74180 and
7404 IC. By varying 9 inputs (of which five inputs at E, F, G, H and I can be varied as they are connected to five input
switches) verify that LED connected to EPGO output of 74180 IC glows only when the 9 input bits have odd parity and
LED connected to EPGO output of 74180 IC will not glow when the 9 input bits have even parity. This verification
ensures that the circuit function as a 10-bit EVEN parity generator.

E. How would you theoretically cascade two 7485 IC (a 4 bit digital magnitude comparator) to realise 8 bit
digital magnitude comparator? Show the circuit diagram using appropriate pin connections.

F. How would you theoretically use a single 74180 IC to realise 5 bit EVEN / ODD parity checker circuit?
Show the circuit diagram using appropriate pin connections.

G. How would you theoretically use a single 74180 IC to realise 10 bits ODD parity generator circuit? Show
the circuit diagram using appropriate pin connections.

H. How would you theoretically cascade two 74180 to realise 16 bit EVEN / ODD parity checker circuit using 74180
IC? Show the circuit diagram with appropriate pin connections.

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 Function Table – 1 of 7485 IC.

Comparing inputs
Cascading Inputs Outputs
IA>B IA<B IA=B OA>B OA<B OA=B
× × × 1 0 0
A>B
× × × 0 1 0
A<B
0 0 0 1 1 0
A=B
0 0 1 0 0 1
A=B
0 1 0 0 1 0
A=B
0 1 1 0 0 1
A=B
1 0 0 1 0 0
A=B
1 0 1 0 0 1
A=B
1 1 0 0 0 0
A=B
1 1 1 0 0 1
A=B

Function Table – 2 of 74180 IC

INPUTS OUTPUTS
Parity of inputs A through H (the 8 inputs) OI/ODD EO / ∑EVEN OO / ∑ODD
EI/EVE
N
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
× 1 1 0 0
× 0 0 1 1
Note: Connect the three cascading inputs A>B, A<B, A=B and the other two inputs A3, and B3 to five input switches from extreme
left position. (A>B input switch should be on extreme left and B0 input switch should be on extreme right. Connect the three outputs
OA>B, OA<B and OA=B to three output LED’s of CDS from extreme left to right position i.e. OA>B output LED should be at extreme left
and OA=B output LED should be at extreme right position. Any unconnected input or NC at any pin is equivalent to logical 1 input
for all TTL IC’s. NC ⇒ no Connection.

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 CIRCUIT DIAGRAMS FOR EXPERIMENT NO -4
U1 U1
A1 NC 10 9 S1 A1 NC 10 9 S1
NC 8 A1 S1 6 NC 8 A1 S1 6
A2 A2 S2
S2 A2 A2 S2
S2
A3 3 2 S3 A3 3 2 S3
1 A3 S3 15 1 A3 S3 15
A4 A4 S4
S4 A4 A4 S4
S4
U1A 11 U1A 11
1 7 B1 1 7 B1
B1 B2 7483
B1 B2 7483
NC 3 4 NC 3 4
2 16 B3 2 16 B3
B4 B4
13 14 13 14 NC
7486 C0 C4 7486 C0 C4

U1B U1B
EO OO
B2 4 B2 4
NC 6 NC 6
5 5
5 6
7486 7486
EO
V D
E
U1C U1C
74180 ND
B3 9 B3 9
8 8
10 10 U1

A B CD E F GH EO
I I
7486 7486
I
8 9 1 1 1 1 1 2 3 4
U1D U1D 0 1 2 3
B4 12 B4 12 NCNCNCNC
A B C D E F GH
1
11 11 U1
13 13 Fig d (2) 7404

7486 7486
M M
2

Fig ( a ) 4 bit 1's Complement Adder/Subtractor circuit Fig ( b ) 4 bit 2's Complement Adder/Subtractor circuit
EPGO
EO OO
NC
NC
NC 2 1
U1A
5 6 5 6
7486 10
10 12 A0
A0 A1 EO EO
12 13 V D V D
E E
13 A1
A4 15 A2
U1 74180 ND 74180 ND
15 A2 9 A3
A3 9 A3 U1 11 B0 U1
11 B0 NC 14 B1 7485 U1
NC 14 B1 7485
3 U1A B4 1 B2
B2 B3 A B CD E F GH EO A B CD E F GH EO
B3 1 B0 2 7 OA<B I I I I
2 B3 7 1 2 3 A<B A<B 6
A<B A<B A<B OA<B A=B A=B OA=B
A=B 3 6 OA=B A0 4 5 OA>B 8 9 1 1 1 1 1 2 3 4 8 9 1 1 1 1 1 2 3 4
4 A=B A=B 5 A>B A>B NCNCNC 1NC
0NC 2 3 0 1 2 3
A>B A>B A>B OA>B NCNCNCNC
A B C D E F G H EI OI
7404 A B C D E F GH 1 2
7404
Fig c (1) Fig c (2) Fig d (1) Fig d (3)
I

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- 10 -
 EXPERIMENT NO: - 5
A. Verification of excitation table of J-K flip-flop: To verify the excitation table – 1 of J-K flip-flop connect the circuit as
shown in Fig (a). Connect the PR, CLR, J and K inputs of J-K flip-flop (IC 7476, a dual J-K flip-flop) to four input
switches and the output Q to one of the LED of CDS. Connect pin no 5 and pin no 13 to VCC = 5V and GND
respectively for 7476 IC. Apply external clock from the TTL clock output of CDS to the clock input (pin no 1 of 7476
IC). Verify that 7476 is a negative edge triggered J-K flip-flop. How would you connect J-K flip-flop to use it as a ÷ 2
or Mod 2 counter?
B. Verification of excitation table of D flip-flop: To verify the excitation table – 2 of D flip-flop connect the circuit as
shown in Fig (b). Connect the PR, CLR and D inputs of D flip-flop (IC 7474, a dual D type flip-flop) to three input
switches and the output Q to one of the LED of CDS. Connect pin no 14 and pin no 7 to VCC = 5V and GND
respectively for 7474 IC. Apply external clock from the TTL clock output of CDS to the clock input (pin no 3 of 7474
IC). Verify that 7474 is a positive edge triggered D type flip-flop.
C. Design of T type flip-flop from D type flip flop (using 7474, a dual D flip-flop): To verify the excitation table –3 of T
type flip-flop using D type flip-flop, connect the circuit as shown in Fig (c). The minimised expression for D input is: D
= T ⊕ Qn. (Verify this by using the flip-flop conversion (T type from D type) state table. Connect the PR, CLR and T
inputs (as shown in Fig (C )) to three input switches and the output Q to one of the LED of CDS. Connect pin no 14 and
pin no 7 to VCC = 5V and GND respectively for 7474 and 7486(a quad 4 input XOR gates) IC. Apply external clock
from the TTL clock output of CDS to the clock input (pin no 3 of 7474 IC). Verify the excitation table –3 of T type flip-
flop, and also verify that T type flip-flop so realised from D type flip-flop IC 7474 (a positive edge triggered flip-flop)
is also a positive edge triggered flip-flop.

Excitation Table-1 (for J-K F/F) Excitation Table-2 (for D F/F) Excitation Table-3 (for T F/F).
__ ____ __ ____ __ ____
CLK PR CLR J K QN+1 CLK PR CLR D QN+1 CLK PR CLR T QN+1

× 0 1 × × 1 × 0 1 × 1 × 0 1 × 1
× 1 0 × × 0 × 1 0 × 0 × 1 0 × 0
1 1 1 0 0 QN 1 1 1 0 0 1 1 1 0 QN
1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 ⎯QN
1 1 1 1 0 1
1 1 1 1 1 ⎯QN

D. Design of asynchronous up counter using J-K flip-flops (IC 7476) having initial count 0 and modulus 6, with a
prevention of lockout condition: This counter design requires the following minimised expression for preset and clear
inputs of three J-K flip-flop: PR0 = PR1 = PR2 = 1 and CLR0 = CLR1 = CLR2 = ⎯Q2 + ⎯Q1. (Verify this by using the
appropriate design procedure for asynchronous counter design). To realise the above counter connect the circuit as
shown in Fig (d). Connect all J’s and K’s inputs of 7476 IC’s to logical 1. Connect pin no 5 and pin no 13 of 7476 IC to
VCC = 5V and GND respectively. Connect pin no 14 and 7 of 7432 to VCC = 5V and GND respectively. Connect the
output Q2 (MSB), Q1 and Q0 (LSB) of the counter to three LED’s of CDS. Apply external clock input from TTL clock
outputs of CDS to the clock input of LSB J-K flip-flop and the clock inputs for other flip-flop are as shown in Fig (d).
Verify the following count sequence by observing the three output LED’s: 0→1→2→3→4→5→0→1→2→3→4→5.
E. Design of Synchronous up counter using D flip-flops (IC 7474) having initial count 0 and modulus 5, without
prevention of lockout condition: This counter design requires the following minimised expressions for the three D
inputs of D flip-flop: D0 = ⎯Q2⋅⎯Q0, D1 = Q1 ⊕ Q0 and D2 = Q1⋅ Q0. (Verify this by using the appropriate design
procedure for synchronous counter design). To realise the above counter connect the circuit as shown in Fig (e).
Connect all the preset and clear inputs of all D flip-flops (i.e. of 7474 IC) to logical 1. Connect pin no 14 and pin no 7
of 7474, 7408 and 7486 IC’s to VCC = 5V and GND respectively. Connect the output Q2 (MSB), Q1 and Q0 (LSB) of the
counter to three LED’s of CDS. Apply external clock from TTL clock output of CDS to the clock inputs of all the D
flip-flop (i.e. IC 7474). Verify for the above counter the following count sequence by observing the output of three
LED’s: 0→1→2→3→4→0→1→2→3→4.

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F. Design theoretically a 3 bit Gray code synchronous counter of modulus 5 having the following sequence of states,
using J-K flip-flop by preventing lockout: 000→001→011→010→110→000→001→011→010→110. Show the
complete circuit with proper connection with appropriate pins of the different IC’s.

G. Design theoretically an asynchronous counter having the following count sequence using J-K flip-flop by preventing
lockout: 0→1→2→3→4→0→1→2→3→4. Show the complete circuit with proper connection with appropriate pins of
the different IC’s.

CIRCUIT DIAGRAMS FOR EXPERIMENT NO -5

Q Q Q
EXT TTL CLK 3

NC NC NC U1A
D0
7408
3 2
1 1
5 4 5 6 5 6
U1A U1A U1A FF0 C D
Q Q Q Q Q Q 1 L 4
7476 7474 7474 K PR
CL U1A
2 3 4 1 4 1 CLR0 PR0 1 2
PR CL PR CL PR CL
7474
C C C Q Q
L L L
J K K D K D K
6 5
Q0
4 1 1 2 3 2 3
6

S1 S3 S2 S1 3 S2
S1 S3 S4 S2 D1
U1A 1 1 VCC = 5V
1 2
7486 Vcc=5V
FF1 C D
PR D CLK CLR PR CLK CLR 13 L 10
K PR
CL U1B
PR J CLK K CLR CLR1 PR1
Verification of J-K Flip-Flop Verification of D Flip-Flop
1 2 7474
3 Q Q
Fig ( a ) Fig ( b ) M
T flip-flop from D flip-flop O Q1
D
- U1A 8 9
Fig ( c ) 5 F 7486 NC
S3 i
g
s
y (
n e
c ) 1 2 D2
VCC = 5V h
r
Q0 Q1 Q2 T o 3 2
n FF2 C D
PR0 PR1 PR2 o 6
1 L 4
u CLR2
K PR
CL U2A PR2
Vcc = 5V Vcc = 5V Vcc = 5V
s
7474
K 2 7 2 c U1B
Q Q
L 4
J Q
15 9
J Q
11 4
J Q
15 o 7408
C P Q0 P Q1 P Q2 u Q2
1 R U1A
CLK 7476
6 R1B
U
CLK 7476
1 R2A
U
CLK 7476
n 6 5
L t
e
T 16 FF0 14 NC 12 FF1 10 16 FF2 14
r 4 5
T K C Q K C Q K C Q
L L L
T
X 3 8 3
E CLR0 CLR1 CLR2

2
3 U1A
1
7432

MOD-6 asynchronous counter

Fig (d)

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- 12 -
 EXPERIMENT NO: - 6
I. Study of asynchronous decade counter IC 7490: Connect the circuit as shown in Fig a (1) to Fig a (4) respectively to
realise the following and verify the function table-1 of 7490 IC (a decade asynchronous counter) and also verify that the counter is
negative edge triggered: For all the four circuits of Fig a (1) to Fig a (4) connect the four inputs MR1, MR2, MS1 and MS2 to four
input switches. Connect pin no 5 and pin no 10 to Vcc = 5V and GND respectively for all the circuit of Fig a (1) to Fig a (4).
a) Using circuit of Fig a (1) (Mode A connection) verify the MOD 10 or ÷ 10 decade counter sequence by observing the four
counter output connected to four LED’s. For this apply TTL clock from CDS to the clock input CP1 of the 7490 counter. Mod 10
sequence is: 0→1→2→3→4→5→6→7→8→9→0→1 and so on.
b) Using circuit of Fig a (2) (Mode B connection) verify the MOD 10 or ÷ 10 symmetrical bi-quinary sequence by observing the
four counter output connected to four LED’s. For this apply TTL clock from CDS to the clock input CP2 of the 7490 counter. Mod
10 symmetrical bi-quinary sequence is: 0→2→4→6→8→1→3→5→7→9→0→2 and so on.
c) Using circuit of Fig a (3) (Mode C connection) verify the MOD 2 or ÷ 2 sequence by observing the output of LED connected
with Q0 output of the counter. For this apply TTL clock from CDS to the clock input CP1 of the 7490 counter. Mod 2 sequence is
0→1→0 and so on.
d) Using circuit of Fig a (4) (Mode D connection) verify the MOD 5 or ÷ 5 sequence by observing the output of LED connected
to Q3, Q2 and Q1 outputs of the counter. For this apply TTL clock from CDS to the clock input CP2 of the 7490 counter. Mod 5
sequence is 0→1→2→3→4→0→1 and so on.
J. Study of asynchronous binary counter or MOD 16 (÷16 counter) IC 7493: Connect the circuit as shown in Fig b
(1) to Fig b (4) respectively to realise the following and verify the function table-2 of 7493 IC (a binary asynchronous counter) and
also verify that the counter is negative edge triggered: For all the four circuits of Fig b (1) to Fig b (4) connect the two inputs MR1
and MR2 to two input switches. Connect pin no 5 and pin no 10 to Vcc = 5V and GND respectively for all the circuit of Fig b (1) to
Fig b (4).
a) Using circuit of Fig b (1) (Mode A connection) verify the MOD 16 or ÷ 16 binary counter sequence by observing the four
counter output connected to four LED’s. For this apply TTL clock from CDS to the clock input CP1 of the 7493 counter. Mod 16
sequence is: 0→1→2→3→4→5→6→7→8→9→10→11→12→13→14→15→0→1 and so on.
b) Using circuit of Fig b (2) (Mode B connection) verify the MOD 16 or ÷ 16 symmetrical bi-octal sequence by observing the
four counter output connected to four LED’s. For this apply TTL clock from CDS to the clock input CP2 of the 7493 counter. Mod
16 symmetrical bi-octal sequence is: 0→2→4→6→8→10→12→14→1→3→5→7→9→11→13→15→0→2 and so on.
c) Using circuit of Fig b (3) (Mode C connection) verify the MOD 2 or ÷ 2 sequence by observing the output of LED connected
with Q0 output of the counter. For this apply TTL clock from CDS to the clock input CP1 of the 7493 counter. Mod 2 sequence is
0→1→0 and so on.
d) Using circuit of Fig b (4) (Mode D connection) verify the MOD 8 or ÷ 8 sequence by observing the output of LED connected
to Q3, Q2 and Q1 outputs of the counter. For this apply TTL clock from CDS to the clock input CP2 of the 7493 counter. Mod 8
sequence is 0→1→2→3→4→5→6→7→0→1 and so on.

Function Table – 1 of 7490 Counter Function Table – 2 of 7493 Counter

MR1 MR2 MS1 MS2 Q3 Q2 Q1 Q0 MR1 MR2 Q3 Q2 Q1 Q0

1 1 0 × 0 0 0 0 1 1 0 0 0 0
1 1 × 0 0 0 0 0 0 × Count enable ⇒Counter increment
× × 1 1 1 0 0 1 × 0 Count enable ⇒Counter increment
0 × 0 × Count enable →Counter increment 0 0 Count enable ⇒Counter increment
0 × × 0 Count enable→Counter increment

× 0 0 × Count enable→Counter increment

× 0 × 0 Count enable→Counter increment

K. Study of synchronous decade counter IC 74160 to realise counter of various modulus: Connect the circuit as
shown in Fig c (1) to Fig c (3). For all the three circuits connect P3, P2, P1 and P0 to four input switches and the four outputs Q3, Q2,
Q1 and Q0 of the counter and TC output of the counter to five LED’s of CDS. Connect pin no 16 and pin no 8 of all the 74160 IC
used in Fig c (1) to Fig c (3) to Vcc = 5V and GND respectively. Apply TTL clock from CDS to the clock input pin no 2 of 74160
for all the three circuits. Verify the function table - 3 of 74160 synchronous counter by observing the four output LED’s connected
to the four outputs (Q3, Q2, Q1 and Q0) of the counter.
a) To realise decade counter or ÷10 counter using 74160(using circuit of Fig c (1)) load 4 bit parallel data inputs as 0000. Verify
that decade or ÷10 counter sequence is 0→1→2→3→4→5→6→7→8→9→0→1 and so on and also verify that this counter is

- 13 -
 positive edge triggered. Also note and observe the status of LED output connected to TC output of the counter for the above
sequence.
b) To realise Mod 6 counter or ÷6 counter using 74160(using circuit of Fig c (2)) load 4 bit parallel data inputs as 0100. Verify that
decade or ÷10 counter sequence is 4→5→6→7→8→9→4→5 and so on and also verify that this counter is positive edge triggered.
Also note and observe the status of LED output connected to TC output of the counter for the above sequence.
c) To realise Mod 4 counter or ÷ 4 counter using 74160(using circuit of Fig c (3)) load 4-bit parallel data inputs as 0110. Verify
that Mod 4 or ÷4 counter sequence is 6→7→8→9→6→7→8→9 and so on and also verify that this counter is positive edge
triggered. Also note and observe the status of LED output connected to TC output of the counter for the above sequence.
L. Study of synchronous UP/DOWN decade counter 74192 IC: To realise UP or DOWN counter using 74192 (a
decade UP/Down counter IC) connect the circuit as shown in Fig d (1) and Fig d (2) respectively. For all the two circuits,
connect d/P3, C/P2, B/P1 and A/P0 to four input switches and the six outputs Q3, Q2, Q1, Q0, ⎯CO and ⎯BO of the counter is
connected to six LED’s of CDS. Connect pin no 16 and pin no 8 of all the 74192 IC used in Fig c (1) to Fig c (3) to Vcc = 5V and
GND respectively.
a) To realise UP count sequence by using 74192 counter IC apply TTL clock from CDS to the UP clock input (pin no 5 of 74192)
and connect DN clock input (pin no 4 of 74192) to logical 1 for the circuit of Fig d (1). Verify the function table - 4 of 74192 (a
synchronous UP/DOWN counter) by observing the four output LED’s connected to (Q3, Q2, Q1 and Q0) the four outputs of the
counter. Verify the UP count sequence 0→1→2→3→4→5→6→7→8→9→0→1 and so on. Also verify that this counter is positive
edge triggered. Note the status of LED’s connected at ⎯CO and ⎯BO output during UP count sequence when the counter output
switches from count 0 to count 9 and during down count sequence when the counter output switches from count 9 to count 0
respectively.
b) To realise DOWN count sequence by using 74192 counter IC apply TTL clock from CDS to the DOWN clock input (pin no 4 of
74192) and connect UP clock input (pin no 5 of 74192) to logical 1 for the circuit of Fig d (2). Verify the function table - 4 of
74192, a synchronous UP/DOWN counter by observing the four output LED’s connected to (Q3, Q2, Q1 and Q0) the four outputs
of the counter. Verify the DOWN count sequence 9→8→7→6→5→4→3→2→1→0→9→8 and so on. Also verify that this counter
is positive edge triggered. Note the status of LED’s connected at ⎯CO and ⎯BO output during UP count sequence when the counter
output switches from count 0 to count 9 and during down count sequence when the counter output switches from count 9 to count 0
respectively.

Function Table – 3 of 74160 (Synchronous decade counter)

⎯R ⎯PE ENP ENT CLK P3 P2 P1 P0 Q3 Q2 Q1 Q0

0 × × × × × × × × 0 0 0 0⇒ Asyn Reset/Clear.
1 0 × × f 1 0 0 1 1 0 0 1⇒Syn. Parallel Load.
1 1 1 1 f × × × × Count enable/ Counter increment
1 1 0 × f × × × × Counter Stops / Counter Hold
1 1 × 0 f × × × × Counter Stops / Counter Hold

Function Table – 4 of 74192 (an UP/DOWN synchronous decade counter)

_____
CL LOAD UP DN D/P3 C/P2 B/P1 A/P0 Q3 Q2 Q1 Q0
R
1 × × × × × × × 0 0 0 0⇒ Clear
0 0 × × 1 0 0 0 1 0 0 1⇒ Load
0 1 f 1 × × × × Counter increment⇒ Up count sequence
0 1 1 f × × × × Counter decrement⇒ Down count sequence
0 1 0 × × × × × Counter stop⇒ Counter Hold
0 1 × 0 × × × × Counter stop⇒ Counter Hold

M. How would you practically realise MOD-7 counter using 7490 IC (an asynchronous decade counter)?

N. How would you practically realise MOD-13 counter using 7493 IC (an asynchronous MOD 16 or ÷ 16
binary counter)?

O. How would you theoretically cascade several 74160 (a synchronous decade counter or Mod-10 counter IC)
to realise a MOD 85 or ÷ 85 counter? Show the interconnections with proper pin diagram.

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P. How would you theoretically cascade several 74161 (a synchronous binary counter or Mod-16 counter IC)
to realise a MOD 213 or ÷ 213 counter? Show the interconnections with proper pin diagram. (74160 IC
and 74161 IC’s are pin to pin compatible).

Q. How would you theoretically cascade two 7490 IC to realise ÷100 (Mod 100) counter.

CIRCUIT DIAGRAMS FOR EXPERIMENT NO - 6

14 12 14 12 14 12
CP1 NC 14 12
CP1 1 A QA 9
Q0 CP1 1 A QA 9
Q0 CP1 A QA 1 9
Q0 1 A QA 9 Q0 NC
CP2 B QB 8
Q1 CP2 B QB 8
Q1 NC CP2 B QB 8
Q1 NC CP2 B QB 8 Q1
U1 QC 11
Q2 U1 QC 11
Q2 U1 QC 11
Q2 NC U1 QC 11 Q2
2
7490 QD Q3 2
7490 QD Q3 2
7490 QD Q3 NC 2
7490 QD Q3
MR1 3 R0(1) MR1 3 R0(1) MR1 3 R0(1)
MR1 3 R0(1)
MR2 6 R0(2) MR2 6 R0(2) MR2 6 R0(2)
MR2 6 R0(2)
MS1 7 R9(1) MS1 7 R9(1) MS1 7 R9(1)
MS1 7 R9(1)
MS2 R9(2) MS2 R9(2) MS2 R9(2) MS2 R9(2)
Fig a(1) Mode - A Fig a(2) Mode - B Fig a(3) Mode - C Fig a(4) Mode - D

14 12 14 12 14 12
CP1 NC 14 12
CP1 1 A QA 9
Q0 CP1 1 A QA 9
Q0 CP1 1 A QA 9
Q0 1 A QA 9
NC
CP2 B QB 8
Q1 CP2 B QB 8
Q1 NC CP2 B QB 8
Q1 NC CP2 B QB 8
Q1
U1 QC 11
Q2 U1 QC 11
Q2 U1 QC 11
Q2 NC U1 QC 11
Q2
2
7493 QD Q3 2
7493 QD Q3 2
7493 QD Q3 NC 2
7493 QD Q3
MR1 3 R0(1) MR1 3 R0(1) MR1 3 R0(1) MR1 3 R0(1)
MR2 6 R0(2) MR2 6 R0(2) MR2 6 R0(2) MR2 6 R0(2)
NC 7 R9(1) NC 7 R9(1) NC 7 R9(1) NC 7 R9(1)
NC R9(2) NC R9(2) NC R9(2) NC R9(2)

Fig b(1) Mode - A Fig b(2) Mode - B Fig b(3) Mode - C Fig b(4) Mode - D

P0 3 14 Q0 P0 0 3 14 Q0 P0 0 3 14 Q0
4 A QA 13 4 A QA 13 4 A QA 13
P1 B QB Q1 P1 0 B QB Q1 P1 1 B QB Q1
P2 5 12 Q2
Q3 P2 1 5 12 Q2
Q3 P2 1 5 12 Q3
Q2
6 C QC 11 6 C QC 11 6 C QC 11
P3 D QD Q3 P3 0 D QD Q3 P3 0 D QD Q3
15 TC 15 TC 15 TC
Vcc = 5V 7 RCO Vcc = 5V 7 RCO Vcc = 5V 7 RCO
10 ENP 10 ENP 10 ENP
2 ENT 74160 2 ENT 74160 2 ENT 74160
TTLCLK CLK U1 1 TTLCLK CLK U1 1 TTLCLK CLK U1 1
9 7404 9 7404 9 7404
1 LOAD 1 LOAD 1 LOAD
CLR U1 CLR U1 CLR U1

2 2 2
Fig c(1) Fig c(2) Fig c(3)
Mod-10(decade) counter by 74160 Mod-6 (decade) counter by 74160 Mod-4 (decade) counter by 74160

P0 15 3 Q0 P0 15 3 Q0
1 A QA 2 1 A QA 2
P1 10 B QB 6
Q1 P1 10 B QB 6
Q1
P2 9 C QC 7
Q2 P2 9 C QC 7
Q2
P3 D U1 QD Q3 P3 D U1
QD Q3
74192 74192
TTL CLK 5 12 CO 5 12 CO
4 UP CO 13 4 UP CO 13
11 DN BO BO TTL CLK 11 DN BO BO
14 LOAD 14 LOAD
CLR CLR

Vcc = 5 V Fig d (1) Vcc = 5 V Fig d (2)

Circuit for up counter using 74192 IC Circuit for down counter using 74192 IC

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- 15 -
 EXPERIMENT NO: - 7
A. Study of 64-bit Read/Write memory using 74189 IC: The 74189 IC is a high speed 64-bit RAM organized as
a 16- word by 4- bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs
are 3-state and are in the high impedance state whenever the Chip Select (⎯CS) input is high. The outputs are active only
in the Read mode and the output data is the complement of the stored data. For this connect the circuit as shown in Fig
(a). Connect ⎯WE, A0, A1, A2 and A3 to five input switches (where S5 as MSB and S1 as LSB switch). Connect the four
outputs ⎯O1,⎯O2, ⎯O3 and ⎯O4 to four output LED’s of the CDS. Connect the data inputs to D4 = 0, D3 = 1, D2 = 1 and D0
= 0 permanently. Connect pin no 16 and pin no 8 to Vcc = 5V and GND respectively for 74189 IC. Connect ⎯CS input
(pin no 2) to GND. Now by varying the combination of five input switches verify the following function Table-1 by
observing the status of four output LED’s connected at four outputs ⎯O1,⎯O2, ⎯O3 and ⎯O4 respectively. To verify the
volatile nature of this memory device first switch off the power to the CDS for some time and again switch on the power
to the CDS. Now observe or read the contents of any previous memory location, changes in the contents of any previous
memory location proves the volatile nature of this memory device.
Function Table - 1

Operat
⎯WE
⎯CS

Mode
⎯Q4

⎯Q3

⎯Q2

⎯Q1
A3

A2

A1

A0

D4

D3

D2

D1

ing
0 0 0 0 0 0 0 1 1 0 NG NG NG NG ⇒ Writing
onto memory
location 0000.
(output
inactive)
0 1 0 0 0 0 0 1 1 0 1 0 0 1 ⇒Reading
from memory
location 0000.
(output active)
0 0 1 1 1 1 0 1 1 0 NG NG NG NG ⇒ Writing
onto memory
location 1111.
(output
inactive)
0 1 1 1 1 1 0 1 1 0 1 0 0 1 ⇒Reading
from memory
location 1111.
(output active)
1 × × × × × × × × × NG NG NG NG ⇒ Output
tristated i.e.
High
impedance
(Reading /
Writing both
disabled)

B. Study of Schmitt trigger inverter using 7414 IC (a hex Schmitt trigger inverter IC):
a) For Schmitt trigger as inverter connect the circuit as shown in Fig b (1). Connect input (pin no 1) to one
input switch and connect the output (pin no 2) to one LED of the CDS. Connect pin no 14 and pin no 7 to Vcc = 5V and
GND respectively for 7414 IC. Now verify the truth table of NOT gate (or inverter gate) by varying the input switch
position and observing the corresponding output LED status.
b) Study of Schmitt trigger characteristics: For this connect the circuit as shown in Fig b (2). Connect the input
(pin no 1) to a source of input voltage through a 25 K potentiometer and the output (pin no 2) to one output point of the
CDS. Now measure the input voltages at pin no 1 (or at the variable point of the potentiometer) and also measure the
corresponding output voltages at the output points (to which pin no 2 is connected) by using a digital voltmeter first by
varying the input voltage gradually between 0V to 5V and then vary the input voltage between 5V to 0V. Now make a
table showing the different input voltages and the corresponding output voltages in two different columns. From this table
of data plot the Schmitt trigger characteristics by plotting Vin along the X- axis and Vout along Y-axis. From this
characteristics find the VUT and VLT the upper trip and lower trip point and hence determine the hysterisis voltage is
given by: VH = VUT – VLT.
c) Converting a Sine wave into Square wave by using Schmitt trigger inverter IC 7414: For this connect
the circuit as shown in Fig b (3). Apply the Sine wave from the point marked high on the CDS to pin no 1 and connect the
output pin no 2 to one Y input of a CRO. Connect pin no 14 and pin no 7 to Vcc = 5V and GND respectively. If double
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beam CRO is available then connect the input and output points of 7414 IC to the Y1 and Y2 channel inputs of the double
beam CRO. Observe the output waveform on the CRO which will be a square wave, this may require little adjustment of
the amplitude of the Sine wave and adjustment of the CRO time base and voltage/ division switch. Observe also the input
waveform on the CRO. By observing the input and output on a dual beam CRO it is clear that the input and output
frequencies are equal.
C. Study of 555 Timer IC:
a) Study of 555 Timer IC in astable mode: For this connect the circuit as shown in Fig c (1). Use RA = RB = B

10KΩ. Use a dual beam CRO to connect the output pin no 6 and pin no 3 to two different channels of a dual beam CRO.
Now at pin no 6 observe the continuous charging and discharging waveform and at pin no 3 observe the unsymmetrical
square wave or astable waveform. From this observation verify that when capacitor is charging output at pin 3 is high and
when capacitor is discharging the output at pin no 3 is low. By observing the output waveform on a CRO at pin no 3 find
the duty cycle and frequency of the unsymmetrical square wave by measuring the TON and TOFF. Also find the duty cycle
and frequency of the unsymmetrical waveform from analytical expressions for the On and Off period of the square wave
which are given by: TOn = 0.693(RA + RB) C and TOff = 0.693RBC respectively. Comment on the difference in the
B B

measured values of the duty cycle and frequency of the square wave by the above two methods. How would you modify
the circuit of Fig c (1) to get symmetrical square wave at the output pin 3.
b) Study of 555 Timer IC in monostable mode: For this connect the circuit as shown in Fig c (2). Use R =
100KΩ and C = 100μf. Now connect the TRG (the trigger input) input to one input switch of the CDS. Connect the
output (pin no 3) to one LED of the CDS. Now observe that when the trigger input at pin no 2 is high the output LED will
not glow which implies that the output remains at low stable state. When the trigger input at pin no 2 is switched from
HIGH → LOW → HIGH state the output LED at pin no 3 glows for some time and again becomes off after some specific
time until the next negative going trigger comes. The duration over which LED connected at pin no 3 remains glowing is
the duration of the quasistable state. Note the duration in seconds of the quasistable state by using your wrist watch. Also
observe that how the duration of this quasi stable state can be changed by varying the time constant (RC) of the
monostable circuit i.e. either by varying the value of R or C. This verify the function of 555 Timer IC as a monostable
multivibrator.
D. Study of 4- bit Universal Shift Register IC 74194:
a) To verify all basic operations of shift register using 4 –bit Universal shift register IC 74194 connect
the circuit as shown in fig d (1). Connect inputs ⎯CLR, S1, S0, SL and SR to five input switches. Connect four outputs
QA(LSB output), QB, QC and QD(MSB output) to four output LED’s of the CDS. Connect the four parallel inputs
B

A=1(A=LSB), B=0, C=1 and D=1(D=MSB). Connect pin no 16 and pin no 8 to Vcc = 5V and GND respectively for all
the circuit of Fig d (1) to Fig d (3). Apply clock input to pin no 11 of 74194 from the TTL clock output of CDS. Now
varying the five input switch position and observing the status of four output LED’s verify the function table- 2 for 74194
IC.

Function Table – 2

CLR S1 S0 SL SR A B C D QA QB B QC QD Mode of operation

0 × × × × × × × × 0 0 0 0 ⇒ Master Reset.
1 1 1 × × 1 0 1 1 1 0 1 1 ⇒ Parallel Load.
1 0 1 × 0 × × × × 0 QA QB B QC ⇒ Right shift operation.

1 0 1 × 1 × × × × 1 0 QA QB B
⇒ Right shift operation.

1 1 0 0 × × × × × QB B QC QD 0 ⇒ Left shift operation.

1 1 0 1 × × × × × QB B QC 0 1 ⇒ Left shift operation.

1 0 0 × × × × × × Output at previous state. ⇒ Output Hold i.e. No

change.
b) Use of 74194 to realise rotate right operation or to realise 4 bit Ring counter: For this connect the
circuit as shown in Fig d (2). Load initially the four output QA (LSB), QB, QC and QD (MSB) as 1000 by applying A = 1, B
B

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 = 0, C = 0 and D = 0 at the four parallel inputs of the shift register and use ⎯CLR = 1, S1 = 0 and S0 = 1 for right shift
operation and apply the clock from TTL clock output of CDS to the clock input (pin no 11) of 74194 IC. Observing the
change in the four output LED’s connected to QA (LSB), QB, QC and QD (MSB) verify the rotate right operation (from QA B

towards QD) or ring counter sequence with the arrival of each clock pulse.
c) To use 74194 to realise rotate left operation: For this connect the circuit as shown in Fig d (3). Load initially
the four output QA (LSB), QB, QC and QD (MSB) as 1000 by applying A = 1, B = 0, C = 0 and D = 0 at the four parallel
B

inputs of the shift register and use ⎯CLR = 1, S1 = 1 and S0 = 0 for left shift operation and apply the clock from TTL
clock output of CDS to the clock input (pin no 11) of 74194 IC. Observing the change in the four output LED’s connected
to QA(LSB), QB, QC and QD(MSB) verify the rotate left operation ( from QD towards QA) with the arrival of each clock
B

pulse.
Note: For experiment with 74194 it is better to use the slower TTL clock pulse (of frequency 0.1 Hz) of the CDS. NG ⇒ LED not
glow. CDS ⇒ Component Development System.
CIRCUIT DIAGRAMS FOR EXPERIMENT NO - 7
Vcc = 5V
16 O1 5
Vcc O1
8 O2 7
GND O2 U?A U?A
2 9 O3 Vin Vout Vin
CS O3 1 2 1 2
3 11
ST ST Vout
S1 WE O4 O4 S1 M?
74189
S2 1 4 0
A0 D1 7414 7414
S3 15
A1 D2
6 1 Schmitt Trigger as inverter V t
u
S4 14
A2 D3
10 1 Fig b (1) Vin V o
V
S5 13 12 0
A3 D4 Vcc = 5V
Study of 74189 (16*4 bit) RAM Fig b (2)
Fig (a ) Circuit for Schmitt Trigger charateristics
Vcc = 5V Vcc = 5V

4 8
4 8 RA=10K K
R V
c
0
R V S c
555 TTIMER IC
0
Vin S c
c 1
1 2 555 TTIMER IC 3 =
ST Vout 3 OUT 7 R
OUT RB=10K Vout DIS
Vout 7
DIS 2
7414 TRG
SIGNAL AC 2
TRG 5 6
5 6 CV THR Vc
CV THR Vc G
Sine wave to square wave converter G N
D S1 C 100μf
using ST circuit N
D C 0.1μ f C1 0.01μf
Fig b (3) C1 0.01μf 1
1
Fig c (1) Fig c (2) Vtrg
555 TIMER IN ASTABLE MODE 555 TIMER IN MONOSTABLE MODE
1 1 1 1 1 1 1 1
5 4 3 2 5 4 3 2
QQQQ
A B C74194
D
U1 QQQQ
A B C74194
D
U1 Fig (a)
1 1 1 1
5 4 3 2
C C C C
S L S L S L S L U1
RA B CD S
L K S
0 1 R R A B CD S
L K S
0 1 R
QQQQ
A B C74194
D

2 3 4 5 6 7 1 9 1 1 2 3 4 5 6 7 1 9 1 1 C C
1 0 1 0 S L S L
S5 S4 S3 S2S1 RA B CD S
L K S
0 1 R
NC S3 S2S1

1011 CP 1000 CP 2 3 4 5 6 7 1 9 1 1
1 0
Study of Universal Shift Register IC 74194 Rotate right with 74194 IC ( Ring Counter ) S3 S2S1
NC
Fig d (3)
Fig d (1) Fig d (2) 1011 CP
Rotate left operation using 74194 IC

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 EXPERIMENT NO: -8
A. Study of 4-bit Arithmetic and Logic Unit (Using 74181 IC): To realise different logical and arithmetic operations using 74181 IC,
(a 4 - bit ALU chip) connect the circuit as shown in Fig (a). Apply the 4 bit number A = (3)10 (i.e. connect A3 = A2 = 0(logical 0)
and A1 = A0 =1( logical 1 or NC)). Apply the 4 bit number B = (4)10 ( i.e. connect B3 = B1 = B0 = 0(logical 0) and B2 = 1( logical 1
B

or NC)). Connect the input carry CN0 = 1 or 0 (for testing arithmetic operations). Connect the four select inputs S3, S2, S1, S0 and
M (the mode control input) to five input switches as shown in fig (a). Connect the four function outputs F3, F2, F1, F0 and the carry
output CN+4 to five output LED’s of the CDS. Now keeping M=1, varying the select inputs verify the different logical operations as
given in function table – 1. Note that the output LED connected to CN+4 output remains always glowing for all possible values of
the select inputs as logical operations between A and B does not produce any carry. Now by making M = 0, and connecting CN = 1
or 0 verify the different arithmetic operations for different possible values of the select inputs according to the function table – 1.
Note the changes in the carry output LED status (connected at CN+4 output) for different arithmetic operation with and without
carry. Connect pin no 24 and pin no 12 to Vcc = 5V and GND respectively.

Function Table – 1 for 74181 ALU chip.

Select inputs M=1 M=0 and CN = 1 M = 0 and CN = 0
(Logical operations) (Arithmetic operations) (Arithmetic operations)
Function output Function output CN+4 Function Output CN+4
0 0 0 0 ⎯A A A Plus 1
_____
0 0 0 1 (A+B) A+B ( A + B ) Plus 1

0 0 1 0 ⎯A⋅B A+⎯B ( A + ⎯B ) Plus 1

0 0 1 1 0 Minus 1(2’s Compl) Zero
___
0 1 0 0 A⋅B A Plus A⋅⎯B A Plus A⋅⎯B Plus 1

0 1 0 1 ⎯B (A+B) Plus A⋅⎯B (A+B) Plus A⋅⎯B Plus 1

0 1 1 0 A⊕B A Minus B Minus 1 A Minus B

0 1 1 1 A⎯B A⋅⎯B Minus 1 A⋅⎯B
1 0 0 0 ⎯A+B A Plus A⋅B A Plus A⋅B Plus 1
_____
1 0 0 1 A⊕B A Plus B A Plus B Plus 1
1 0 1 0 B (A+⎯B) Plus A⋅B (A+⎯B) Plus A⋅B Plus 1
1 0 1 1 A⋅B A⋅B Minus 1 A⋅B
1 1 0 0 1 A Plus A A Plus A Plus 1
1 1 0 1 A+⎯B ( A + B ) Plus A (A+B) Plus A Plus 1
1 1 1 0 A+B ( A + ⎯B ) Plus A (A+⎯B) Plus A Plus 1
1 1 1 1 A A Minus 1
A
Note: Plus ⇒ Arithmetic addition. Minus ⇒ Arithmetic subtraction.

B. Study of 8-bit Microprocessor compatible D/A converter using DAC0800/MC1408 IC in unipolar mode: To study the
characteristics of 8-bit DAC using DAC0800/MC1408 IC in unipolar mode, connect the circuit as shown in Fig (b). Connect the
three MSB inputs D7, D6, and D5 to GND (i.e. pin no 5, 6 and 7 are connected to GND) and the remaining five inputs D4, D3, D2, D1
and D0 (i.e. pin no 8, 9, 10, 11 and 12) are connected through five input switches. The circuit of Fig (b) gives the unipolar
configuration of the D/A converter IC. Short circuit the GND point of ± 15V power supply with the GND point of 5V power
supply to have a common ground. Now by varying the five digital inputs by varying the five switch position measure the
corresponding analog output voltage for each digital input by using a digital voltmeter connected between pin no 6 (the output of
op-amp) and the GND. Now by connecting the three MSB inputs to logical 1 voltage (i.e. connecting D7, D6, and D5 to logical 1
voltage) and all five input switch connected to logical 1 position measure the maximum analog output voltage of the DAC0808
between pin no 6 (the output of op-amp) and the GND. Analog voltage Va (t) so obtained will vary from 0V to 10V i.e. 0V≤ Va (t)
≤10V (in unipolar mode. Now plot a curve between the digital inputs (plotted along x-axis) and the corresponding analog output
voltages (plotted along y-axis) to get the D/A converter characteristics for unipolar DAC.

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C. Study of 8-bit Microprocessor compatible D/A converter using DAC0800/MC1408 IC in bipolar mode: To study the
characteristics of 8-bit DAC using DAC0800/MC1408 IC in bipolar mode, connect the circuit as shown in Fig (c). By varying the
digital inputs in the same manner as above note the corresponding analog output voltage Va (t) by using a digital voltmeter
connected between the output pin 6 of 741 op-amp and the GND. Verify that the analog output voltage for bipolar mode varies
between – 5V to 5V i.e. –5V ≤ Va(t) ≤ 5V. Now plot a curve between the digital inputs (plotted along x-axis) and the
corresponding analog output voltages (plotted along y-axis) to get the D/A converter characteristics for bipolar DAC.

CIRCUIT DIGRAMS FOR EXPERIMENT NO - 8

Vcc = 5V
U?
A0 2 9 F0
23 A0 F0 10 (MSB) DAC0808/MC1408 Vref = 5V
A1 A1 F1 F1
A2 21 11 F2 5 13 Vcc = 15V
19 A2 F2 13 D7 Vcc R14 = 2.5K
A3 A3 F3 F3 6 14
1 D6 Vref 1
B0 B0
B1 22 S 7 15
20 B1 D5 Vref 2
B2 B2 T
B3 18
B3 U S5 8
D4
R15 = 2.5K
A=B
14 NC P 7 1
CN 7
CN CN+4
16 CN4 N S4 9 4 3
+
G
17 NC I D3 I0 6 Va (t)
6 15 10 2 741
S0 S0 P NC S3 D2 -
S1 5 ANALOG OUTPUT
S2 4 S1 L 11 16
3 S2 A S2 D1 CAP
S3 S3 T VOLTAGE
M 8 I S1 12 G G 4 5
M D0 V
G N
D
N
D
e
e
74181 I (LSB)
D Vcc = - 15V
STUDY OF 4 BIT ALU USING 74181IC 1 2 3
C=22PF R = 5K
Fig (a)

Vcc = 5V Vcc = - 15V

UNIPOLAR CONFIGURATION OF 8 BIT DAC0808/MC1408
(MSB) DAC0808/MC1408 Vref = 5V
Fig (b)
5 13 Vcc = 15V
D7 Vcc R14 = 2.5K
6 14
D6 Vref 1
7 15
S D5 Vref 2
T
U S5 8
D4
R15 = 2.5K
P K 7 1
N S4 9
D3 I0
4 5
= 3
+
I R
741
6 Va (t)
S3 10 2
D2 -
L 11 16
ANALOG OUTPUT
A S2 D1 CAP
T 12
VOLTAGE
I S1 D0 G
N
G
N V
4 5
G D D
e
e
I (LSB)
D Vcc = - 15V
1 2 3
C=22PF R = 5K

Vcc = - 15V
BIPOLAR CONFIGURATION OF 8 BIT DAC0808/MC1408
Fig (c)

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