CE222_Slides1
CE222_Slides1
Salman Ashraf
Peripheral devices
Central Main
Processing Memory
Unit
Computer
Systems
Interconnection
Input
Output
Communication
Lines for external
environment
STRUCTURE - THE CPU
Structural Organization of CPU
Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Interconnection
Internal CPU
Memory Interconnection
Control
Unit
STRUCTURE - THE CONTROL UNIT
Structural Components of Control Unit
CPU
Sequencing
ALU Logic
Internal Control
Unit
Bus
Control Unit
Registers Registers and
Decoders
Control
Memory
THE VON NEUMANN ARCHITECTURE
MAR
– Registers may also be represented showing the bits of data they contain
DESIGNATION OF REGISTERS
• Designation of a register
- a register
- portion of a register
- a bit of a register
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits in a 16-bit register Subfields
BASIC SYMBOLS FOR REGISTER TRANSFERS
R2 R1
R2 R1
– the data lines from the source register (R1) to the destination
register (R2)
– Parallel load capability at destination register (R2)
– Control lines to perform the action