Performance Improvement Techniques for

High-Speed Dynamic Latch Comparator at

45nm Technology Node

Ekansh Jindal1,2 , Divya Singh1,3 , Charu Kumar1,4 , and Poornima Mittal1,5

1
Delhi Technological University, New Delhi, 110042, India
2
[email protected]
3
[email protected]
4
[email protected]
5
[email protected]

Abstract. This paper examines three improvements made to a dynamic

bias latch type comparator at a 45-nm technology node: tail-enhancing
latch, modifying latch, and three-tail architecture. Extensive simulations
show that the time delay is significantly reduced. When operating at
low voltage, this decrease ranges from a minimum of 36.67% to a high
of 82.99%. Conversely, the findings show a drop at higher voltage levels
that ranges from a minimum of 24.53% to a maximum of 59.99%. This
illustrates the reduced time delay achieved by the modified dynamic bias
latch type comparator. Fast and precise analog-to-digital conversion is
essential for real-time data processing, and high-speed dynamic latch
comparators are essential for the Internet of Things, edge computing, and
autonomous systems. They guarantee safety and efficiency by improving
network responsiveness in the Internet of Things applications, lowering
latency in edge computing, and enabling split-second decision-making in
autonomous systems.

Keywords: Dynamic Bias Comparator, Analog-to-Digital Converter (ADC),

Successive Approximation Register (SAR), Comparator Propagation De-
lay

1 Introduction

In the current high-tech era, the introduction of high-speed, low-power analog-

to-digital converters (ADCs) has completely changed the electronic device land-
scape. These complex converters are essential in many different applications, but
they are particularly important in the field of mobile devices, where digital signal
processing must be done seamlessly. Comparators are the core building blocks
of analog-to-digital converters (ADCs), and they have developed into essential
parts [16].
Because they can deliver fast and accurate analog-to-digital conversion, high-
speed dynamic latch comparators are critical to developing technologies such as
2 Ekansh Jindal et al.

edge computing, autonomous systems, and the Internet of Things. These tech-
nologies require real-time processing of data streams for timely decision-making
and response. High-speed comparators facilitate fast sensor data analysis in
Internet of Things applications, enhancing network responsiveness. Fast com-
parators also lower latency in edge computing, improving system performance.
Exploring methods to improve dynamic bias latch comparators’ performance is
driven by the growing need in contemporary electronic systems for fast and ef-
fective analog-to-digital conversion, especially in edge computing, autonomous
systems, and Internet of Things applications. By lowering propagation delays
and improving comparator design, these techniques seek to enhance the ADC’s
performance and enable quicker and more precise data processing. This work
advances electronic systems generally by encouraging innovation in ADC tech-
nology and satisfying specific application needs. In response to these require-
ments, several comparators have been developed, each employing a unique design
methodology. With developments in big data, cloud computing, and computer
vision interacting with the creation of analog-to-digital conversion technologies,
this diversity demonstrates how the technological environment is always evolving
[1].
SAR ADCs have an Input Sample and Hold (SHA) function that keeps the
signal stable throughout the conversion. SAR ADC utilizes the Binary Search
algorithm which reduces the time complexity. It uses a successive approximation
register instead of a counter which is used by other ADCs. As a result, SAR
ADCs show superior performance in terms of complexity, power dissipation and
propagation delay [19].
The dynamic bias latch type comparator is crucial in achieving high-speed
signal processing [5, 13]. This paper aims to improve the dynamic bias latch type
comparator by using three different optimization strategies: tail-enhancing, latch
modification, and triple-tail architecture [10]. The research will concentrate on
minimizing propagation latency. By strategically implementing these optimiza-
tion strategies, the paper aims to not only reduce propagation delay but also
advance the overall performance of the dynamic bias latch type comparator [6,
20]. The rest of the paper is structured in the following manner: A literature
review of the existing comparator architectures like Elzakker and Dynamic Bias
Latch Type is discussed in Section 2, followed by Section 3 which describes the
working of Dynamic Bias Latch-Type comparator. Section 4 investigates dif-
ferent performance improvement techniques. A performance comparison of the
proposed techniques is included in Section 5.

2 Literature Review

T. Kobayashi et al. used 0.7µm double-polysilicon/double-metal CMOS tech-

nology with five NMOS and four PMOS transistors to introduce an effective
and economical ARM latch comparator in 1992 [8]. A/D converters, wireline
receivers, and memory bit-line detectors are among of its uses.
 Techniques for High-Speed Dynamic Latch Comparator 3

Later, to improve common-mode rejection and lower offset voltages, a double-

tail latch-type design was added, which helped low-voltage operations [3]. Its ap-
plicability for low-power applications was limited, though, by the pre-amplifier
and regenerative latch operating simultaneously, which made it difficult to op-
timize energy usage for a given SNR. In order to overcome these problems,
the Modified Double Tail Comparator added two control transistors that were
cross-coupled to enhance positive feedback during regeneration and lower power
consumption without making the device more complicated.
The success of an energy-conserving SAR ADC is largely dependent on the ef-
ficiency of its comparator. In an effort to conserve power, dynamic pre-amplifiers
are gaining increasing popularity. In the evolution of dynamic comparator de-
signs, Elzakkar implemented notable alterations to the 2-stage dynamic com-
parator, a design initially presented by Schinkel et al.[14, 7]. These modifications
were aimed at achieving an enhanced gain and a reduction in comparator noise
and offset. The Elzakkar comparator achieved a reduction in energy consump-
tion by lowering the initialization energy of the pre-amplifier stage. Instead of
charging the pre-amplifier capacitors to the full supply, they are powered to only
half the supply, resulting in a 50% energy saving.
Drawing inspiration from Elzakkar’s comparator, Harijot Singh Bindra pro-
posed a novel comparator design in 2018. This design, characterized by dynamic
biasing and the inclusion of a tail capacitor, was aimed at reducing both energy
consumption and delay [4].In the comparator employing dynamic bias, the ini-
tial current in the tail is lower and experiences a significant reduction compared
to Elzakkar’s comparator after the response. As a consequence, this results in
a multiple-fold decrease in power consumption. This innovative approach has
significantly contributed to the advancements in the field of SAR ADCs.

3 Dynamic Bias Latch-Type Comparator

In the Dynamic Bias Circuit, as depicted in Figure 1(a), a sequence of events is

triggered when the clock signal is in a low state. During this phase, transistors
P5 and P6 are brought into action, which results in Fp and Fn reaching the
voltage level of VDD . This action initiates the charging process for capacitors C1
and C2. Due to this, transistors P3 and P4 are deactivated by Fp and Fn.
In parallel to these events, N1 and N4 are activated, which leads to the dis-
charge of OUTN and OUTP to a zero level. This discharge process, in turn,
activates transistors P1 and P2. As the clock transitions to active state tran-
sistors P5, P6, N1, and N4 are deactivated, while N7 is activated. This change
in the state of the transistors leads to the commencement of the discharging
process for capacitors C1 and C2. During this phase, if INP exceeds INN, Fp
and C1 discharge at a faster rate. This rapid discharge activates P3 and charges
OUTN to VDD before OUTP, resulting in OUTN exceeding OUTP, as shown in
Figure 1(b).
The circuit also includes an additional tail transistor, N8, which plays a
crucial role in preventing unnecessary charging. N8 takes an inverted clock signal
4 Ekansh Jindal et al.

(a) (b)

Fig. 1. Dynamic Bias Latch-Type Comparator (a) Schematic Diagram (b) Transient
Analysis for VDD = 1 V

as input and is coupled with a 20F capacitor, C3. For example, in the above
scenario where INP exceeds INN, Fp and C1 discharge more rapidly. However,
instead of discharging the capacitor to zero, the charge is distributed between
C1 and C3. This distribution of charge reduces the delay in the next cycle when
the clock switches. This mechanism, facilitated by N8, contributes significantly
to the reduction of both static and dynamic power. This efficient design of the
Dynamic Bias Circuit ensures optimal performance and power management.

4 Performance Improvement Techniques for Dynamic

Bias Latch-Type Comparator

In advancing dynamic bias comparators, circuit delay has been significantly re-
duced through three key enhancements. Firstly, a clock-driven tail has been inte-
grated which will enhance the circuit’s slewing rate, augment the current flowing
through the circuit, and optimize the biasing condition of the circuit. Secondly,
a transition from a two-stage to a three-stage architecture, with an added am-
plifier, refines transitional dynamics for improved sensitivity. This helps in the
independent optimization of each stage. Lastly, the latch circuit has been inno-
vatively modified, departing from conventional design to optimize performance.
These enhancements collectively elevate the dynamic bias comparator’s speed,
accuracy, and reliability, aligning it with evolving demands in integrated circuit
design.
 Techniques for High-Speed Dynamic Latch Comparator 5

4.1 Dynamic Bias Comparator using Tail Transistor

As illustrated in Figure 2, introducing a tail with a clock signal as an input pro-
duced a significant reduction in delay. The width (W) and length (L) parameters

Fig. 2. Schematic Diagram of Dynamic Bias Comparator using Tail Transistor

were configured at 1.8µm and 45nm, respectively, with a total of 15 transistors

employed— one more than in the dynamic bias configuration. The inclusion of
a tail transistor offers several advantages, enhancing the circuit’s slewing rate,
which in turn contributes to a decrease in propagation delay. Additionally, it
aids in augmenting the current flowing through the circuit, with the tail current
playing an essential role in establishing the operating point and influencing the
gain and speed of the circuit in a differential pair [3]. A higher current facilitates
faster charging and discharging of nodes, ultimately reducing overall delay[11,
15]. The tail transistor assists in optimizing the biasing conditions of the circuit.
Proper biasing ensures that the transistors are operating in their active region,
maximizing their speed and efficiency.

4.2 Dynamic Bias Comparator using Triple-Tail Dynamic

Architecture
Figure 3 presents the diagram of the second proposed circuit, characterized by
its multi-stage architecture. The circuit integrates a triple tail technique within
the comparator. Input from the Fn and Fp nodes of the first pre-amplifier is
supplied to the second, and its ensuing output is directed to the latch.
The inherent advantage of this multi-stage configuration lies in its capacity
for independent optimization at each stage. It is imperative to acknowledge
that the introduction of the triple tail structure contributes to elevated energy
consumption relative to the conventional comparator. This heightened energy
demand, however, is counterbalanced by a noteworthy reduction in delay [12,
6 Ekansh Jindal et al.

Fig. 3. Schematic Diagram of Dynamic Bias Comparator using Triple-Tail Dynamic

Architecture

21]. The trade-off between increased energy consumption and diminished delay
underscores the intricate design considerations and trade-offs inherent in the
proposed circuit, reinforcing its potential for enhancing performance in specific
applications[9].

4.3 Dynamic Bias Comparator using Modified Latch

Figure 4 illustrates the schematic of the third proposed circuit. During a low clock
state, transistors P1 and N7 are turned off, while P4, P5, and N8 are turned on.
Consequently, nodes Fn and Fp, along with capacitors C1 and C2, begin charging
to VDD . This action activates N1 and N4, establishing a discharging path for
OUTN and OUTP, leading to their discharge to the ground. Since OUTN and
OUTP serve as inputs to P2 and P3, these transistors are turned on.
Upon the clock transitioning to a high state, P1, and N7 are turned on, while
P4, P5, and N8 are turned off. As P2 and P3 are already activated, they charge
OUTP and OUTN to VDD , subsequently activating N2 and N3 and turning off
P2 and P3. With N1 and N2 activated, and N3 and N4 activated, OUTN and
OUTP commence discharging to the ground.
When input signals are applied and INP >INN, Fn discharges faster than Fp,
causing N1 to turn off. This results in the faster discharge of OUTP compared
to OUTN. When OUTP becomes 0, P2 is turned on, causing OUTN to become
VDD , thereby ensuring that OUTN>OUTP.
This circuit employs 13 transistors, a quantity lower than that in the con-
ventional design [18, 17]. There is a significant decrease in delay when compared
to the conventional design.
 Techniques for High-Speed Dynamic Latch Comparator 7

Fig. 4. Schematic Diagram of Dynamic Bias Comparator using Modified Latch

5 Performance Comparison of Proposed Techniques

The simulation results reveal key insights into the performance of different com-
parators, as depicted in Figure 5. In Figure 5(a), the time delay across various
VDD values shows a consistent increase in delay for all comparators as VDD in-
creases. Notably, the triple tail consistently exhibits the lowest delay, followed by
the tail-enhanced and modified latch. Figure 5(b) illustrates the Average Power
Dissipation across different VDD levels. An increase in VDD results in higher aver-
age power dissipation. The dynamic bias comparator consistently demonstrates
the lowest power dissipation, followed by tail enhanced, modified latch, and triple
tail. This graph demonstrates a contrasting trend to the delay graph due to the
necessity of maintaining a constant power delay product. Consequently, when
a comparator experiences a reduction in delay, its power will correspondingly
increase.
Moving to Figure 5(c), which represents Total Energy Dissipation, an in-
crease in VDD leads to higher total power dissipation for all comparators. In
Figure 5(d), depicting Static Power across varying VDD , dynamic bias exhibits
the least static power dissipation when VDD is less than or equal to 1. As VDD in-
creases, the triple tail starts showing the least static power dissipation, followed
by the modified latch, dynamic bias, and tail enhancement. Figure 5(e) focuses
on Dynamic Power Dissipation across different VDD values. Despite an increase
in dynamic power for dynamic bias with rising VDD , it consistently maintains
the least dynamic power dissipation among all comparators. Following dynamic
bias, tail enhanced, modified latch, and triple tail exhibit increasing dynamic
power dissipation.
Table 1 presents an exhaustive comparative analysis of crucial performance
metrics for four distinct variants of Dynamic Bias Comparators: namely, the Dy-
namic Bias Latch-Type Comparator, Tail-Enhanced, Triple-Tail Dynamic Archi-
tecture, and Modified Latch. This evaluation is conducted on a consistent 45 nm
CMOS technology platform, operating at a supply voltage of 1 V and a sam-
8 Ekansh Jindal et al.

(a) (b) (c)

(d) (e)

Fig. 5. Evaluating Comparator Architectures Across Varying Supply Voltages (VDD )

(a) Time Delay (b) Average Power Dissipation (c) Total Energy Dissipation (d) Static
Power Dissipation (e) Dynamic Power Dissipation

pling frequency of 0.125 GHz. Employing LTSpice software at a temperature of

27 ◦ C, the architectures undergo scrutiny across various critical parameters. All
the architectures are being designed using predictive technology model (PTM)
[2].
In the tail-enhanced configuration, an additional tail transistor was imple-
mented, effectively decreasing delay. Meanwhile, modifications in the latch design
involved optimizing the pre-amplifier with one less transistor compared to the
dynamic bias setup, resulting in a notable reduction in delay, as demonstrated
in Table 1. Both tail-enhanced and modified latch stages were maintained at
2. In the triple tail configuration, a new stage was introduced increasing the
number of transistors to 18. This strategic enhancement played a pivotal role in
substantially mitigating delays.
The time delay parameter reveals interesting insights into the efficiency of
these variants. Dynamic Bias Comparator exhibits a time delay of 237.091 ps,
while the Tail-Enhanced variant showcases a notable reduction by approximately
26.6%, registering at 173.922 ps. The Triple-Tail Dynamic Architecture out-
performs others, demonstrating a significant decrease of approximately 64.2%
compared to the Dynamic Bias Comparator, with a time delay of 84.7894 ps.
Similarly, the Modified Latch exhibits a time delay of 93.6379 ps, representing
a considerable reduction of 60.5% compared to the Dynamic Bias Comparator.
Moving on to total energy dissipation, the Dynamic Bias Comparator records
19.54 fJ, with the Tail-Enhanced variant experiencing an increase of approxi-
mately 73.4%, totaling 33.8667 fJ. The Triple-Tail Dynamic Architecture demon-
 Techniques for High-Speed Dynamic Latch Comparator 9

Table 1. Comparative Performance Analysis of Dynamic Bias Comparator Variants

at 45 nm CMOS technology node, VDD = 1 V, and temperature = 27 ◦ C

Parameters Dynamic Bias Tail-Enhanced Triple-Tail Modified Latch

Number of Transistors 14 15 18 13
Number of Stages 2 2 3 2
Sampling Freq. (GHz) 0.125 0.125 0.125 0.125
Time Delay (ps) 237.091 173.922 84.7894 93.6379
Total Energy (fJ) 19.54 33.8667 142.708 69.387
Average Power (µW) 2.4425 4.2333 17.8385 8.6734
Static Power (nW) 34.891 45.6 38.6923 43.4428
Dynamic Power (µW) 11.496 24.173 49.4023 31.1441
Power-Delay Product (aJ) 579.0948 736.2710 1512.5157 812.1571

strates a total energy dissipation of 142.708 fJ. While, the Modified Latch shows
a substantial increase of 254.4%, recording a total energy dissipation of 69.387
fJ.
Average power dissipation follows a similar trend, with Dynamic Bias Com-
parator manifesting 2.4425 µW. The Tail-Enhanced variant experiences an in-
crease of about 73.4%, totaling 4.2333 µW. Meanwhile, the Triple-Tail Dynamic
Architecture showcases a notable decrease of approximately 86.7%, registering at
17.8385 µW. The Modified Latch exhibits an increase of approximately 255.4%,
recording an average power dissipation of 8.6734 µW.
Considering static power dissipation, the Dynamic Bias Comparator incurs
34.891 nW, and the Tail-Enhanced variant experiences an increase of approxi-
mately 30.8%, totaling 45.6 nW. The Triple-Tail Dynamic Architecture records
a marginal decrease of approximately 11.2%, resulting in static power dissipation
of 38.6923 nW. The Modified Latch exhibits a slight increase of approximately
24.5%.
Table 1 illustrates that despite the variants exhibiting lower comparator de-
lay, the dynamic power consumption and power-delay product of the dynamic
bias latch-type comparator are the most optimal. Reducing the delay of a com-
parator circuit will lead to faster response times and improved performance in
applications where quick decision-making is crucial, such as in digital signal pro-
cessing, analog-to-digital conversion, and sensor interfaces. However, excessively
reducing the delay could potentially introduce issues such as increased power
consumption and higher noise sensitivity.

6 Conclusion

Simulations of four optimization techniques for the dynamic bias latch-type

comparator—tail-enhancing, modifying latch, and triple-tail architecture were
10 Ekansh Jindal et al.

carried out 45-nm technology node. Extensive modifications resulted in a signif-

icant decrease in time delay, ranging from a minimum of 34.69% to a maximum
of 82.99%, under low voltage conditions. Conversely, at higher voltage levels,
the outcomes demonstrate a reduction ranging from a minimum of 24.53% to a
maximum of 59.99%. Notably, simulations revealed the modified latch’s superior
performance with a 26.83% reduction in Power Delay Product at a low voltage
level, underscoring its efficiency in power consumption and delay. The Power De-
lay Product, indicative of the trade-off between power consumption and delay,
holds paramount importance in optimizing integrated circuits for energy effi-
ciency. The research’s optimized comparator designs hold promise for industries
reliant on high-speed analog-to-digital conversion, including telecommunications
and automotive systems. Future developments in comparator design can address
challenges such as power consumption and noise immunity, potentially through
novel circuit architectures or adaptive power management techniques. Efforts to
enhance noise immunity and ensure robust performance in noisy environments
are crucial for advancing high-speed comparator designs, making them suitable
for diverse industry applications.

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