Unit 3.

Digital systems

Computer Structure
E.T.S.I. Informática
Universidad de Sevilla

Jorge Juan-Chico <[email protected]> 2021-2024

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 Contents
●
Digital circuits vs digital systems
●
Digital systems design overview
●
Data unit design
●
Control unit design
●
Verilog modelling and test
●
Top-level system design and FPGA implementation
●
Working examples:
– Working example 1: RPN simple calculator (complete design)
– Working example 2: 3-register stack RPN calculator (specification)

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 Bibliography
●
CED Unit 3.5. Hardware description languages. In ev.us.es.
– Introduction to Verilog.
– Verilog coding videos.
●
verilog-course.v
– General Verilog examples, specially units 5 to 8: ALU, FSM, edge
detectors, ROM and RAM.
●
Verilog HDL Quick Reference Guide. Stuart Sutherland, 2001
– General Verilog reference, syntax, formats, etc.

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 Digital circuits vs digital systems
●
Signals
Can be a single FSM?
– clk: ~50Mhz
– open: button, 1 when pressed
– gate: 0-close, 1-open
– finished: 1 when completely
open/closed
– obs: 0 when there is an
obstacle
●
Operation
– Open the gate for 10s when
the open button is pressed
The system is not feasible with just a FSM – Close automatically
because it has to count 500000000 cycles! – The system should be safe

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Digital circuits vs digital systems
●
Introduce a counter as a helper
module.
●
Is the complexity of the control
unit reduced?
– No need to count.
– Need to control the counter.
●
Next steps
– Define the counter behavior
and implement it (we already
know that).
– Design the FSM.

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Digital circuits vs digital systems
●
Counter:
– enable: count.
– clear: reset to initial value.
– eoc: end of count.
– Modulus: 10x50000000.
●
FSM:
– 5 inputs (2^5 combinations).
– 3 outputs.
– We will learn how to describe
complex FSMs.
●
Solution:
– Lab exercise.

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 Digital circuits vs digital systems
●
Limitations of circuit-level thinking
– Complex problems are difficult to solve just by combining digital blocks.
We need higher-level abstraction.
●
Digital systems abstraction
– Think on data words more than on individual bits.
– Building blocks are data processing elements: registers, counters, ALU,
converters, etc.
●
Register-Transfer Level (RTL) description.
– FSMs are used to control the data processing units.
– Do it recursively: a very complex digital system can use other digital
systems as building blocks.
●
Representation
– RTL notation more than logic expressions.
– More powerful FSM representation (will see later).

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 Digital systems design overview
Specification. Describe the system’s required
operation and interface.

RTL design. Block interconnection and FSM

description: registers, counters, ALU, etc. module calculator (
input ...
- Traditional: pen and paper. output ...
);
- Modern: HDL description from block diagram.
always @(posedge clk)
...

Logic-level design. Low-level description using

basic elements: gates, FF, FA, HA, etc. x3 x2 x1 x0

CL

- Traditional: pen and paper.

CL
LD
REG
q A B
CK CL CL
J1 q1 J2 q2
x
n n
- Modern: automatic logic synthesis from HDL.
z3 z2 z1 z0
K1 K2

s[2:0] ALU v z

3 clk

Implementation. Technology mapping to a

particular hardware platform.
- Traditional: PCB + SSI chips.
- Modern: automatic technology mapping to ASIC
or FPGA.

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Digital system design overview
Control/data unit abstraction

The data unit includes the processing elements needed by the system: registers, counters,
ALUs, etc. and an interconnection system.
The control unit organize the activation of control signals to the elements of the data unit to
accomplish some task or group of tasks: implement a control algorithm, do some complex
calculation, execute a program (in computers).

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Digital system design overview
Control/data unit abstraction

Complex systems may be split in various, interconnected digital system.

Eg: modern computers include several digital systems, some of them are computers
themselves.

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 Digital system design overview
Macro-operation vs micro-operation
●
Macro-operation (macro-instruction or instruction)
– Each task the system cam perform automatically.
– In general, several clock cycles may be needed to complete a macro-
operation.
– In each clock cycle, some operations are carried out by the data
processing elements.
– The control unit determines which operations are done in each clock
cycle to complete the macro-operation.
●
Micro-operation
– Each operation that is carried out in one clock cycle as part of the
execution of a macro-operation.
– One micro-instruction may involve various processing elements.

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 Digital system design overview
Methodology
1. Start with a clear specification of the system:
• Input/output signals and expected operation
• Definition of the macro-operations (instructions) the system has to
perform.
2. Design a data unit that can perform all the basic data processing
operations needed by the macro-operations.
• It involves defining the data processing elements and the way they are
interconnected.
3. Calculate the micro-operations needed to execute each macro-
operation.
4. Design a FSM that controls the sequencing of micro-operations.
5. Describe the system using a HDL. Write a test bench and simulate it.
6. Add additional connections, interfaces and/or peripherals and
implement in in a chip (e.g. FPGA).

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 Register-Transfer (RT) notation
●
Used to represent multi-bit data assignment (like the contents of
registers and counters).
Type Operators Function Examples Verilog ex.
If the (optional) condition C is met,
the value of <expr> is stored in Q←Q+A q <= q + a;
Sequential
C: A←<expr> register A; if not, A keeps its current W A: A ← X If (wa)
assignment
stored value. Storage takes place a <= x;
with the active clock edge.
If the (optional) condition C is met,
the value of signal A at each assign a = b + c;
Combinational A=B+C
C: A = <expr> moment is obtained by evaluating assign dout =
assignment OE: Dout = X
<expr>; if not, A remains oe == 0 ? x : ‘z;
unassigned (typically in HI state).
A=B*C a = b * c;
Arithmetic +, -, *, /, ... Arithmetic operations
CNT ← CNT+1 cnt <= cnt + 1;
Logic &, |, ^, , ... Bitwise logic operations A=B&C a = b & ~c;
SHL(A,b) A is shifted one bit. The new bit is Q ← SHL(Q,0)
Shift Z = SHR(X,XR) q <= q << 1;
SHR(A,b) taken from 'b'.
Bit selection A[i], Ai i-th bit in A is selected. Z = B3 z = b[3];
Bit range A[i..j], Ai..j B = Q7..4
Bits from i-th to j-th are selected. b = q[7:4];
selection
The bits of two words are chained A ← {B,C} a <= {b,c};
Chain {A,B} D = {A ,B }
together to form a larger word. 3..0 7..4 d = {a[3:0],b[7:4]};
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 Simple calculator
Specification
Simple calculator
We want to build a calculator with the inputs and outputs in the diagram.
●
A and B are the contents of two internal registers.
●
“din” is a data input.
●
“reset” takes the calculator to the initial state. In this state, ready=1 and the calculator is ready to
start a new operation.
●
The operation is selected by “op” (see the table).
●
“start” starts the operation selected by “op”.
●
When the operation finishes the calculator goes back to the initial state.
Design and implement the calculator in a Digilent’s Basys2 FPGA development board.

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Simple calculator
Specification

start

op din reset

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 Data unit design
●
Specification
The DU must have enough building blocks to
– We start with the list of macro-operations perform all required macro-operations, and an
that the system needs to perform. interconnection system that can make all needed
data transfers.
●
Building blocks
– Registers: store data. May do some The same system can be implemented with
different data units.
processing: shifting, etc.
– Counters: measure time, perform
Compromise:
repetitions, etc.
- Performance: do macro-operations in as fewer
– ALU: processes data. The core of the steps as possible.
data unit in computers. - Cost: use as fewer blocks as possible.
- Cost: use a simple interconnection.
●
Interconnection - Power consumption?
– Routes data from one device to another. - Robustness?
– Buses: connection lines shared by
various devices.
– Multiplexers: select data coming from
various devices.

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 Data unit design
Register interface
Independent I/O ports Independent I/O ports
Bi-directional port
(unconditional output) (tri-state output)

Registers may have more than one or two ports.

Tri-state output and bidirectional output can be easily implemented
outside the register.
Moderns standard digital design avoids tri-state signals (thus tri-state
and bi-directional ports).

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 Data unit design
Register interface
Example 1
Design a bidirectional port register using a register with independent input and
output ports and tri-state buffers.

If the register and the buffer are in the same chip,

there is no difference with a tri-state output register.
This is how these registers are made.

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Data unit design. Interconnection
Shared vs dedicated buses
Dedicated bus Shared bus

Buses can be dedicated: connect just two devices, but most of the
time we use “bus” to refer to shared connections among various
devices.
Shared buses save resources but reduce performance.
Modern systems tend to use more and more dedicated buses.

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Data unit design. Interconnection
Shared input bus (multi-drop bus)

Register (or other devices) inputs are all connected to the same bus.
Any register can be the destination of the data in the bus.
A control signal in the register (eg. write enable) makes the desired
register to load the data.
Drawback: different registers cannot be written with different data at
the same time.

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 Data unit design. Interconnection
Shared output bus with tri-state registers

Bidirectional
connection

Only one register can be read to the bus at a given time, so all
registers need to be able to disconnect from the bus (tri-state
output).
The same bus will probably be the input bus to other devices.
Registers may have a bidirectional connection to the bus.
This is a form of bus multiplexing: many data sources.

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 Data unit design. Interconnection
Shared output bus using a multiplexer

Instead of using registers with tri-state outputs, regular outputs

(unconditional) can be used and selected with a multiplexer.
The selection signal sel determines which register is read.
The actual multiplexer can be implemented in different ways.

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Data unit design. Interconnection
Multiplexer options

Tri-state multiplexer. Equivalent to

using registers with tri-state output
ports.

AND-OR multiplexer. A multiplexer

with decoded selection inputs.
Logically equivalent to the tri-state
multiplexer but avoids HI signals.

Regular multiplexer. Reduces

number of control signals, but may
complicate control unit design.

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 Data unit design. Interconnection
Bus multiplexing summary
●
Shared buses reduce resources (cost) but may impact performance.
●
Output bus sharing needs some kind of connection multiplexing:
– Registers with tri-state output.
– Tri-state multiplexer (equivalent to the above).
– Decoded-selection multiplexer (logically equivalent to the above).
– Regular multiplexers (saves control signals).
●
A shared bus connection can be easily changed form one type of
multiplexing to another.

Modern standard digital design avoids

using tri-state signals: no tri-state outputs
or tri-state multiplexers.
Most FPGA devices do not use tri-state
signals (except for external input/output
in IOBs).
Most logic synthesis tools can
automatically transform a design using
tri-state outputs to an equivalent design
using regular logic gates.
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 Data unit design. Interconnection
Example 2
Convert the data unit interconnection to an equivalent one using only
unidirectional ports and multiplexed buses (no more tri-state!).

Buses: add a MUX for every shared

output bus.
Registers: separate i/o ports. Move the
“read” control to the MUX.

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 Data unit design
Sample ALU-based architectures
●
ALU-based data units are the core of computers.
●
The number of buses used to “feed” the ALU has a big impact in the
overall design:
– More buses: higher cost, more performance.
– Fewer buses: lower cost, less performance.
●
Some examples with the same general specification
– One ALU with some operations.
– n registers: R0, …, Rn-1.
– Operators can be in any register and the result can go to any register.
● Rk ← operator(Ri, Rj)
– Sample macro-operation:
● R1 ← R2 + R3

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 Data unit design. ALU based
3 buses architecture

The ALU can get all the needed data and calculate the result in one clock cycle.
The result can be saved to the target register in the same clock cycle.

Note 1: tri-state register output used for simplicity.

Note 2: some controls signals omitted for simplicity.

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 Data unit design. ALU based
2 buses architecture

Only one bus for ALU input data. One operand have to be transferred to a temporary register (T).
An extra clock cycle is needed to transfer the operand to T.
T is a hidden register. No macro-operation uses it, but it is needed by the architecture “internally”.

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Data unit design. ALU based
1 bus architecture

Only one bus for all ALU input and output. Needs another temporary register to
store the result (A).
Another clock cycle (3) is needed to transfer the result to its destination.

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 Data unit design
Sample ALU-based architectures
Example 3
A variant of the 1-bus architecture has the ALU taking one of its operands from the A register and
the other operand from the bus, so the T register is no longer needed. The result is still stored in A
and the contents of A can be later transferred to any other register in the data unit. In this
configuration the A register works as an accumulator.
a) Draw a possible representation of this alternative design. Define A as needed.
b) Assuming that the ALU has a “transfer” operator so that it is possible to do A←Ri, calculate the
micro-operations needed to do the macro-operation R1←R2+R3. Compare to the sample 1-bus
data unit.
c) Calculate the micro-operation for the macro-operation R1←R2+R3+R4 with the sample 1-bus
calculator and this variant and compare them.

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 Data unit design
Sample ALU-based architectures

Same no. µOps

Fewer µOps!

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Simple calculator
Data unit design
Example 4. Simple calculator (data unit)
We want to build a calculator with the inputs and outputs in the
diagram.
●
A (rega) and B (regb) are the contents of two internal registers.
●
“din” is a data input.
●
“reset” takes the calculator to the initial state. In this state,
ready=1 and the calculator is ready to start a new operation.
●
The operation is selected by “op” (see the table).
●
“start” starts the operation selected by “op”.
●
When the operation finishes the calculator goes back to the initial
state.
Design a data unit for the calculator with a 2-buses architecture that
can perform all the calculator’s (macro)operations.

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 Simple calculator
Data unit design
Think about other design
alternatives

External data input

is controlled by a tri-
state buffer

The temporal A two-buses

register needed by architecture with
An ALU that is the two-buses arch. registers A and B
capable of doing all
required calculations

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 Simple calculator
Data unit block diagram

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 Control unit design
●
The control unit is just a FSM.
●
Once micro-operations have been calculated, the FSM specification
is straightforward.
●
But a regular state diagram may be confusing because we may have
many input and output signals (4 and 4 in our simple calculator).
●
We make some simplifications: only mention the input/output signals
that are active.
– If the signal is mentioned, it is active (normally '1').
– If the signal is not mentioned, it is not active (normally '0').

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 Control unit design
Algorithmic State Machine (ASM) charts
●
A better way to represent control units for digital systems.
●
Represents more clearly the algorithmic nature of control units.
●
Normally used in two steps:
– Step 1 (RTL ASM chart): represents the data transfer and processing at
each state.
– Step 2 (control ASM chart): represent the control signals that are
activated at each state.
●
The control chart is easily derived from the RTL chart by looking at
the data unit design.
●
From the control ASM chart it is easy to derive:
– A logic circuit that implements the FSM (classic approach).
– An HDL description of the FSM (current approach).

An experienced HDL coder can implement a control unit

directly in HDL (like Verilog) without an ASM chart.

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 ASM charts
Building blocks
State Name

RTL operation
or State box: represents an state of the FSM. The name of the
signal activation state is written next to the box. Includes the RTL operations
or signal activation that occurs while in that state.
Represents the Moore’s behavior of the state.

Decision box: the condition inside the box is tested and the path
0 1 out of the box is selected accordingly.
condition

Conditional box: always follows a decision box. Includes

the RTL operation or signal activation that will occur if the
condition leading to the box is met while in the state
determined by the previous state box. Represent the
Conditional Mealy’s behavior of the state.
RTL operation or
signal activation
A Moore’s FSM will not have conditional blocks.
Any path in the ASM chart must start and end in a
state block.
There cannot be loops that involve only decision and
conditional boxes.

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 ASM control charts
Simplified notation
●
Notation in control ASM charts:
– A signal name in a state or conditional box means the signal is active
(normally ‘1’).
– A signal name not present in a state conditional or conditional block
means the signal is not active (normally ‘0’).
– A signal name inside a decision box means the condition tests if the
signal is active (normally ‘1’).

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 ASM control charts
State diagram vs ASM chart

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Simple calculator
Control unit
Example 4. Simple calculator (control unit)
We want to build a calculator with the inputs and outputs in the
diagram.
●
A (rega) and B (regb) are the contents of two internal registers.
●
“din” is a data input.
●
“reset” takes the calculator to the initial state. In this state,
ready=1 and the calculator is ready to start a new operation.
●
The operation is selected by “op” (see the table).
●
“start” starts the operation selected by “op”.
●
When the operation finishes the calculator goes back to the initial
state.
Design a control unit of the calculator for the given data unit.

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 Simple calculator
ASM chart overall structure (initial state)

Micro-operations

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Simple calculator
Micro-operations

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Simple calculator
RTL ASM chart

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Simple calculator
Control ASM chart

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 Verilog modelling and test

Specification: describe the

system’s required operation and
interface.

RTL Design: describe a data unit

(schematic) and control unit (ASM
chart) that can perform all required
operations.

module calculator (
input ... RTL design with HDL (Verilog):
);
output ...
describe the system in Verilog. It
always @(posedge clk)
enables:
...
- Testing by simulation.
- Automatic logic synthesis.

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 Verilog modeling and test guidelines
●
Put in a separate Verilog module any part of the design that is complex
enough to need be simulated separately separately:
– E.g.: ALU, data unit, control unit and calculator.
●
Make one file for each module: one file = one module.
– Makes simulation and module re-use easier.
●
Name the file as the module (including case).
●
Write a test bench for and simulate any non-trivial module until it is
correct.
– Work bottom-up, since bigger modules may include smaller ones.
●
Make a top-level description for the system that is to be implemented in
your hardware platform.
– Many top-level modules are just interconnection and may not be simulated
if implemented on PLDs.
●
Implement and test the hardware.

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 Simple calculator
Verilog modeling and test plan
●
Stage 1: Data unit description and syntax check.
– Files: data_unit.v
●
Stage 2: Control unit description and syntax check.
– Files: control_unit.v
●
Stage 3: Calculator description and simulation.
– Files: calculator.v, calculator_tb.v
●
Stage 4: Top-level system for FPGA implementation.
– Files: system.v, display_ctrl.v, FPGA board configuration files.
Example 4. Simple calculator (Verilog coding)
Starting with the simple calculator’s design notes (operation
table, diagrams, ASM chart, etc.) describe it in Verilog and write
a test bench to test the design (stages 1 to 3).
Verilog design videos
This is a simple example. We are not:
- Simulating every module. Verilog code
- Describing the top-level module to be implemented.
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 Simple calculator Verilog description
Stage 1: data unit
// ALU
always @*
case(sel)
2'b00: alu_out = regt + bus;
2'b01: alu_out = regt - bus;
2'b10: alu_out = regt;
2'b11: alu_out = bus;
endcase

// T register
always @(posedge clk)
if (reset == 1'b0)
regt <= 'b0;
else if (wt)
regt <= bus;

// File: data_unit.v // A register

// Project: simple calculator always @(posedge clk)
// Description: Calculator's data unit if (reset == 1'b0)
// Author: Jorge Juan-Chico rega <= 'b0;
// Date: 2021-03-19 (initial) else if (wa)
rega <= alu_out;
module data_unit #(parameter W = 8)(
input wire clk, // clock signal // B register
input wire reset, // global reset always @(posedge clk)
input wire [1:0] sel, // ALU operation selector if (reset == 1'b0)
input wire rin, // input reading control regb <= 'b0;
input wire [W-1:0] din, // input data else if (wb)
input wire wt, // T register write control regb <= alu_out;
input wire ra, // A register read control
input wire wa, // A register write control // Output bus multiplexer
input wire rb, // B register read control always @*
input wire wb, // B register write control if (rin)
output reg [W-1:0] rega, // Register A bus = din;
output reg [W-1:0] regb // Register B else if (ra)
); bus = rega;
// Internal signals else if (rb)
reg [W-1:0] alu_out; // ALU output bus = regb;
reg [W-1:0] regt; // T register else
reg [W-1:0] bus; // output bus bus = 'b0;
endmodule
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 Simple calculator Verilog description
Stage 2: control unit
// State change process
always @(posedge clk)
if (reset == 1'b0)
state <= READY;
else
state <= next_state;
// Next state and output calculation
always @* begin
// default values
next_state = 'bx;
ready = 1'b0; sel = 'b0; rin = 1'b0; wt = 1'b0;
ra = 1'b0; wa = 1'b0; rb = 1'b0; wb = 1'b0;
// next state and output assignment
case (state)
READY: begin
ready = 1'b1;
if (start == 1'b0)
// File: contro_unit.v next_state = READY;
// Project: simple calculator else if (op == 2'b00 || op == 2'b01) begin
// Description: Calculator's control unit ra = 1'b1; wt = 1'b1;
// Author: Jorge Juan-Chico next_state = ADDSUB2;
// Date: 2021-03-19 (initial) end else if (op == 2'b10) begin
rin = 1'b1; wa = 1'b1; sel = 2'b11;
module control_unit ( next_state = READY;
input wire clk, // global clock end else begin // op = 11
input wire reset, // reset (active-low) rb = 1'b1; wt = 1'b1;
input wire start, // start next_state = SWAP2;
input wire [1:0] op, // operation code end
output reg ready, // ready for next operation end
output reg [1:0] sel, // ALU code ADDSUB2: begin
output reg rin, // data input read control rb = 1'b1; wa = 1'b1;
output reg wt, // T register write control sel[0] = op[0];
output reg ra, // A register read control next_state = READY;
output reg wa, // A register write control end
output reg rb, // B register read control SWAP2: begin
output reg wb // B register write control ra = 1'b1; wb = 1'b1; sel = 2'b11;
); next_state = SWAP3;
// State definition end
localparam READY = 0, SWAP3: begin
ADDSUB2 = 1, wa = 1'b1; sel = 2'b10;
SWAP2 = 2, next_state = READY;
SWAP3 = 3; end
// State variables endcase
reg [1:0] state, next_state; end
endmodule

Departamento de Tecnología Electrónica – Universidad de Sevilla 49

 Simple calculator Verilog description
Stage 3: calculator module and simulation
// Control unit instance
control_unit control_unit (
.clk(clk), // global clock
.reset(reset), // reset (active-low)
.start(start), // start
.op(op), // operation code
.ready(ready), // ready for next operation
.sel(sel), // ALU code
.rin(rin), // data input read control
.wt(wt), // T register write control
.ra(ra), // A register read control
// File: calculator.v .wa(wa), // A register write control
// Project: simple calculator .rb(rb), // B register read control
// Description: Calculator system. .wb(wb) // B register write control
// Author: Jorge Juan-Chico );
// Date: 2021-03-19 (initial)
// Data unit
module calculator #( data_unit #(.W(W)) data_unit (
parameter W = 8 .clk(clk), // clock signal
)( .reset(reset), // global reset
input wire clk, // global clock .sel(sel), // ALU operation selector
input wire reset, // reset (active-low) .rin(rin), // input reading control
input wire start, // start .din(din), // input data
input wire [W-1:0] din, // input data .wt(wt), // T register write control
input wire [1:0] op, // operation code .ra(ra), // A register read control
output wire ready, // ready for next operation .wa(wa), // A register write control
output wire [W-1:0] rega, // Register A .rb(rb), // B register read control
output wire [W-1:0] regb // Register B .wb(wb), // B register write control
);
// Internal signals .rega(rega), // Register A
wire [1:0] sel; .regb(regb) // Register B
wire rin, wt, ra, wa, rb, wb; );
endmodule

Departamento de Tecnología Electrónica – Universidad de Sevilla 50

 Simple calculator Verilog description
Stage 3: calculator module and simulation
// File: calculator_tb.v // Main simulation process
// Project: simple calculator // A <- 5
// Description: System's test bench // SWAP(A,B)
// Author: Jorge Juan-Chico // A <- 3
// Date: 2021-03-19 (initial) // A <- A + B : A = 8, B = 3
// SWAP(A,B)
`timescale 1ns / 1ps // A <- 12
// A <- A - B : A = 4, B = 8
module test (); initial begin
// output generation
reg clk; // global clock $dumpfile("calculator_tb.vcd");
reg reset; // reset (active-low) $dumpvars(0, test);
reg start; // start
reg [7:0] din; // input data // input signal initialization
reg [1:0] op; // operation code clk = 1'b0;
reset = 1'b1;
wire ready; // ready for next operation start = 1'b0;
wire [7:0] rega; // Register A din = 'b0;
wire [7:0] regb; // Register B op = 'b0;

calculator #(.W(8)) calculator ( // global reset

.clk(clk), // global clock @(posedge clk) #1 reset = 1'b0;
.reset(reset), // reset (active-low) @(posedge clk) #1 reset = 1'b1;
.start(start), // start
.din(din), // input data repeat(3) @(posedge clk) #1;
.op(op), // operation code
.ready(ready), // ready for next operation din = 5; op = 2; // A <- 5
.rega(rega), // Register A start = 1'b1;
.regb(regb) // Register B @(posedge clk) #1;
); start = 1'b0;

// Clock generator (T=20ns, f=50MHz) repeat(3) @(posedge clk) #1;

always
#10 clk = ~clk; // A should be 5 here

op = 3; // SWAP(A,B)
start = 1'b1;
@(posedge clk) #1;
start = 1'b0;

[...]
Departamento de Tecnología Electrónica – Universidad de Sevilla 51
Simple calculator. Top-level system design
and FPGA implementation
●
The implementation in the development
board requires some additional devices:
A – 7-segment display controller: to convert
binary data to drive the 7-segment display.
B
– An inverter to make the reset signal active-
high (easier to control with a push button).
– An edge detecting circuit to convert a
start button press in a single pulse.

op din reset
module system (
input ...
output ...
);

calculator ...
display_ctrl ...
edge_detector ...

Departamento de Tecnología Electrónica – Universidad de Sevilla 52

 Simple calculator Verilog description
Stage 4: top-level system and imp.

// Edge detector
always @(posedge(clk)) begin
start0 <= start;
if (start == 1'b1 && start0 == 1'b0)
start1 <= 1'b1;
else
start1 <= 1'b0;
end

// Calculator instance
calculator #(.W(W)) calculator (
// File: system.v .clk(clk), // global clock
// Project: simple calculator .reset(~reset), // reset (active-low)
// Description: Calculator system. .start(start1), // start
// Author: Jorge Juan-Chico <[email protected]> .din(din), // input data
// Date: 2023-02-12 (initial version) .op(op), // operation code
.ready(ready), // ready for next operation
module system #( .rega(rega), // Register A
parameter W = 4 .regb(regb) // Register B
)( );
input wire clk, // clock (rising edge)
input wire reset, // reset button (active-high)// 7-segment controller instance
input wire start, // start button display_ctrl #(.cdbits(18), .hex(1)) display_ctrl (
input wire [W-1:0] din, // data input .ck(clk), // system clock
input wire [1:0] op, // operation input .x3(4'h0), // display digits, from left to right
output wire ready, // ready indicator .x2(rega),
output wire [3:0] an, // 7-segment anode control .x1(4'h0),
output wire [0:6] seg, // 7-segment code (active-low) .x0(regb),
output wire dp // 7-segment decimal point output.dp_in(4'b1011), // decimal point vector
); .seg(seg), // 7-segment output
.an(an), // anode output
// Internal signals .dp(dp) // decimal point output
wire [W-1:0] rega, regb; );
reg start0, start1; endmodule

Departamento de Tecnología Electrónica – Universidad de Sevilla 53

Simple calculator Verilog description
Stage 4: top-level system and imp.
system.v

synthesis bitstream
tools
restrictions
file

programmer

start

op din reset

Departamento de Tecnología Electrónica – Universidad de Sevilla 54

 Working example 1 (WE1)
RPN simple calculator
●
RPN stands for “Reverse Polish Notation” or “put an HP calculator in
your life”.
– See the Wikipedia to learn more about Normal Polish Notation (NPN)
and Reverse Polish Notation (RPN).
– Try a RPN calculator in the web.
– Install Free42 (for various platforms including Android) to have an
emulator of probably the best RPN calculator ever made.
●
Advantages of RPN over normal (infix/algebraic) notation
– No need to type parenthesis.
– Fewer keystrokes for the same expression.
– More similar to manual simplification.
– Easier to implement.
– Can be extended to a full programming language.

Departamento de Tecnología Electrónica – Universidad de Sevilla 55

 Working example 1 (WE1)
RPN simple calculator

Infix (normal) KS RPN KS Value

(7 + 5) * 2 7 75+2* 6 24

((9 - 2) * 4) ^ 3 11 92-4*3^ 8 21952

3 * (5 - 2) / (9 - 1) 13 352-*91-/ 12 1.125

3 * (5 - 2) ^ (7 - 3) / ((9 - 1) * 352-73-^*91
27 22 2.53125
(8 + 4)) -84+*/

Try it out in the HP 15C!

Departamento de Tecnología Electrónica – Universidad de Sevilla 56

 WE1: RPN simple calculator
User-level specification
Interface Operations

The calculator needs the following peripherals:

Input (X) is set using the switches in the board. a 4-digit 7-segment display, 8 switches, 4
buttons and 2 LEDs.
An internal register (Y) works as an accumulator.
The operation is executed immediately upon button pressing.
The Digilent Basys2 board fulfill the
The display shows X and Y in hexadecimal.
requirements. Port names in the Basys2 board
Operation are done in two's complement with 8 bits. are in orange.
LEDs indicate carry (c) and overflow (v) when needed.
Departamento de Tecnología Electrónica – Universidad de Sevilla 57
WE1: RPN simple calculator
User-level specification

ov c
x

+/-

x -
+

enter

Departamento de Tecnología Electrónica – Universidad de Sevilla 58

WE1: RPN simple calculator
Data unit design

Departamento de Tecnología Electrónica – Universidad de Sevilla 59

 WE1: RPN simple calculator
Data unit design

We already know how to design all the required elements: ALU

and registers.
Instead of using basic blocks (gates, FA, HA, flip-flops, etc.) we
will just model each element using Verilog and we will let the
synthesis tools to do the hard work of building the circuits for us.

Departamento de Tecnología Electrónica – Universidad de Sevilla 60

 WE1: RPN simple calculator
Control/data unit connection

The control unit reads the active input (enter, add, sub or pm)
and generates the sequence of control signals for the data unit
to perform the required operation.
Control unit + data unit form our calculator, but we still lack the
interface to display x_in and y_reg in the 7-segment display.

Departamento de Tecnología Electrónica – Universidad de Sevilla 61

WE1: RPN simple calculator
Top-level system

We add a 4-digit 7-segment controller from our library.

Now we have a system that can be implemented in our prototype
board (Digilent Basys2).
Basys2 port names are in orange.

Departamento de Tecnología Electrónica – Universidad de Sevilla 62

 WE1: RPN simple calculator
Control unit design
●
The control unit has to “execute” this loop:
– Wait for an operation button to be pressed.
– Generate the signals for the data unit to do the computations needed by
the selected macro-operation.
– Wait for all buttons to be released.
●
All macro-operation in our calculator are simple and can be done by
the data unit in just one clock cycle (just one micro-operation).
●
More complex macro-operations may require more than one clock
cycle.

Departamento de Tecnología Electrónica – Universidad de Sevilla 63

WE1: RPN simple calculator
Macro- and micro-operations

Macro-operation
Micro-operations Micro-operations
name for each macro for each macro
(register transfer) (signal activation)

Departamento de Tecnología Electrónica – Universidad de Sevilla 64

 WE1: RPN simple calculator
Complex macro-operations (example)

Micro-operations Value of y after the

Macro-operation for each macro micro-op
(register transfer) (y0 → initial value)

How do we generate a correct

carry/overflow? Can we?
Calculate signals activation.

Does it always work? For any

value of X?

Departamento de Tecnología Electrónica – Universidad de Sevilla 65

WE1: RPN simple calculator
Control unit state diagram

It does the job, but the “algorithm” implemented by

the control unit is not easy to grasp from a state
diagram.

We have a better way to represent algorithmic

state machines.

Departamento de Tecnología Electrónica – Universidad de Sevilla 66

WE1: RPN simple calculator
RTL ASM chart
RTL chart (only one press)

Departamento de Tecnología Electrónica – Universidad de Sevilla 67

WE1: RPN simple calculator
Control ASM chart
Control chart (only one press)

Departamento de Tecnología Electrónica – Universidad de Sevilla 68

WE1: RPN simple calculator
Alternative RTL ASM chart
RTL chart (priority)

Departamento de Tecnología Electrónica – Universidad de Sevilla 69

WE1: RPN simple calculator
Alternative control ASM chart
Control chart (priority)

Departamento de Tecnología Electrónica – Universidad de Sevilla 70

 WE1: RPN simple calculator
Verilog modelling
Specification: describe the
system’s required operation and
interface.

RTL Design: describe a data unit

(schematic) and control unit (ASM
chart) that can perform all required
operations.

RTL design with HDL (Verilog):

module calculator ( describe the system in Verilog. It
input ...
output ... enables:
);
- Testing by simulation.
always @(posedge clk)
... - Automatic logic synthesis.

Departamento de Tecnología Electrónica – Universidad de Sevilla 71

 WE1: RPN simple calculator
Verilog modeling and implementation
●
The importance of design and implementation planning
●
Stage 1: ALU design and simulation
●
Stage 2: Data unit design and simulation
●
Stage 3: Control unit design and simulation
●
Stage 4: Calculator design and simulation
●
Stage 5: Top-level system design, implementation and test

Verilog code template

Departamento de Tecnología Electrónica – Universidad de Sevilla 72

 WE1 Verilog modeling
Stage 1: ALU
Carry and overflow may be tricky and
can be left for later.

always @* begin
c = 1'b0; v = 1'b0;
case(op)
`ALU_ADD: begin
r = a + b;
// Design: Simple RPN calculator c = a[7] & b[7] | b[7] & ~r[7] | a[7] & ~r[7];
// File: alu.v v = ~a[7] & ~b[7] & r[7] | a[7] & b[7] & ~r[7];
// Description: Arithmetic-(Logic) Unit end
// Author: Jorge Juan-Chico <[email protected]> `ALU_SUB: begin
// Date: 2021-02-27 (initial) r = a - b;
c = ~a[7] & b[7] | b[7] & r[7] | ~a[7] & r[7];
`define ALU_ADD 0 v = a[7] & ~b[7] & ~r[7] | ~a[7] & b[7] & r[7];
`define ALU_SUB 1 end
`define ALU_TRA 2 `ALU_TRA: begin
`define ALU_NEGB 3 r = a;
end
module alu #( `ALU_NEGB: begin
parameter W = 8 // Data width r = -b;
)( c = |b;
input wire [W-1:0] a, // data input a v = b[7] & r[7] | ~b[7] & ~r[7];
input wire [W-1:0] b, // data input b end
input wire [1:0] op, // operation selector default: // Should not happen
output reg c, // carry carry output flag r = 'bx;
output reg v, // overflow flag endcase
output reg [W-1:0] r // output result end
); endmodule

Departamento de Tecnología Electrónica – Universidad de Sevilla 73

 WE1 Verilog modeling
Stage 1: ALU test bench
// Design: Simple RPN calculator initial begin
// File: alu.v np = `NP;
// Description: Arithmetic-(Logic) Unit. Test bench.
// Author: Jorge Juan-Chico <[email protected]> // Waveform generation (optional)
// Date: 2021-02-27 (initial) // $dumpfile("test.vcd");
// $dumpvars(0, test);
`timescale 1ns / 1ps
// Output printing
// Simulation macros and default values: $write("Operation: %d ", op);
// NP: number of test patterns case (op)
// SEED: initial seed for pseudo-random number generation 0: $display("ADD");
// OP: type of operation (see 'alu.v') 1: $display("SUB");
2: $display("TRANSFER A");
`ifndef NP default: $display("NEGATE B");
`define NP 20 endcase
`endif
`ifndef SEED $display(" A B",
`define SEED 1 " OUT c v");
`endif $monitor("%b (%d) %b (%d) %b (%d) %b %b",
`ifndef OP a, a, b, b, alu_out, alu_out, c, v);
`define OP 0 end
`endif
// Test generation process
module test (); always begin
$ iverilog #20
-DOP=1 -DNP=40 -DSEED=2 alu.v alu_tb.v
reg signed [7:0] a; // input 'a' $ vvp a.outa = $random(seed);
reg signed [7:0] b; // input 'b' Operation: b1 = $random(seed);
SUB
reg [1:0] op = `OP; // type of operation A np = np - 1; B OUT c v
wire signed [7:0] alu_out; // output if (np == 0)
xxxxxxxx ( x) xxxxxxxx ( x) xxxxxxxx ( x) x x
wire c; // carry flag $finish;
00000000 ( 0) 01110001 ( 113) 10001111 (-113) 1 0
wire v; // overflow flag end
11010100 ( -44) 00110001 ( 49) 10100011 ( -93) 0 0
endmodule
integer np; 01000000
// number of patterns (auxiliary ( 64) 11000000 ( -64)
signal) 10000000 (-128) 1 1
integer seed = `SEED; // seed (auxiliary signal) 11000100 ( -60) 00100001 ( 33) 10100011 ( -93) 0 0
10010011 (-109) 11111010 ( -6) 10011001 (-103) 1 0
// Circuit under test 00101111 ( 47) 11001100 ( -52) 01100011 ( 99) 1 0
01110010
/* Alu width is parametrized. We instantiate an 8 bit ALU. */ ( 114) 00001101 ( 13) 01100101 ( 101) 0 0
alu #(.W(8)) uut (.a(a), .b(b), .op(op), 01110101 ( 117) 11000101 ( -59) 10110000 ( -80) 1 1
.c(c), .v(v), .r(alu_out)); 01001100 ( 76) 10101111 ( -81) 10011101 ( -99) 1 1

Departamento de Tecnología Electrónica – Universidad de Sevilla 74

 WE1 Verilog modeling
Stage 2: data unit
// Design: Simple RPN calculator
// File: data_unit.v

module data_unit #(
parameter W = 8 // Data width
)(
input wire clk,
input wire [W-1:0] x_in,
input wire [1:0] op,
input wire y_w,
input wire s_w,
output reg [W-1:0] yreg, // Y register
output wire f_c, // flag carry
output wire f_v // flag overflow
);
wire [W-1:0] alu_out;
wire c, v;
reg [1:0] sreg; // Status register

// ALU instance
alu #(.W(8)) alu (.a(x_in),.b(yreg),.op(op),
Register Y and the status register are );
.c(c),.v(v),.alu_out(alu_out)

defined inside the data unit (we do

// Y register (accumulator)
not need a separate module for them. always @(posedge clk)
if (y_w)
The previously designed (and tested) yreg <= alu_out;

ALU is instantiated. // Status register

always @(posedge clk)
Note the module's output signals. if (s_w)
sreg <= {v, c};
Check the system's drawings.
// Status flags output
assign f_c = sreg[0];
assign f_v = sreg[1];
endmodule

Departamento de Tecnología Electrónica – Universidad de Sevilla 75

 WE1 Verilog modeling
Stage 2: data unit test bench
// Design: Simple RPN calculator
// File: data_unit_tb.

`timescale 1ns / 1ps

module test ();

reg clk; reg [7:0] x_in; reg [1:0] op; reg y_w; reg s_w;
wire [7:0] yreg; // Y register
wire f_c; // flag carry
wire f_v; // flag overflow

// Data unit instance

data_unit #(.W(8)) data_unit (...);
The test bench
// Clock generator (T=20ns, f=50MHz)
always
displays an error
#10 clk <= ~clk; if the results are
not as expected
// Main simulation process
// We make the data unit do: Y = 7 - 3.
// Operation (active control signals)
// x_in = 7; yreg <- x_in (op=TRA, y_w)
// x_in = 3; yreg <- yreg-x_in; sreg <- {v,c} (op=SUB; y_w)
The test bench emulates the
initial begin
control sequence to perform
the operations: [...]

if (yreg!=4 || f_c!=1'b0 || f_v!=1'b0)

Y=7-3 $display("ERROR: ...");

Y = Y + 125 [...]

$finish; // finish the simulation

end
endmodule

Departamento de Tecnología Electrónica – Universidad de Sevilla 76

WE1 Verilog modeling
Stage 3: control unit
// Design: Simple RPN calculator
// File: control_unit.v

module control_unit (
input wire clk, // clock (rising edge)
input wire reset, // reset (synchronous, active-low)
input wire enter, // enter key
input wire add, // add key
input wire sub, // subtract key
input wire pm, // plus/minus key

output reg [1:0] op, // ALU operation control

output reg y_w, // yreg (accumulator) write control
output reg s_w // sreg (status) write control
);

// State definition
localparam [1:0] READY = 0,
WAIT = 1;

// State variables
reg [1:0] state, next_state;

// State change process

always @(posedge clk, negedge reset)
if (reset == 1'b0)
state <= READY;
else
state <= next_state;

[...]

The control unit is a standard FSM. The code can be directly derived
from the ASM control chart (see DEC unit about FSMs).
The code adds a reset signal, that must be present in every FSM
implementation.

Departamento de Tecnología Electrónica – Universidad de Sevilla 77

 WE1 Verilog modeling
Stage 3: control unit
// Next state and output process
always @* begin
// Default output values
op = 'bx; y_w = 1'bx; s_w = 1'bx;
next_state = 'bx;
case (state)
READY: begin
y_w = 1'b1; s_w = 1'b1;
next_state = WAIT;
if (enter) // ALU_TRA
op = 2;
else if (add) // ALU_ADD
op = 0;
else if (sub) // ALU_SUB
op = 1;
else if (pm) // ALU_NEGB
op = 3;
else begin
op = 0; y_w = 1'b0; s_w = 1'b0;
next_state = READY;
end
end
WAIT: begin
y_w = 1'b0; s_w = 1'b0;
op = 0;
if (enter || add || sub || pm)
next_state = WAIT;
else
next_state = READY;
end
default: begin // Should not reach this point
next_state = 'bx; y_w = 1'bx; s_w = 1'bx;
end
The code actually implements the version with endcase
operation priority. end
endmodule
Try to describe the other version.

Departamento de Tecnología Electrónica – Universidad de Sevilla 78

 WE1 Verilog modeling
Stage 3: control unit test bench
// Design: Simple RPN calculator
// File: control_unit_tb.v

module test ();

[...]

// Control unit instance

control_unit control_unit (...);

// Clock generator (T=20ns, f=50MHz)

[...]

// Main simulation process

initial begin
// Signal initialization
reset = 1'b1;
clk = 1'b0;
{enter, add, sub, pm} = 4'b0000;

// Output printing
$display("reset enter add sub pm : op y_w s_w");
$monitor(" %b %b %b %b %b : %d %b %b",
reset, enter, add, sub, pm, op, y_w, s_w);

// Operation
@(posedge clk) #1; // wait one clock cycle and
reset = 1'b0; // reset
@(posedge clk) #1;
The test bench just activates some inputs of reset = 1'b1;
the control unit in sequence: repeat(3) @(posedge clk) #1;
enter = 1'b1; // press "enter"
- enter a number, repeat(3) @(posedge clk) #1;
- change the sign, enter = 1'b0;
repeat(3) @(posedge clk) #1;
- add with the previous number, pm = 1'b1; // press "pm"
- enter another number, repeat(3) @(posedge clk) #1;
- subtract to the previous number. pm = 1'b0;
[...]
$finish; // finish the simulation
end
endmodule
Departamento de Tecnología Electrónica – Universidad de Sevilla 79
 WE1 Verilog modeling
Stage 4: calculator module
// Design: Simple RPN calculator
// File: calculator.v

module calculator #(
parameter W = 8 // Data width
)(
input wire clk, // clock (rising edge)
input wire reset, // reset (synchronous, active-low)
input wire enter, // enter key
input wire add, // add key
input wire sub, // subtract key
input wire pm, // plus/minus key
input wire [W-1:0] x_in, // data input
output wire [W-1:0] yreg, // data output (Y register)
output wire f_c, // flag carry
output wire f_v // flag overflow
);

// Internal signals
wire [1:0] op;
wire y_w, s_w;

// Control unit instance

control_unit control_unit (
.clk(clk), // clock (rising edge)
.reset(reset), // reset (synchronous, active-low)
.enter(enter), // enter key
[...]
);

// Data unit instance

data_unit #(.W(8)) data_unit (
The calculator module is just the interconnection .clk(clk), // clock input
.reset(reset), // reset signal, active-low
of the data and control units. .x_in(x_in),
[...]
);
endmodule

Departamento de Tecnología Electrónica – Universidad de Sevilla 80

 WE1 Verilog modeling
Stage 4: calculator module test bench
// Design: Simple RPN calculator
// File: calculator_tb.v

module test ();

[...]
// Calculator instance
calculator #(.W(8)) calculator (
[...]
);

// Clock generator (T=20ns, f=50MHz)

[...]

// Main simulation process

initial begin
// Signal initialization
reset = 1'b1; clk = 1'b0;
{enter, add, sub, pm} = 4'b0000; x_in = 0;

// Output printing
$display("reset enter add sub pm : x_in yreg f_c f_v");
$monitor(" %b %b %b %b %b : %d %d %b %b",
reset, enter, add, sub, pm, x_in, yreg, f_c, f_v);

// Operation
@(posedge clk) #1; // wait one clock cycle and do
This test bench is very similar to the control reset = 1'b0; // reset
unit, but now the data unit should generate @(posedge clk) #1;
the correct result. It does: reset = 1'b1;
repeat(3) @(posedge clk) #1;
- enter number 7,
- change the sign, x_in = 7; // Y <- 7
enter = 1'b1; // press "enter"
- enter number 20 and add, repeat(3) @(posedge clk) #1;
- enter number 5 and subtract. enter = 1'b0;
repeat(3) @(posedge clk) #1;

[...]
$finish; // finish the simulation
end
endmodule
Departamento de Tecnología Electrónica – Universidad de Sevilla 81
 WE1 Verilog modeling
Stage 5: top-level system and test
// Design: Simple RPN calculator
// File: system.v

module system (
input wire clk, // clock (rising edge)
// input wire reset, // reset (synchronous, active-low)
input wire enter, // enter key
input wire add, // add key
input wire sub, // subtract key
input wire pm, // plus/minus key
input wire [7:0] x_in, // data input
output wire f_c, // flag carry
output wire f_v, // flag overflow
output wire [3:0] an, // 7-segment anode control
output wire [0:6] seg, // 7-segment code (active-low)
output wire dp // 7-segment decimal point output
);

// Internal signals
wire [7:0] yreg;

// Calculator instance
calculator #(.W(8)) calculator (
.clk(clk), // clock (rising edge)
.reset(1'b1), // reset (synchronous, active-low)
.enter(enter), // enter key
This is the module that will be implemented in the [...]
);
development board.
It just connects the calculator to the 7-segment // 7-segment controller instance
display_ctrl #(.cdbits(18), .hex(1)) display_ctrl (
display controller we have taken from elsewhere. .ck(clk), // system clock
.x3(x_in[7:4]), // display digits, from left to right
Note that the reset input has been disabled by .x2(x_in[3:0]),
setting it to 1. If necessary, it could be connected .x1(yreg[7:4]),
to a GPIO port. .x0(yreg[3:0]),
.dp_in(4'b1011), // decimal point vector
We won't simulate it and just test in a FPGA chip. .seg(seg), // 7-segment output
.an(an), // anode output
We also need a “restrictions” file for the synthesis .dp(dp) // decimal point output
tool. );
endmodule
Departamento de Tecnología Electrónica – Universidad de Sevilla 82
 WE1 Verilog modeling
Source files necessary at each stage
●
Stage 1: ALU design and simulation
– alu.v, alu_tb.v
●
Stage 2: Data unit design and simulation
– + data_unit.v, data_unit_tb.v
●
Stage 3: Control unit design and simulation
– + control_unit.v, control_unit_tb.v
●
Stage 4: Calculator design and simulation
– + calculator.v, calculator_tb.v
●
Stage 5: Top-level system design, implementation and test
– + display_ctrl.v, system.v, system.ucf

Departamento de Tecnología Electrónica – Universidad de Sevilla 83

 WE1 Verilog modeling
Improvements and alternatives
●
BTN0 does a clear (Y ← 0)
– Modifying the data unit (level 1)
– Without modifying the data unit (level 2)
●
BTN0 doubles (Y ← 2Y)
– Modifying the data unit (level 1)
– Without modifying the data unit (level 2)
– NOTE: generate overflow bit only (carry=0)
●
BTN0 multiplies (Y ← X * Y)
– Modifying the data unit (level 2)
– Without modifying the data unit: a counter may help (level 3)
– NOTE: generate overflow bit only (carry=0)
●
BTN0 is a shift key and introduce logic operations (level 2)
– BTN0+BTN1 (and): Y ← X AND Y
– BTN0+BTN1 (or): Y ← X OR Y
– BTN0+BTN1 (not): Y ← NOT Y

Departamento de Tecnología Electrónica – Universidad de Sevilla 84

 Working example 2 (WE2)
3-register stack RPN calculator
WE1 shortcomings How to do 3 - (5 - 4)?
●
1 register stack (Y). Cannot operate complex Option 1 (not possible)
expressions (not two “enter” without 354--
operation). Option 2 (possible)
●
Very few operations. 54-±3+

WE2 improvements Can do expressions like:

3 - 5 * (4 + 2) * (7 - 9)
●
3 register stack (X, Y, Z).
3 - (5 - (4 - 1) * 2)
●
More operations: +, -, ±, *, ½, X↔Y, R↓

WE2 operation
●
“enter” loads new data in the stack from d_in.
●
“calc” perform a calculation given by a code in
d_in.
●
Operations use X or X and Y.
●
The result is always stored in X.
●
Operations are two's complement.

Departamento de Tecnología Electrónica – Universidad de Sevilla 85

 WE2 Macro-operations

External signal activation Macro-operation Comment

enter Z ← Y; Y ← X; X ← d_in Load X and push stack up

calc & d_in=ADD X ← X + Y; Y ← Z; Z ← 0 Add X and Y, pop stack

calc & d_in=SUB X ← X - Y; Y ← Z; Z ← 0 Sub. X and Y, pop stack

calc & d_in=MUL X ← X * Y; Y ← Z; Z ← 0 Mult. X and Y, pop stack

calc & d_in=PM X ← -X Complement X

calc & d_in=HALF X ← SHR(X) Divide X by 2

calc & d_in=DOWN X ← Y; Y ← Z; Z ← X Rotate the stack down

calc & d_in=SWXY X ← Y; Y ← X Swap X and Y

Departamento de Tecnología Electrónica – Universidad de Sevilla 86

 WE2 design exercise
Step 1
Draw a data unit for the new calculator. Use tri-state buses, but only unidirectional ports. Try two
options and select one of them
●
A 1 shared bus architecture.
●
A 3 shared buses architecture.
Redraw the selected option substituting the tri-state buses by multiplexers.

Step 2 Step 3
Assign values to the operation codes in d_in. Specify the operations to be implemented by
the ALU.

Step 4 Step 5
Specify the operations to be implemented by Write the micro-operations for the selected
the registers and their control signals. architecture that are needed to execute each
macro-operation.

Step 6 Step 7
Draw the RTL and control ASM chart of a Describe the system in Verilog. Decide which
control unit for the system. modules to design and simulate independently

Step 8
Map the system's input/output signals to a development board and implement it. (Include
additional peripherals in a top-level design if needed).
Departamento de Tecnología Electrónica – Universidad de Sevilla 87