LOW POWER AND HIGH-SPEED MULTI-

THRESHOLD DATA FLIP-FLOP DESIGN WITH

18nm FINFET TECHNOLOGY
A Project Report Submitted in Partial fulfilment of the Requirement for the
Award of the Degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by

NEELA JAGADEESH(219Y1A04B5)

OBUGANI RAVANAMMA( 219Y1A04B8)

MANGALI JANARDHAN( 219Y1A0492)

NALLAGONDU VENKATA SAI VAMSI(219Y1A04A9)

KASTURI RADHA PRIYANJALI(219Y1A0469)

Under the Guidance of

Smt. Y.SRAVANTHI, M.Tech.
Associate Professor
Department of Electronics and Communication Engineering

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

K.S.R.M. COLLEGE OF ENGINEERING

(AUTONOMOUS)
(Approved by AICTE, New Delhi & Affiliated to JNTUA, Ananthapuramu)
(Accredited by NAAC with A+ Grade & B. Tech. (EEE, ECE, CSE, CE and ME) Programs by NBA)
(An ISO 9001:2018, 14001:2004 Certified Institution)
KADAPA – 516005 (A.P.)
2024- 2025
 K.S.R.M. COLLEGE OF ENGINEERING
(AUTONOMOUS)
(Approved by AICTE, New Delhi & Affiliated to JNTUA, Ananthapuramu)
(Accredited by NAAC with A+ Grade & B. Tech. (EEE, ECE, CSE, CE and ME) Programs by NBA)
(An ISO 9001:2018, 14001:2004 Certified Institution)
KADAPA – 516005 (A.P.)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the project report entitled “LOW POWER AND HIGH-SPEED
MULTI-THRESHOLD DATA FLIP-FLOP DESIGN WITH 18nm FINFET
TECHNOLOGY”, is the Bonafide work done and submitted by NEELA JAGADEESH
(219Y1A04B5), MANGALI JANARDHAN (219Y1A0492), OBUGANI RAVANAMMA
(219Y1A04B8), NALLAGONDU VENKATA SAI VAMSI (219Y1A04A9), KASTURI
RADHA PRIYANJALI (219Y1A0469) to K.S.R.M. College of Engineering
(AUTONOMOUS), Kadapa in partial fulfilment of the requirements for the award of the
degree of “BACHELOR OF TECHNOLOGY” in “ELECTRONICS AND
COMMUNICATION ENGINEERING” during the period 2024-2025.

Project guide: Head of the Department:

Smt. Y. SRAVANTHI, M.Tech. Dr. V. VIJAYA KISHORE, M.Tech., Ph.D.
Assistant Professor, Professor & Head,
Dept. of E.C.E. Dept. of E.C.E.

Date: Internal Examiner External Examiner

I
 DECLARATION
We hereby declare that the project work entitled “Low Power and High-Speed Multi-Threshold
data flip flop design with 18nm FINFET technology” submitted in partial fulfillment of the
requirements for the award of the degree of Bachelor of Technology in Electronics and
Communication Engineering to KSRM College of Engineering (Autonomous), Kadapa, is a
record of original work carried out by us under the guidance of Smt.Y.SRAVANTHI, M.Tech.
and Assistant Professor.

This project has not been submitted earlier, either in part or in full, for the award of any degree
or diploma in any university or institution.

Place: KADAPA
Date:

Roll Number Name of the Student Signature

219Y1A04B5 Neela Jagadeesh

219Y1A04B8 Obugani Ravanamma
219Y1A0492 Mangali Janardhan
219Y1A04A9 Nallagondu Venkata sai vamsi
219Y1A0469 Kasturi Radha priyanjali

II
 ACKNOWLEDGEMENT
We take this opportunity to express our deep gratitude and appreciation to all those who encouraged
for successful completion of project work.
We are deeply indebted to our supervisor Smt. Y. SRAVANTHI, M.Tech., and Head of the
Department of Electronic and Communication Engineering Dr. V. VIJAYA KISHORE, Ph.D.,
for valuable guidance, constructive criticism and keen interest evinced throughout the course of
our project work. We are really fortunate to associate ourselves with such an advising and helping
guide in every possible way, at all stages, for the successful completion of this work.
We express gratitude to our principal Dr. V. S. S. MURTHY, Ph.D., for supporting us in
completion of our project work successfully by providing the facilities. We are pleased to express
our heart full thanks to our faculty in Department of ECE of K.S.R.M College of Engineering
College for their moral support and good wishes.
Finally, we have a notation to express our sincere thanks to friends and all those who guided,
inspired and helped us in the completion of our project.

PROJECT ASSOCIATES

Neela Jagadeesh 219Y1A04B5

Obugani Ravanamma 219Y1A04B8
Mangali Janardhan 219Y1A0492
Nallagondu Venkata sai vamsi 219Y1A04A9
Kasturi Radha priyanjali 219Y1A0469

III
 INSTITUTION VISION AND MISSION

VISION
To evolve as center of repute for providing quality academic programs amalgamated with creative
learning and research excellence to produce graduates with leadership qualities, ethical and
human values to serve the nation.

MISSION
M1: To provide high quality education with enriched curriculum blended with impactful teaching-
learning practices.
M2: To promote research, entrepreneurship and innovation through industry collaborations.
M3: To produce highly competent professional leaders for contributing to Socio-economic
development of region and the nation.

IV
 DEPARTMENT VISION AND MISSION

VISION
To emerge as globally recognized department in the frontier areas of Electronics and
Communication Engineering.

MISSION
M1: To imbibe experiential, lifelong learning skills and problem solving capabilities through
enriched curriculum and innovative teaching learning practices.
M2: To promote quality research by strengthening industry collaborations.
M3: To inculcate entrepreneurial attitude, leadership skills, human values and professional ethics.

V
 PEOs, POs and PSOs
Programme Educational Objectives
PEO1: To apply the concepts of electronics, communication and computation and pursue career in
core and allied industries to solve industrial and societal problems.
PEO2: To pursue higher education to progress professionally in contemporary Technologies and
multidisciplinary fields with an inclination towards continuous learning.
PEO3: To exhibit professional skills, ethical values, interpersonal skills, leadership abilities, team
spirit and lifelong learning.

Programme Outcomes
PO1 - Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO2 - Problem Analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
PO3 - Design/Development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
PO4 - Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5 - Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modelling to complex engineering activities with
an understanding of the limitations.
PO6 - The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.

VI
PO7 - Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO8 - Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of engineering practice.
PO9 - Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
PO10 - Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions .
PO11 - Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one's own work, as a member and leader
in a team, to manage projects and in multidisciplinary environments.
PO12 - Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.
Programme Specific Outcomes
The Program Outcomes after successful completion of B.Tech ECE program are,
PSO1: An ability to design electronic circuits for applications including signal
processing,communications, computer networks, Embedded systems and in the field of VLSI.
PSO2: Develop innovative technologies for Entrepreneurship with new cutting-edge Technologies
in the fields of electronic design, communication and automation.
PSO3: Identify and Apply Domain specific tools for Design, Analysis and Synthesis in the areas
of Signal Processing, Communications, VLSI and Embedded systems.

VII
 TABLE OF CONTENTS
Chapters Description Page No.
Abstract x

LIST OF ABBREVIATIONS xi

LIST OF FIGURES xii

LIST OF TABLES xiii

Chapter-1 INTRODUCTION 1
1.1. Introduction for Mt-Finfet based D-FlipFlop 1

1.2. PROJECT OVERVIEW 1

1.3. OBJECTIVES 2

2
1.3.1. Design and Implementation
2
1.3.2. Performance Evaluation and Comparison
2
1.3.3. Optimization of Power Consumption and Speed
3
1.3.4. Technology Feasibility for Low-Power Applications
3
1.3.5. Simulation and Validation
1.4. Significance of the Project 3

1.5. Scope of the Project 4

Chapter-2 LITERATURE SURVEY 5-7

Chapter-3 PROPOSED METHOD 8

3.1. Introduction to the Proposed Method 8

3.2. Overview of Multi-Threshold FinFET Technique 8
3.3. Circuit Design Architecture 8
3.4. FinFET Advantages in This Design 9
3.5. Implementation Using Cadence EDA Tools 9
3.5.1.Schamitac Design 9
3.5.2. Simulation and Functional Verification
3.6. Summary 10
Chapter-4 MOSFET AND FINFET 11

VIII
 4.1 MOSFET structure 11
4.2 MOSFET operation 11
4.3 FinFET Structure 12
4.4 How the FINFET Operates 13
4.5. Symbols of MOSFET and FinFET 14-15

4.6. COMPRASION OF Multi Threshold CMOS AND 16

FINFET PROPERTIES
Chapter-5 MultiThreshold FinFet Based D-FlipFlop 17

5.1. MULTI THRESHOLD LOGIC 18-19

5.2. MultiThreshold FinFet Based D-FlipFlop Circuit Diagram 20

5.3. D-FLIPFLOP 21
5.4. METHODOLOGY 22-23
Chapter-6 RESULTS 24

6.1. MULTI-THRESHOLD FINFET BASED D-FLIP FLOP 24

WAVEFORMS
6.2. TRUTH TABLE 25

6.3. Delay and Power Calculations of Multi-Threshold D Flip- 26

Flop

CONCLUSION 27

REFERENCES 28

APPENDIX : BASE PAPER 29

APPENDIX : OPERATION 30

CO-PO AND PSO MAPPING TABLE 29-32

PROJECT EVALUATION RUBRICS 33-34
BIO-DATA OF TEAM MEMBERS 35-39

IX
 ABSTRACT

The design of a D flip-flop optimized for high-speed operation and low power consumption using
FinFET technology. The proposed approach leverages the Multi-Threshold FinFET (MTF)
technique, which strategically employs transistors with varying threshold voltages to strike a
balance between performance and energy efficiency. A key focus of the design is the reduction of
subthreshold leakage power, achieved by incorporating high-threshold voltage transistors to control
sleep and sleep-bar signals. When the circuit enters a low-power mode—indicated by an active
sleep signal and inactive sleep-bar—the lowthreshold voltage path is effectively shut off,
preventing unnecessary current flow. During normal operation, the signals are managed to ensure
full functionality and performance. The design is modeled and evaluated using Cadence tools with
18nm technology, and simulation results confirm its ability to minimize power dissipation without
compromising operational speed.

X
 LIST OF ABBREVIATIONS

Abbreviation Full Form

MOSFET - Metal Oxide Semiconductor Field Effect Transistor

FinFET - Fin Field Effect Transistor

CMOS - Complementary Metal-Oxide-Semiconductor

MTCMOS - Multi-Threshold CMOS

MT-FinFET - Multi-Threshold FinFET

DFF - D Flip-Flop

PDK - Process Design Kit

PVT - Process, Voltage, Temperature

LVS - Layout Versus Schematic

DRC - Design Rule Check

PDP - Power Delay Product

V_t - Threshold Voltage

SL / SL′ - Sleep / Complement Sleep Signals

CLK - Clock

sp / spb - Sleep Bar / Complement Sleep Bar

ADE - Analog Design Environment (Cadence)

XI
 LIST OF FIGURES

Figures Description Page No.

Figure.4.1 N-channel MOSFET 12

Figure.4.2 P-channel MOSFET 12

Figure.4.3 p-Mos Depletion Mode 12

Figure.4.4 n-Mos Depletion Mode 12

Figure.4.5 Structure Of Fin Field Effect Transistor (FET) 13

Figure4.6 MOSFET symbols 14

Figure.4.7 FINFET symbols 15

Figure.4.8 COMPRASION OF Voltage’s in CMOS AND FINFET 15

Figure.5.1 Basic Multi Threshold Circuit 16

Figure.5.2 Block Diagram 17

Figure.5.3 MultiThreshold FinFet Based D-FlipFlop 18

Figure.5.4 Schematic of MultiThreshold FinFet based D Flip-flop in Cadence Tool 19

Figure.5.5 Simulation setup of Schematic Diagram 20

Figure.6.1 Transient response of MultiThreshold FinFet Based Data Flip-Flop 23

Figure.6.2 MT FinFet-based data flip-flop's Total Average Power of transient 24

analysis

XII
 LIST OF TABLES

Tables Description Page No.

Table. 3.1 Power Gating Modes for Logic Blocks 9

Table. 6.1 Switching action of FinFet Transistors 24

Delay and Power Calculations of

Table. 6.2 25
MultiThreshold – Data flipflop

XIII
 CHAPTER - I
INTRODUCTION
1.1. Introduction for Mt-Finfet based D-FlipFlop

In modern VLSI systems, the demand for high-performance yet energy-efficient designs is ever-
increasing, particularly with the rise of portable electronic devices, AI accelerators, and edge
computing hardware. As clock frequencies increase and feature sizes shrink, flip-flops—being
fundamental sequential elements—play a critical role in determining the power and speed
performance of a digital circuit. Among the various challenges in deep sub-micron technologies,
reducing power consumption without compromising speed remains a primary design concern.

This paper focuses on the design and analysis of a low-power and high-speed data flip-flop (DFF)
architecture using multi-threshold voltage (MTCMOS) techniques implemented with 18nm FinFET
technology. FinFETs, with their superior short-channel control and reduced leakage compared to
planar CMOS, offer an effective platform for exploring advanced flip-flop designs in sub-20nm
nodes.

The proposed design leverages the multi-threshold approach, which integrates both high-Vt
(threshold voltage) and low-Vt transistors in a strategic manner to balance speed and leakage power.
High-Vt transistors are used in non-critical paths to reduce static power, while low-Vt transistors
are deployed in critical timing paths to maintain high-speed performance. This hybrid technique
allows the flip-flop to operate efficiently under aggressive technology scaling.

A comprehensive simulation and analysis of the proposed flip-flop architecture are performed using
industry-standard EDA tools. The design is benchmarked against conventional D flip-flops and
other state-of-the-art low-power variants. Key performance metrics such as power consumption,
propagation delay, power-delay product (PDP), and setup/hold time violations are evaluated.

Results indicate that the proposed flip-flop achieves significant reductions in dynamic and leakage
power while preserving or even improving switching speed. The adoption of FinFET-based
MTCMOS provides not only a scalable solution but also ensures robustness under process
variations and reduced supply voltages—making it ideal for next-generation low-power VLSI
systems.

Moreover, the proposed design is particularly suitable for clock distribution networks and register
files, where power efficiency is critical due to high toggle rates and dense integration. The energy-
saving advantages are especially beneficial in battery-operated devices and ultra-low-power SoCs.

In summary, the combination of FinFETs with multi-threshold design strategies yields a promising
path forward for energy-efficient and high-performance sequential elements. The presented flip-
flop architecture sets the stage for further innovations in low-power design methodologies targeting
nanometer-scale technologies.

1
1.2. PROJECT OVERVIEW
This project , titled “Low Power and High-Speed Multi-Threshold data flip flop design with 18nm
FINFET technology” .The primary goal of this project is to design and implement an energy-
efficient, high-performance data flip-flop (DFF) using Multi-Threshold CMOS (MTCMOS)
techniques within the 18nm FinFET technology node. The design aims to achieve an optimal
balance between speed and power consumption, making it suitable for next-generation low-power
VLSI systems.
• Problem Addressed: Traditional CMOS circuits suffer from high power dissipation,
increased leakage current, and reduced efficiency at smaller node sizes.

• Technology Used: FinFET (18nm) and CMOS (90nm) are compared, with FinFET
providing better electrostatic control, reduced leakage power, and higher speed.

• Circuit Design: The design of an D-FlipFlop using 18nm FinFET technology with
Multithreshold logic, offers significant advantages over traditional MOSFET designs.
Multithreshold logic will help reduce power consumption, minimize leakage, and boost
switching speed.
• Simulation Tools: The Cadence Virtuoso EDA tool is used for designing and analyzing
circuit performance.

1.3. OBJECTIVES
The primary objective of this project, titled " Low Power and High-Speed Multi-
Threshold data flip flop design with 18nm FINFET technology," is to develop an
efficient multi threshold design that leverages advanced transistor technologies to enhance
power efficiency, speed, and performance.

1.3.1. Design and Implementation

• To design a novel multi-threshold data flip-flop architecture optimized for both low power
and high speed.
• To implement the proposed flip-flop using 18nm FINFET technology, leveraging its
advanced performance and leakage reduction capabilities.
• To integrate power gating and clock gating techniques in the flip-flop architecture for further
power optimization.

1.3.2. Performance Evaluation and Comparison

• To evaluate the performance of the proposed flip-flop in terms of power consumption, delay,
area, and energy efficiency.
• To compare the proposed design with existing conventional flip-flops (e.g., standard
CMOS, dynamic flip-flops) under the same technology node.
• To assess improvements in speed and power performance due to the use of multi-threshold
logic and FINFET structure.

1.3.3. Optimization of Power Consumption and Speed

2
 • To optimize the threshold voltages and transistor sizing for balancing power and
performance.
• To minimize dynamic and static power consumption through architectural and circuit-level
techniques.
• To reduce clock-to-Q delay and setup time while maintaining robustness against process
variations.

1.3.4. Technology Feasibility for Low-Power Applications

• To explore the suitability and scalability of 18nm FINFET technology for ultra-low-power
applications like IoT, wearables, and biomedical devices.
• To analyze the leakage characteristics and short-channel effects handled by FINFETs in the
proposed design.
• To validate the compatibility of multi-threshold techniques with FINFET-based design
flows.

1.3.5. Simulation and Validation

• To perform pre-layout and post-layout simulations using industry-standard EDA tools such
as Cadence Virtuoso, Synopsys HSPICE, or Mentor Graphics.
• To validate the functionality, power, and timing metrics under different process corners and
operating conditions.
• To verify the flip-flop’s performance using parametric sweeps and Monte Carlo simulations
for variation analysis.

6. Significance and Scope of the Project

The rapid advancement in semiconductor technology has driven the need for circuits that are not
only faster but also more power-efficient. Flip-flops, being fundamental elements in digital circuits,
play a crucial role in determining both the performance and power consumption of modern
integrated circuits (ICs). In high-performance applications like processors, digital signal processors
(DSPs), and low-power IoT devices, the optimization of flip-flop design becomes critical.

This project addresses the growing demand for low-power and high-speed operation by leveraging
Multi-Threshold CMOS (MTCMOS) design techniques along with 18nm FinFET technology.
MTCMOS allows better control over leakage currents by using transistors with different threshold
voltages, enabling power gating and fine-grained performance tuning. FinFETs, being 3D
transistors, significantly reduce short-channel effects and provide better control over the channel,
leading to enhanced speed and energy efficiency compared to traditional planar CMOS.

1.4. Significance of the Project

• Reduction in dynamic and static power consumption, which is critical for battery-
powered and thermally sensitive devices.

3
 • Improved switching speed and timing characteristics, ensuring better performance in
high-frequency applications.

• Scalability to future technology nodes, enabling this design to be adaptable for next-
generation systems-on-chip (SoCs).

• Enhancing the reliability and energy efficiency of VLSI designs without compromising
performance.

1.5. Scope of the Project

This project focuses on the design and implementation of a low-power, high-speed data flip-flop
utilizing multi-threshold CMOS (MTCMOS) techniques in 18nm FinFET technology. The aim is
to optimize power efficiency and performance two critical parameters in modern VLSI design by
leveraging the benefits of FinFETs and multi-threshold voltage design methodologies.

Technology Exploration and Comparison: The project explores the integration of

MTCMOS techniques with FinFET transistors at the 18nm technology node. This includes
analyzing how varying threshold voltages affect power consumption and switching speed.The
performance (delay, power, area) of the proposed flip-flop design is compared with traditional
CMOS-based and single-threshold FinFET designs to highlight improvements in energy efficiency
and speed.

Applications in Real-World Scenarios: The designed flip-flop is applicable in high-

performance CPUs where speed and power efficiency are critical, especially in clock distribution
and pipeline stages.Due to its low-power characteristics, the design is suitable for energy-sensitive
applications such as mobile devices, wearable electronics, and IoT edge devices.

Scope for Future Research: Future work can explore how the same multi-threshold design
strategies can be adapted and optimized for more advanced nodes like 10nm, 7nm, or even 5nm
technology, considering increasing variability and short-channel effects. In Further power
optimization can be achieved by integrating the flip-flop design with advanced dynamic power
management techniques such as fine-grain clock gating and block-level power gating.

4
 CHAPTER – 2
LITERATURE SURVEY
The Low Power and High-Speed Multi-Threshold data flip flop design with 18nm FINFET
technology require an in-depth review of prior research. The following literature provides insights
into various aspects relevant to this project:

[1] B. Bapuji, P. Surabhi, B. Sridhar, A. Rakesh, and C. Venu, "Low Power and High-Speed
MultiThreshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using
EDA Tools," TVLSI-00380-2024, pp. 1-6, 2024.

Bapuji et al. [1] proposed a low-power and high-speed multi-threshold CMOS (MTCMOS) data
flip-flop design validated on the 90nm technology node. Their work demonstrates the effectiveness
of threshold voltage control in minimizing leakage and optimizing delay. While this study focuses
on older planar CMOS technology, it provides foundational insights into the advantages of multi-
threshold techniques, which this project builds upon by advancing the design using 18nm FinFET
technology is a more modern, three-dimensional transistor structure with better electrostatic control
and reduced leakage.

[2] S. Malipatil and A. Patil, "Design of a Low Power Flip-flop Using MTCMOS Technique
in Cadence Tool," Int. J. Ethics Eng. Manag. Educ., vol. 1, no. 4, pp. 333-335, Apr. 2014.

Malipatil and Patil [2] designed a low-power flip-flop using the MTCMOS technique in the
Cadence tool suite, focusing on practical implementation and simulation-level results. Their design
emphasized leakage reduction during idle states, showcasing how MTCMOS can be effectively
applied even in older technology nodes.Building on these foundational studies, the current project
explores the integration of MTCMOS principles with 18nm FinFET technology, aiming to combine
the power-saving capabilities of MTCMOS with the speed and efficiency benefits of FinFETs for
modern nanoscale VLSI applications.

[3] K. Liaa, X. Cui, N. Liaa, and T. Wang, "Design of D flip-flops with low power-delay
product based on FinFET," in Proc. ICSICT, Guilin, China, 2014, pp. 1-6. doi:
10.1109/ICSICT.2014.

More aligned with nanoscale FinFET processes, Liaa et al. [3] proposed a low power-delay
product D flip-flop design using FinFET technology, which highlights the performance benefits
of FinFETs over planar CMOS, particularly in sub-22nm regimes. Their work serves as a valuable
benchmark for FinFET-based sequential circuits and illustrates the importance of 3D transistor
structure in achieving high speed and low leakage.

[4] M. Sowmya, A. Divya, D. Sudharsan, and T. Ramyah, "Design of D-Flip Flop using
MTCMOS Technique," Int. J. Innov. Res. Sci. Technol., vol. 1, no. 12, pp. 141-144, May 2015.

5
Sowmya et al. [4] extended MTCMOS applications by designing a D flip-flop architecture
specifically optimized for power savings without compromising timing performance. Their
research supports the growing relevance of MTCMOS in clocked sequential circuits.

[5] S. Shivali, S. Sharma, and A. Dev, "Energy Efficient D Flip-Flop using MTCMOS
Technique with Static Body Biasing," Int. J. Recent Technol. Eng. (IJRTE), vol. 8, no. 1, pp.
1696-1698, May 2019.

Shivali et al. [5] presented a novel approach for designing an energy-efficient D Flip-Flop by
employing the Multi-Threshold CMOS (MTCMOS) technique integrated with static body biasing.
The study aimed to reduce leakage power, a major concern in modern CMOS technologies,
especially as device dimensions scale down. MTCMOS technology utilizes transistors with
different threshold voltages high-threshold transistors for sleep transistors to minimize leakage
during standby, and low-threshold transistors for logic to maintain performance.In their work, the
authors incorporated static body biasing to further optimize the threshold voltages, thereby
enhancing leakage control without significant performance penalties. The proposed design was
implemented and compared with conventional D Flip-Flops. Simulation results demonstrated a
considerable reduction in leakage power and overall energy consumption, validating the
effectiveness of the MTCMOS technique combined with static body biasing.

[6] M. U. Kiran, K. Revanth Reddy, V. S. Nithin, B. Srikanth and P. Ramakrishna, "A

Conditional Feedthrough Pulsed Flip-Flop using MTCMOS Technique," 2023 4th
International Conference for Emerging Technology (INCET), Belgaum, India, 2023, pp. 1-5,
doi: 10.1109/INCET57972.2023.10170439.

Kiran et al. [6] proposed a Conditional Feedthrough Pulsed Flip-Flop (CFP-FF) design utilizing the
MTCMOS (Multi-Threshold CMOS) technique to enhance power efficiency in sequential circuits.
The study primarily focused on addressing the challenges of dynamic power consumption and
leakage current in conventional pulsed flip-flop architectures. By integrating conditional
feedthrough logic with MTCMOS, the authors aimed to achieve a balance between speed, area, and
power performance.The CFP-FF architecture was designed to allow signal propagation only under
specific conditions, reducing unnecessary transitions and hence dynamic power dissipation.
MTCMOS technology was employed to manage leakage power effectively by using high-threshold
transistors in non-critical paths and low-threshold transistors in performance-critical sections. This
dual-threshold approach helped achieve significant power savings during both active and standby
modes.

[7] G. Shanthi, G. Sainath, N. Ashwini, P. G. Sai, P. A. Kumar and S. N. Leela, "Design and
Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double
Gate FinFET Technology," 2024 5th International Conference for Emerging Technology
(INCET), Belgaum, India, 2024, pp. 1- 6, doi: 10.1109/INCET61516.2024.10593607.

Shanthi et al. [INCET 2024] explored the design and implementation of high-speed, low-power D
Flip-Flops and digital counters using Double Gate FinFET technology, a prominent solution in sub-
20nm design nodes. Recognizing the limitations of traditional CMOS devices in terms of short-
channel effects and leakage power, the authors leveraged the superior electrostatic control of
Double Gate FinFETs to enhance both performance and energy efficiency.The proposed D Flip-

6
Flop architecture was optimized for high-speed operations while minimizing power consumption,
making it suitable for next-generation digital systems. By employing FinFETs, which offer reduced
threshold voltage variation and lower leakage currents, the design demonstrated significant
improvements in timing metrics (e.g., reduced setup and hold times) and power dissipation
compared to planar CMOS-based counterparts.

[8] S. A. Tawfik and V. Kursun, "Multi-Threshold Voltage FinFET Sequential Circuits,"

IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 151-156, Jan. 2011, doi:
10.1109/TVLSI.2009.

Tawfik and Kursun [6] investigated the application of Multi-Threshold Voltage (MTCMOS)
techniques in FinFET-based sequential circuits, addressing key concerns in ultra-deep
submicron technologies such as leakage power and scalability. As FinFETs emerged as a
promising alternative to traditional bulk CMOS, the study emphasized leveraging their inherent
advantages such as better control over short-channel effects and reduced leakage currents while
combining them with multi-threshold design strategies to further optimize power efficiency in
sequential elements like flip-flops.

[9] T. Alam, T. T. Hossain, T. H. Saika, and S. Nishat, "Novel architecture of a low power D
flip-flop based compact frequency divider for wideband PLL applications," 2024 IEEE
International Conference on Power, Electrical, Electronics and Industrial Applications
(PEEIACON), Rajshahi, Bangladesh, 2024, pp. 191–196, doi:
10.1109/PEEIACON63629.2024.10800452.

Alam et al. present a novel low-power D flip-flop architecture designed specifically for use in
compact frequency dividers, particularly for wideband phase-locked loop (PLL) applications. The
proposed design emphasizes both area efficiency and low power consumption, making it highly
suitable for PLLs used in communication systems and frequency synthesizers. The authors address
traditional flip-flop limitations such as high clock loading and unnecessary transitions, proposing
modifications that significantly reduce dynamic power. Simulation results demonstrate improved
power savings and reliable operation at high frequencies, highlighting the design’s potential for
integration in wideband RF systems.

[10] M. H. Aung and T. T. Hla, "A comparative study of D-type flip-flop architecture using
90-nm and 45-nm CMOS technology for high-performance and low-power systems," 2024
IEEE Conference on Computer Applications (ICCA), Yangon, Myanmar, 2024, pp. 1–6, doi:
10.1109/ICCA62361.2024.10532986.

Aung and Hla provide a comparative analysis of D-type flip-flop architectures implemented using
two different CMOS technology nodes: 90 nm and 45 nm. The study focuses on evaluating how
technology scaling impacts performance, delay, and power consumption. The authors compare
several popular flip-flop designs using both technology nodes and present their findings based on
simulation data. Results show that while 45 nm technology generally offers better performance and
reduced dynamic power due to smaller transistor sizes, it also introduces challenges like increased
leakage currents. This paper is valuable for understanding the trade-offs involved in technology
scaling for flip-flop-based systems in high-performance, low-power VLSI designs.

7
[11] M. U. Kiran, K. Revanth Reddy, V. S. Nithin, B. Srikanth, and P. Ramakrishna, "A
conditional feedthrough pulsed flip-flop using MTCMOS technique," 2023 4th International
Conference for Emerging Technology (INCET), Belgaum, India, 2023, pp. 1–5, doi:
10.1109/INCET57972.2023.10170439.

Kiran et al. introduce a pulsed flip-flop desi=gn that employs a conditional feedthrough
mechanism along with Multi-Threshold CMOS (MTCMOS) technology. This combination is
used to minimize both dynamic and static power consumption. MTCMOS helps reduce leakage
power by turning off unused circuit blocks during idle periods, while the feedthrough and pulse-
triggered operation help achieve faster clock-to-Q delays and minimize internal transitions. The
proposed design is shown to be superior to traditional flip-flops in terms of power-delay product
(PDP), making it highly effective for power-sensitive digital applications such as portable
electronics and battery-operated devices.

8
 CHAPTER-3

PROPOSED METHOD
3.1. Introduction to the Proposed Method

The proposed work focuses on the design and implementation of a D-type flip-flop using Multi-
Threshold FinFET (MT-FinFET) technology. The main objective is to develop a circuit that offers
low power consumption during idle states and high-speed operation during active states. This is
achieved by strategically integrating FinFET devices with varying threshold voltages and
leveraging the advantages of power gating. The design is implemented using Cadence Virtuoso
EDA tools at the 18nm technology node.

As modern VLSI systems operate under strict power and performance constraints, the integration
of FinFET devices and multi-threshold techniques presents a promising solution to mitigate sub-
threshold leakage and enhance circuit efficiency.

3.2. Overview of Multi-Threshold FinFET Technique

The proposed design utilizes Multi-Threshold CMOS (MTCMOS) principles, adapted for FinFET
technology. In traditional CMOS scaling, reducing the threshold voltage (V_th) leads
to exponential increases in sub-threshold leakage current. MT-FinFET addresses this by
incorporating transistors with:

• High Threshold Voltage (HVT): These devices offer low leakage but slower performance.
They are placed at the power supply (V_DD) and ground (GND) paths as sleep
transistors, effectively cutting off leakage during idle periods.

• Low Threshold Voltage (LVT): These transistors enable faster switching and are used in
the active data path of the flip-flop.

The dynamic control of these transistors based on sleep (SL) and sleep-bar (SL′) signals allows
the circuit to switch between power-efficient and performance-driven states.

3.3. Circuit Design Architecture

The core of the proposed D flip-flop is built using a compact 5-transistor (5T) structure optimized
for both area and performance. The schematic includes:

• One high-V_th PMOS FinFET (sleep transistor) connected between the power
rail (V_DD) and the logic core.

9
 • One high-V_th NMOS FinFET (sleep transistor) placed between the logic core
and ground (GND).

• A data-driven logic circuit consisting of low-V_th FinFETs forming the main

flip-flop structure.

• Control signals SL (Sleep) and SL′ (Sleep-bar) that determine the power mode of the
circuit.

This design ensures the low-V_th logic block is isolated from power and ground during
idle conditions, significantly reducing leakage currents.

Mode Sleep Sleep- Description

(SL) bar
(SL′)
Sleep Mode 0 1 Both power and ground are cut off via high-V_th
transistors. Sub-threshold leakage is minimized.
Active Mode 1 0 High-V_th transistors are ON. Low-V_th
logic is powered and operational at high speed.
Table-3.1: Power Gating Modes for Logic Blocks

This dual-mode operation provides a substantial power-saving advantage during standby periods
while maintaining performance integrity during switching events.

3.4. FinFET Advantages in This Design

The proposed circuit utilizes FinFETs in place of traditional planar CMOS due to several inherent
advantages:

• Better electrostatic control over the channel via dual-gate architecture.

• Reduced short-channel effects, crucial at sub-20nm technology nodes.

• Higher ON-current (I_ON) and lower OFF-current (I_OFF)

compared to CMOS.

• Faster switching and lower dynamic power consumption.

The three operational modes of FinFETs—Independent Gate (IG), Shorted Gate (SG), and Low
Power (LP)—also provide additional flexibility, though the proposed design operates primarily in
SG-mode for stronger drive capability.

10
3.5. Implementation Using Cadence EDA Tools

The entire design flow was implemented in Cadence Virtuoso, targeting the 18nm technology node.
The following steps were involved:

3.5.1. Schematic Design

A schematic was developed based on the described architecture, integrating FinFET P-type and N-
type devices with different V_th values. The sleep and sleep-bar control logic was
designed for proper power gating behavior.

3.5.2. Simulation and Functional Verification

The design was simulated under different supply voltages (1V, 0.8V, 0.6V) to assess:

• Transient behavior of Q and Q′ outputs.

• Propagation delay during data transitions.

• Leakage and dynamic power consumption.

The simulations validated the correct operation of the flip-flop and its capability to operate reliably
in both active and sleep states.

3.6. Summary

The proposed Multi-Threshold FinFET-based D flip-flop effectively integrates advanced transistor

technology, power-aware design techniques, and CAD simulation validation to meet modern digital
system demands. It offers a practical, energy-efficient solution that does not compromise on
performance and is highly suitable for integration into larger VLSI subsystems and power-critical
applications.

11
 CHAPTER – 4

MOSFET AND FINFET

4.1.MOSFETstructure
One essential part of contemporary electronics is the Metal-Oxide-Semiconductor Field-Effect
Transistor (MOSFET). In integrated circuits, this kind of transistor is employed for switching and
amplification. The operation of the MOSFET is determined by a number of essential components.
➢ The substrate (body): The silicon substrate that the MOSFET is constructed on provides the
framework. The type of MOSFET (NMOS or PMOS) will determine whether this substrate is p-
type or n-type.
➢ The source and drain are two areas of the substrate that are highly doped. The source and drain
of a PMOS are p-type, but in an NMOS they are n-type. The charge carriers enter through the source
and escape through the drain.
➢ Channel: The area where current flows between the source and drain. When voltage is given to
the gate, a channel is created that permits charge carriers to flow from source to drain.
➢ Gate: A conductive layer positioned above the channel, often made of metal or polysilicon. The
gate modifies the channel conductivity to determine whether the MOSFET is ON or OFF.
➢ Gate oxide is a very thin layer of insulating material that separates the gate from the channel. It
is usually silicon dioxide, or SiO₂. This layer permits an electric field to regulate the channel
conductivity while blocking direct current flow between the gate and the channel.
➢ Drain-Source Current: A conductive channel is formed between the source and drain when a
voltage is supplied to the gate, creating an electric field that attracts charge carriers. When there is
a voltage differential between these terminals, current can flow.
➢ Bulk/Body Terminal: The body (bulk) terminal is the MOSFET's fourth terminal.
In order to prevent undesirable effects, it is often connected to the source in most applications.
➣ Because of its quick switching speed, low power consumption, and scalability in contemporary
semiconductor devices, the MOSFET is frequently employed.
4.2.MOSFEToperation
When a voltage is applied to the gate of a MOSFET, an electric field is produced. The conductivity
between the source and drain is modulated by this field.
➢ When the MOSFET is in the OFF state (Gate = 0V), no current is flowing from the source to the
drain.

12
➢ ON State (Gate = Positive for nMOS, Negative for pMOS): Current flows because the gate
voltage draws charge carriers, which are holes for pMOS and electrons for nMOS, creating a
conductive channel between the source and drain.
➢ A positive gate voltage activates the n-channel MOSFET (MOS), which uses electrons as charge
carriers.
➢ A negative gate voltage activates the pMOS (p-channel MOSFET), which uses holes as charge
carriers.

Figure.4.1. N-channel MOSFET. Figure.4.2. P-channel MOSFET.

Figure.4.3. p-Mos Depletion Mode Figure.4.4. n-Mos Depletion Mode

4.3.FinFETStructure
The FinFET, or Fin Field-Effect Transistor, is a contemporary transistor type utilized in cutting-
edge semiconductor technology. By lowering power leakage and improving channel control, it gets
around the drawbacks of conventional MOSFETs.
➢ The fin-shaped channel of the FinFET is its most distinguishing characteristic. A thin, vertical
silicon "fin" distinguishes a FinFET from a traditional MOSFET, in which the channel is flat on the
silicon substrate. The conducting path from the source to the drain is this fin.
➢ The top, left, and right sides of the gate in FinFET are wrapped around the fin. Leakage currents
are avoided and energy efficiency is increased thanks to the tri-gate structure's greater electrostatic
control over the channel.

13
 Figure.4.5. Structure Of Fin Field Effect Transistor (FET)

(i) Planar MOSFET: A conventional single-gate MOSFET with a flat construction is called a
planarMOSFET.
(ii) Double-Gate MOSFET: A MOSFET with two gates that improves electrostatic control over
the channel is called a double-gate MOSFET.
(iii) FinFET (Fin Field-Effect Transistor): A 3D MOSFET with a gate that encircles a fin-like
structure to enhance performance and minimize leakage is called a FinFET (Fin Field-Effect
Transistor).
FinFET is made up of several essential parts:
Fin (Channel): A thin, vertical silicon fin that conducts electricity is called a fin (channel).
Gate: Enhances control by encircling the fin on three sides.
Source and Drain: Located at the fin's ends, these components permit electron passage.
Gate Oxide: Between the gate and fin is a small layer of insulating material called gate oxide.
Substrate: The silicon foundation upon which the transistor is constructed is known as the
substrate.
FinFETs are perfect for smaller technology nodes because the gate minimizes short-channel effects
by covering the fin on numerous sides. (for example, 7 nm and lower).

4.4. Howt the FINFET Operates

A sophisticated kind of transistor called a FinFET (Financial Field-Effect Transistor) was created
to get around the drawbacks of conventional MOSFETs. It functions by increasing performance,
decreasing leakage, and strengthening channel control.
➣ There is no voltage applied to the gate while the transistor is off. Current cannot flow because
the channel between the source and drain is still non-conductive. Compared to planar MOSFETs,
the fin-shaped construction reduces leakage currents.

➢ A voltage is applied to the gate when the transistor is turned on. Charge carriers, such as electrons
in an n-channel FinFET or holes in a p-channel FinFET, are drawn into the fin by the electric field
produced by this voltage. The gate offers improved channel control and enables effective transistor
switching since it encircles the fin on three sides.
➣ By decreasing short-channel effects that result in power leakage in smaller transistors, the tri-
gate arrangement enhances electrostatic control. Because of their increased performance and
decreased power consumption, FinFETs are perfect for low-power devices and contemporary
processors.

14
4.5. Symbols of MOSFET and FinFET

Figure.4.6. MOSFET symbols.

Figure.4.7. FinFET Symbols.

• FinFETs have two gates (a front gate and a back gate) for improved control, whereas MOSFETs
only have one.
• FinFETs employ several gates but lack an explicit bulk, while MOSFETs have a bulk (B)
terminal.
• Current travels vertically up the fin of FinFETs as opposed to a planar channel in MOSFETs.
• FinFETs offer superior channel control, yet MOSFETs and FinFETs both feature Source (S) and
Drain (D) connections.
• MOSFETs are shown more simply, whereas FinFETs feature more complex circuit diagrams
with extra gate terminals (FG & BG).

15
4.6. COMPRASION OF Multi Threshold CMOS AND FINFET PROPERTIES

Figure.4.8. COMPRASION OF Voltage’s in CMOS AND FINFET

In the simulation environment, the CMOS-based multi-threshold D flip-flop was configured with a
supply voltage of 14V, whereas the FinFET-based counterpart operated correctly at just 4V. This
variation is due to the intrinsic properties of the two technologies. CMOS devices typically require
a higher operating voltage to overcome their higher threshold voltages and drive strength
requirements. In contrast, FinFETs offer superior electrostatic control and reduced short-channel
effects, enabling them to function efficiently at significantly lower voltages. Despite the difference
in supply levels, both circuits exhibited correct functionality as validated through waveform
analysis, demonstrating reliable output transitions in sync with clock signals. This confirms that the
multi-threshold FinFET-based D flip-flop is not only functionally accurate but also more power-
efficient, making it a suitable candidate for low-power VLSI designs.

16
 CHAPTER – 5
Multi Threshold FinFet Based D-Flip Flop
5.1. MULTI THRESHOLD LOGIC

CMOS technology scaling results in lower supply and threshold voltages. An exponential rise in
the sub-threshold leakage current occurs as threshold voltages are lowered. In contemporary high-
performance integrated circuits, leakage currents have the potential to consume almost 40% of the
total active mode energy.CMOS technology with multiple thresholds has two primary
characteristics. In order to manage power effectively, MultiThreshold FinFet technology is linked
to both "active" and "sleep" operating modes. Secondly, N channel and P channel MOSFETs are
implemented on a single chip using two distinct threshold voltages. This technique, commonly
referred to as power gating, works by disconnecting low-threshold voltage logic gates from the
power supply and ground using high-threshold voltage (high-V_t) sleep transistors that
operate in cut-off mode. This isolation effectively reduces leakage during idle periods without
affecting the normal operation of the circuit.Prevents subthreshold leakage in Sleep mode.High
speed operation with low Vth logic.Prevents sub threshold leakage in Sleepbar mode.

Figure.5.1. Basic Multi Threshold Circuit

Multi-threshold logic, often referred to as MTCMOS (Multi-Threshold CMOS) or Multi-Threshold

FinFET when applied to FinFET technology, is a power optimization technique in VLSI design
that strategically uses transistors with different threshold voltages (V_th) to balance
performance and power consumption. This methodology is especially important in modern
semiconductor technologies where leakage power has become a major concern due to aggressive
technology scaling.In traditional CMOS design, reducing the threshold voltage improves switching
speed but increases leakage current, especially subthreshold leakage. Conversely, increasing the
threshold voltage reduces leakage but degrades performance. Multi-threshold logic solves this
trade-off by integrating both low-V_th and high-V_th transistors in a single
design:

17
Low-V_th transistors are used in the critical paths of the circuit where speed is essential.
High-V_th transistors, acting as sleep transistors, are used in non-critical paths or as
power gating switches to reduce leakage during idle periods.

5.2. MultiThreshold FinFet Based D-FlipFlop Circuit Diagram

In FinFET-based design, multi-threshold logic becomes more efficient because of the FinFET’s
superior control over short-channel effects and reduced leakage compared to planar MOSFETs.
The FinFET structure, which uses a 3D fin-like channel wrapped by the gate, enhances electrostatic
control and enables more precise threshold voltage tuning.

Figure.5.2. Multi Threshold FinFet Based D-Flip Flop

The Multi-Threshold FinFET-based D flip-flop is built around a compact five-transistor core. In

this configuration, a high-threshold P-type FinFET is used as a sleep transistor connected to the
power supply, while a high-threshold N-type FinFET is placed at the ground terminal. These
transistors are controlled by a pair of complementary signals, SL and SL′. When SL is at a logic
low level and SL′ is at logic high, the high-V_t transistors effectively isolate the low-
threshold logic circuit from both power and ground, thereby minimizing leakage by halting
current flow through the main path.

5.3. D-FLIPFLOP
A D flip-flop is a fundamental digital storage element designed to hold a single bit of data. Often
called a "data" or "delay" flip-flop, it can operate in either synchronous or asynchronous modes.
In the synchronous mode, data transfer is governed by a clock signal, ensuring that changes occur

18
only at specific clock edges. In contrast, the asynchronous mode allows changes independently
of the clock. A typical synchronous D flip-flop has two main inputs: the data input (D) and the
clock signal (CLK). When the clock signal is low, the output retains its previous value, effectively
holding the data. As the clock goes high, the current input is latched and reflected at the output,
enabling controlled and predictable data storage within digital circuits.
The schematic illustrated below represents the design of a D flip-flop based on Multi-Threshold
FinFET technology.
Design and Simulation Flow for D-Flip Flop using 18nm FINFET Technology

Figure.5.3. Block Diagram

The figure above illustrates the systematic design flow adopted for the modeling, simulation, and
analysis of a D-Flip Flop using 18nm FINFET technology in the Cadence EDA environment. The
process comprises several sequential steps as follows:

1. Start

The process initiates with the definition of objectives, which in this case is the modeling and
analysis of a D-Flip Flop. This sets the foundation for selecting the appropriate tools and
technology.

2. CADENCE EDA TOOL

Cadence Electronic Design Automation (EDA) tools are employed as the primary simulation and
design platform. Cadence offers a comprehensive suite for schematic design, layout, simulation,
and verification of integrated circuits (ICs). It enables users to create and analyze circuits at various
abstraction levels, from gate-level to physical layout.

3. 18nm FINFET Technology

The circuit is designed using 18nm FINFET (Fin Field-Effect Transistor) technology. This
technology is preferred over traditional planar MOSFETs due to its improved performance, reduced
leakage currents, and enhanced scalability. A technology library supporting 18nm FINFET is
integrated within Cadence for accurate modeling.

19
4. D-Flip Flop Design

The D-Flip Flop is selected for implementation due to its fundamental role in sequential circuits
and digital storage applications. The design is carried out using the specified FINFET technology,
ensuring adherence to design rules and timing specifications.

5. Simulation and Execution

The designed circuit undergoes comprehensive simulation using Cadence tools to verify its
functionality. Transient and timing simulations are conducted to observe the behavior of the D-Flip
Flop under various input conditions. This step ensures the logical correctness and identifies any
timing violations or design flaws.

6. Calculate the Power & Delay

Post-simulation, critical performance parameters such as power consumption and propagation delay
are evaluated. These metrics are essential for assessing the efficiency and suitability of the design
for high-speed, low-power applications.

7. Stop

The process concludes with the analysis of results and documentation. Based on the outcomes,
further optimization can be considered, or the design can proceed to the next stage of integration or
fabrication.

Schematic Diagram

Figure.5.4. Schematic of Multi Threshold FinFet based D Flip-flop in Cadence Tool

20
The multi-threshold FinFET-based D flip-flop is a sophisticated digital circuit designed to enhance
efficiency and reduce power consumption in modern electronic devices. FinFET technology,
known for its ability to minimize short-channel effects, is used in this flip-flop to improve
switching performance while reducing leakage power. The circuit employs transistors with
different threshold voltages, optimizing speed and energy efficiency. This approach allows the flip-
flop to function reliably while consuming less power, making it highly suitable for applications
requiring low-power operation, such as portable electronic devices and high-performance
computing systems.
Structurally, the flip-flop consists of PMOS and NMOS transistors, specifically labeled as PM1,
PM2, PM3, PM4, NM1, NM2, NM3, and NM4, ensuring balanced functionality. These transistors
work together to facilitate proper switching behavior, enabling the storage and transfer of digital
data. The flip-flop captures input data (D) on the rising edge of the clock (clk) signal, producing
stable output (Y)that help maintain data integrity. The multi-threshold design enhances operational
efficiency by dynamically adjusting the circuit's power consumption based on the required
processing speed.
One of the significant advantages of multi-threshold FinFET technology in this flip-flop is the
reduction of leakage currents, which is a common problem in traditional CMOS-based designs. By
carefully selecting transistors with different threshold voltages, engineers can balance speed and
power efficiency, leading to optimized performance without unnecessary energy waste. This
characteristic is particularly beneficial in advanced computing systems, where power consumption
and heat dissipation must be carefully managed to ensure long-term reliability and efficiency.
In the broader context of semiconductor technology, multi-threshold FinFET-based circuits are
gaining popularity for their ability to address the limitations of traditional MOSFETs. As device
scaling continues and transistors become smaller, FinFET-based designs offer a sustainable
solution to overcome issues related to power consumption, threshold voltage variations, and
performance degradation. The multi-threshold FinFET-based D flip-flop exemplifies this
technological advancement, making it an essential component in modern digital circuits and
integrated systems.

Simulation Setup

Figure.5.5. Simulation Setup of Schematic Diagram

21
The simulation setup of the Multi-Threshold FinFET-based D flip-flop involves configuring key
parameters within Cadence Virtuoso to validate the circuit’s performance under various
conditions. The schematic diagram includes essential components such as FinFET transistors,
voltage sources, and clock signals, ensuring accurate modeling of the flip-flop’s behavior. The
setup defines input signals like the clock (CLK) and data input (D) to analyze how the flip-flop
stores and transfers information at specific clock transitions. Additionally, supply voltage
variations ranging from 0.6V to 1V are applied to study the power dissipation and delay
characteristics. Transient analysis is performed to observe the flip-flop’s response over time,
tracking output transitions and validating switching speeds. The leakage and sleep-mode
mechanism is also tested, where high-threshold FinFET sleep transistors disconnect low-threshold
voltage paths to reduce leakage power during inactive states. The simulation results provide critical
insights into the flip-flop’s energy efficiency, operational speed, and overall reliability, confirming
its suitability for high-speed and low-power digital applications.

5.4.METHODOLOGY
This section describes the thorough process used to evaluate the design of a low-power, high-speed
Data Flip-Flop (DFF) at the 18nm technology node using multi-threshold FinFET technology and
Electronic Design Automation (EDA) tools. Schematic design, simulation, layout creation, and
performance analysis are all part of the methodical procedure.

• Selection of Technology:

Process Node: To take use of the benefits of FinFETs, such as lower leakage current, improved
electrostatic control, and more scalability, the 18nm technology node was chosen.
Transistor Type: To balance speed and power consumption, multi-threshold FinFETs were
used. For low-leakage pathways, high-Vt devices were employed, while for high-speed paths, low-
Vt devices.

• Specification for Design: The goal was to use FinFET devices to develop a D-type Flip-
Flop that was tuned for fast speed and low power consumption. Key design criteria included
power dissipation, setup/hold time, propagation latency, and functional accuracy.
• Design Input and Implementation of Schematics: EDA Tool Used: Industry-
standard tools, such as Cadence Virtuoso and Synopsys Custom Designer, were used to
implement the design. Using FinFET transistors with mixed threshold voltages, a unique DFF
circuit was created. To confirm functionality, logic-level simulation was carried out.
• Transistor-Level Simulation and Optimization Tool: Spectre/HSPIC was
employed to simulate transistors at the transistor level. To guarantee robustness, simulations
were run for various PVT (Process, Voltage, Temperature) corners. Important parameters were
examined, including rise/fall times, dynamic and static power, and latency. To achieve the best
possible balance between speed and power, iterative threshold voltage tweaking was carried
out.
• DRC/LVS Checks and Layout Design: FinFET PDKs were used in Virtuoso Layout
Suite to draw the layout. Verification using Layout Versus Schematic (LVS) and Design Rule
Check (DRC) made sure the physical design followed foundry design guidelines and was in
line with the schematic. Tools such as Calibre or Assura were used to extract parasites.

22
• Simulation of Post-Layout: Parasitic effects were included in post-layout simulations. To
confirm the effect on performance parameters like power and delay, the extracted netlist was
simulated.
• Evaluation of Performance:Conventional designs and the suggested DFF design were
contrasted using:
• Average power usage as well as leaks
• Delay in propagation
• Product of Power Delay (PDP)
To emphasize advancements, a comparison between single-Vt and multi-Vt techniques was also
conducted.
• Analysis and Validation: The usage of multi-threshold FinFETs and sophisticated EDA
tools resulted in improvements in speed and power metrics in the final validated design.
To evaluate consistency and dependability, the design was examined under a variety of
switching scenarios and data patterns.

23
 CHAPTER-6

RESULTS
6.1. MULTI-THRESHOLD FINFET BASED D-FLIP FLOP WAVEFORMS

Figure.6.1. Transient response of MultiThreshold FinFet Based Data Flip-Flop

The transient simulation waveform of the Multi-Threshold FinFET (MT-FinFET) based D flip-flop
comprises three input signals and one output signal. The inputs include the Sleep Bar (sp),
Complement Sleep Bar (spb), Data (D), and Clock (clk), while the output is denoted as Y. The
sleep control signals (sp and spb) are used to activate or deactivate the high-threshold sleep
transistors, enabling power gating.

When sp = 0 and spb = 1, the circuit is in active mode, allowing the flip-flop to latch the input data
(D) on the rising edge of the clock. The output Y reflects the value of D accurately in
synchronization with the clock signal during this mode.

When the sleep control signals are toggled to sp = 1 and spb = 0, the circuit enters sleep mode,
effectively disconnecting the logic from the power rails and minimizing leakage power. The
waveform confirms correct functional behavior of the D flip-flop across various transitions,
validating the integrity of the MT-FinFET design under low-power operation at a supply voltage of
4V.

24
6.2. TRUTH TABLE

CLK I N Sleep M1 M2 M3 M4 M5 M6 M7 OUT

0 0 0 0 on on off on off on off 0

0 0 1 1 on off off off off off off 0

1 1 1 1 off on on on on on on 1

1 1 1 1 off on on off off off off 1

Table-6.1: Switching action of FinFet Transistors

The table illustrates the transistor-level switching behavior of the Multi-Threshold FinFET (MT-
FinFET) based D flip-flop under various input conditions. The control signals involved include the
clock (CLK), data input (IN), and the sleep signal (Sleep), which determines whether the circuit
operates in active or standby mode. The table tracks the ON/OFF states of internal transistors M1
through M7, and the resulting output (OUT).

Figure.6.2. MT FinFet-based data flip-flop's Total Average Power of transient analysis

The figure represents the average power consumption of the Multi-Threshold FinFET (MT-
FinFET) based D flip-flop, evaluated through transient simulation. The waveform data was
analyzed using built-in simulation tools (such as Virtuoso ADE), capturing dynamic and static
power components over multiple clock cycles.
The measured results confirm that the MT-FinFET architecture achieves significantly lower
average power consumption compared to traditional CMOS implementations due to reduced
leakage currents and better electrostatic control. This makes the MT-FinFET flip-flop highly
suitable for low-power digital applications, especially in modern VLSI designs that demand high
energy efficiency.

25
6.3. Delay and Power Calculations of Multi-Threshold D Flip-Flop

Technology Supply Voltage Delay (µs) Power

1.0 V 3.03 µs 794.3 µW

MOSFET (90 nm) 0.8 V 3.036 µs 998.6 µW

0.6 V 3.042 µs 1.166 mW

1.0 V 2.020 µs 6.448 µW

FinFET (18 nm) 0.8 V 2.024 µs 6.583 µW

0.6 V 2.028 µs 6.798 µW

Table-6.2: Delay and Power Calculations of Multi Threshold – Data flipflop

The performance of the Multi-Threshold (MT) based D flip-flop was evaluated using both
conventional MOSFET (90 nm) and FinFET (18 nm) technologies under varying supply voltages
(1V, 0.8V, and 0.6V). The analysis focused on two key metrics: propagation delay and average
power consumption.

From the simulation results, it is evident that the Multi-Threshold FinFET-based D flip-flop
outperforms the conventional 90 nm MOSFET design in both delay and power efficiency, across
varying supply voltages. The FinFET architecture exhibits superior control over short-channel
effects, which is a critical advantage at lower technology nodes like 18 nm. This control contributes
to reduced leakage current, which is one of the main sources of power dissipation in modern
integrated circuits.As observed, even when the supply voltage is scaled down from 1V to 0.6V, the
delay increase in FinFET-based D flip-flop is minimal (2.020 µs to 2.028 µs), indicating stable
switching characteristics. The results clearly show that the MT-FinFET based D flip-flop offers
substantial improvements over the traditional MOSFET counterpart. As the supply voltage
decreases, the delay increases only slightly in both technologies; however, the power consumption
in FinFET remains consistently low, in the range of 6–7 µW, while MOSFET power rises
significantly, reaching over 1 mW at 0.6V. This demonstrates the superior energy efficiency and
scalability of FinFETs, making them an ideal choice for low-power applications in advanced VLSI
circuits.

26
 CONCLUSION
The 18nm Finfet technology consumed up to 90% less power and operated 40% faster than CMOS
version. using Multi-Threshold FinFET technology at the 18nm node to create a D flip-flop
architecture with low power consumption and fast speed. FinFET transistors are utilized to improve
circuit performance because of their better electrostatic control and less short channel effects. The
design utilizes Multi-Threshold FinFET techniques to strike an optimal balance between power
efficiency and delay. To maintain high-speed operation, subthreshold leakage is minimized by
incorporating high threshold voltage transistors to control the sleep and sleep-bar signals. This
design may find value in complex VLSI applications since it maintains speed while significantly
lowering power consumption, according to simulation studies. Multi threshold FINFET based D
Flip-Flop designed with 7 Transistors is having less power consumption. The D Flip-Flop is
simulated in 18nm technology using Cadence tool. The circuits designed using Multi threshold
FINFET are suitable for high performance applications like level converters, microprocessors,
clocking systems counters, etc.

27
 REFERENCES

[1] B. Bapuji, P. Surabhi, B. Sridhar, A. Rakesh, and C. Venu, "Low Power and High-Speed
MultiThreshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using
EDA Tools," TVLSI-00380-2024, pp. 1-6, 2024.

[2] S. Malipatil and A. Patil, "Design of a Low Power Flip-flop Using MTCMOS Technique in
Cadence Tool," Int. J. Ethics Eng. Manag. Educ., vol. 1, no. 4, pp. 333-335, Apr. 2014.

[3] K. Liaa, X. Cui, N. Liaa, and T. Wang, "Design of D flip-flops with low power-delay product
based on FinFET," in Proc. ICSICT, Guilin, China, 2014, pp. 1-6. doi: 10.1109/ICSICT.2014.

[4] M. Sowmya, A. Divya, D. Sudharsan, and T. Ramyah, "Design of D-Flip Flop using
MTCMOS Technique," Int. J. Innov. Res. Sci. Technol., vol. 1, no. 12, pp. 141-144, May 2015.

[5] S. Shivali, S. Sharma, and A. Dev, "Energy Efficient D Flip-Flop using MTCMOS
Technique with Static Body Biasing," Int. J. Recent Technol. Eng. (IJRTE), vol. 8, no. 1, pp.
1696-1698, May 2019.

[6] M. U. Kiran, K. Revanth Reddy, V. S. Nithin, B. Srikanth and P. Ramakrishna, "A

Conditional Feedthrough Pulsed Flip-Flop using MTCMOS Technique," 2023 4th International
Conference for Emerging Technology (INCET), Belgaum, India, 2023, pp. 1-5, doi:
10.1109/INCET57972.2023.10170439.

[7] G. Shanthi, G. Sainath, N. Ashwini, P. G. Sai, P. A. Kumar and S. N. Leela, "Design and
Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double
Gate FinFET Technology," 2024 5th International Conference for Emerging Technology
(INCET), Belgaum, India, 2024, pp. 1- 6, doi: 10.1109/INCET61516.2024.10593607.

[8] S. A. Tawfik and V. Kursun, "Multi-Threshold Voltage FinFET Sequential Circuits," IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 151-156, Jan. 2011, doi:
10.1109/TVLSI.2009.

[9] T. Alam, T. T. Hossain, T. H. Saika, and S. Nishat, "Novel architecture of a low power D
flip-flop based compact frequency divider for wideband PLL applications," 2024 IEEE
International Conference on Power, Electrical, Electronics and Industrial Applications
(PEEIACON), Rajshahi, Bangladesh, 2024, pp. 191–196, doi:
10.1109/PEEIACON63629.2024.10800452.

[10] M. H. Aung and T. T. Hla, "A comparative study of D-type flip-flop architecture using 90-
nm and 45-nm CMOS technology for high-performance and low-power systems," 2024 IEEE
Conference on Computer Applications (ICCA), Yangon, Myanmar, 2024, pp. 1–6, doi:
10.1109/ICCA62361.2024.10532986.

[11] M. U. Kiran, K. Revanth Reddy, V. S. Nithin, B. Srikanth, and P. Ramakrishna, "A

conditional feedthrough pulsed flip-flop using MTCMOS technique," 2023 4th International
Conference for Emerging Technology (INCET), Belgaum, India, 2023, pp. 1–5, doi:
10.1109/INCET57972.2023.10170439.

28
 APPENDIX : BASE PAPER

B. Bapuji, P. Surabhi, B. Sridhar, A. Rakesh, and C. Venu, "Low Power and High-Speed
MultiThreshold CMOS-Data Flip-Flop Design Validation on 90nm Technology Node Using EDA
Tools," TVLSI-00380-2024, pp. 1-6, 2024.
DOI: 10.1109/ICIET48527.2019.9290556 (Referenced in their citations; belongs to a related study
by Rahman Khan and Uzzal on MTCMOS)

29
 APPENDIX : OPERATION
Technology Specifications and Tools Used
The design and implementation were carried out using both 90nm MOSFET and 18nm FinFET
technologies. The 18nm node was specifically chosen for its advantages, such as reduced leakage,
improved scalability, and better electrostatic control in FinFET devices.
The following tools and platforms were employed:
• Cadence Virtuoso: Used for schematic design and layout.
• Spectre Simulator: Used for transient and delay simulations.
• Assura/Calibre: Employed for Design Rule Check (DRC) and Layout Versus Schematic
(LVS) verifications.
FinFET Process Design Kits (PDKs) were utilized to accurately model and simulate the electrical
behavior of the transistors.
Circuit Configuration and Operation
The Multi-Threshold FinFET-based D Flip-Flop was designed using a compact 7-transistor
architecture, comprising:
• High-V_t PMOS (used as sleep transistor connected to VDD)
• High-V_t NMOS (used as sleep transistor connected to ground)
• Low-V_t transistors (used in the logic path for fast switching)
The control signals sp and spb regulate sleep mode operation. When sp = 0 and spb = 1, the circuit
is in active mode and functions normally. When sp = 1 and spb = 0, it enters sleep mode,
disconnecting from power and ground, thereby reducing leakage.
Simulation Setup and Parameters
The simulation setup included the design of schematic diagrams with FinFET transistors, clock,
data input, and sleep control signals. Voltage sources were applied with supply levels of 1.0V, 0.8V,
and 0.6V to evaluate the power and delay behavior under voltage scaling.
• Transient Analysis: Captured output behavior (Y) based on data input (D) and clock (CLK).
• Leakage Testing: Verified power-saving behavior during sleep mode.
• PVT Variation Testing: Simulations were conducted under different process and
temperature conditions to ensure robustness.
The Cadence ADE environment was used to collect waveforms, power data, and switching speed.

30
Transistor-Level Switching and Truth Table
A truth table was created to analyze the behavior of internal transistors (M1–M7) under different
input conditions. The table includes combinations of:
• CLK – Clock Signal
• IN – Data Input
• Sleep Signal – Activates or deactivates sleep transistors
• Transistor States – ON/OFF behavior of each transistor
• Output (OUT) – Logic output based on active mode or sleep mode
This validated the design’s ability to switch correctly during clock transitions and isolate power
during idle periods.
Performance Metrics and Power Analysis
Performance evaluation focused on key parameters:
• Propagation Delay
• Average Power Consumption
• Power Delay Product (PDP)
This data clearly demonstrates the superior efficiency of the Multi-Threshold FinFET-based design.
While the delay increased slightly with lower voltage, the power consumption remained
consistently low for FinFETs, making them ideal for low-power digital circuits.
Final Observations
The Multi-Threshold FinFET-based D Flip-Flop exhibited reliable behavior under simulation, with
clear advantages in power savings and switching speed over traditional MOSFET designs. The
architecture effectively addressed leakage power challenges while preserving data integrity and
operational accuracy. These properties make it a strong candidate for implementation in future low-
power VLSI systems, including microprocessors, digital signal processors, and energy-efficient
SoCs.

31
 CO-PO AND PSO MAPPING TABLE

Course Outcomes POs PSOs

Course PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO
No. Statements PSO3
1 2 3 4 5 6 7 8 9 0 1 2 1 2
Apply the
knowledge
C41 of
3 2 2 3
8.1 engineering
fundamental
s
Analyse the
C41 procedure
2 3 2 3 3 3
8.2 for technical
solutions
Design the
2004801
C41 system
Project 2 3 3 3 3 3 3 3 2 3 3
8.3 giving the
work /
solution
Internship
Simulate the
designed
C41
system using 2 3 3 3 2 2 3 3 3
8.4
appropriate
tool.
Present the
work done in
C41 the form of a
3 2 3 3
8.5 report and
oral
presentation

PO & PSO Mapping

Project P P P PO PO PO P PO PO PO1 PO1 PO1 PSO PSO PSO
Title O1 O2 O3 4 5 6 O7 8 9 0 1 2 1 2 3
Low Power
and High-
Speed Multi-
Threshold
data flip flop
3 3 3 2 2 2 2 2 3 2 1 2 2 2 3
design
with 18nm
FINFET
technology

Correlation levels 0, 1, 2 or 3 are defined as: 0. Nil, 1. Slight, 2. Moderate, 3. Substantial

32
 RUBRICS FOR EVALUATION
Needs
Excellent Good Satisfactory
Parameter/Marks(%) Improvement
(76%-100%) (51%-75%) (26%-50%)
(0-25%)
Topic is
Topic is
innovative, Topic is
Relevance & somewhat Topic is not
relevant, and relevant but
Innovation in Topic relevant but suitable or lacks
well-justified lacks strong
Selection (10M) needs better clarity.
with practical novelty.
justification.
applications.
Demonstrates
deep analytical Good analysis Poor analysis
Analytical Thinking & Basic analysis
thinking and with minor with no clear
Problem Interpretation but lacks depth
strong logical refinements synthesis of
(10M) and synthesis.
interpretation of needed. ideas.
the problem.
Efficient Poor problem-
Good problem- Basic
Effective Problem- problem-solving solving,
solving but implementation,
Solving & approach with incorrect or
with some lacks
Implementation (10M) optimized inefficient
inefficiencies. optimization.
implementation. implementation.
Effective and
Application of appropriate use Uses modern No or incorrect
Limited use of
Engineering of modern tools, tools but needs use of
tools, lacks
Techniques & Tools software, and better techniques and
integration.
(10M) technical optimization. tools.
methodologies.
Clearly explains
the societal
Societal Impact & benefits and Considers Basic awareness No awareness of
Responsibility in responsible impact but of impact but not how the project
Engineering (5M) application of lacks depth. well integrated. affects society.
engineering
solutions.
Strong
integration of
Some Basic awareness,
Environmental sustainability No concern for
environmental but not
Sustainability & Green principles with environmental
considerations effectively
Engineering (5M) minimal impact.
but minor gaps. applied.
environmental
impact.
Strong ethical
awareness in Ethical aspects Some ethical
Ethical Considerations No ethical
project work, considered but considerations
& Professional considerations
decision-making, with minor but not fully
Responsibility (5M) in the project.
and gaps. developed.
implementation.

33
 Needs
Excellent Good Satisfactory
Parameter/Marks(%) Improvement
(76%-100%) (51%-75%) (26%-50%)
(0-25%)
Demonstrates
strong ability for
Shows interest Limited self- No effort
Self-Learning & self-learning,
in learning but learning, depends towards learning
Research Adaptability exploring new
relies partially mostly on given beyond the
(5M) domains, and
on guidance. knowledge. syllabus.
independent
research.
Excellent Good Poor
Lacks
Presentation Skills & articulation, communication, presentation,
confidence, some
Technical confidence, and with minor unable to
difficulty in
Communication (15M) clarity in areas for explain the
conveying ideas.
explaining work. improvement. work.
Well-structured
Report is well-
report with Report lacks Poorly written
Report Writing, written but has
proper format, depth, with report, lacks
Documentation & minor
citations, clarity, missing or structure and
Formatting (15M) formatting
and professional unclear sections. clarity.
issues.
presentation.
Well-planned
execution,
Good planning
Time, Budget & optimizing time Basic planning Poor or no time
but minor
Resource Management and cost while but lacks detailed and cost
inefficiencies in
(5M) managing breakdowns. analysis.
cost or time.
resources
effectively.
Demonstrates
Shows some
commitment to
effort in Limited No effort toward
Lifelong Learning & continuous
exploring future awareness of learning or
Future Scope of Work learning and
possibilities but further learning future research
(5M) identifies future
needs or enhancements. considerations.
research
improvement.
opportunities.

HOD, ECE

34
 BIO-DATA OF TEAM MEMBERS
TEAM MEMBER-1
Personal Information
Name: Obugani Ravanamma
Father’s Name: Obugani Ramaiah
Date of Birth: 24/04/2004
Gender: Female
Nationality: Indian
Marital Status: Single
Languages Known: English, Telugu
Contact: +91-9391203257
Email: [email protected]
Address: 11-79,Gagireddy palle,B.mattam,Kadapa(dist),Andhra Pradesh,516503.
Educational Qualifications
Qualification Institution Board/University Year Percentage/CGPA
B.Tech (Electronics KSRM JNTUA University 2025 9.01 CGPA
and Communication College Of
Engineering) Engineering
Class XII Govt.Junior Board of Intermediate 2021 8.9 %
College for Education Andhra
Girls Pradesh
Class X Deepthi high Board of Secondary 2019 9.7 CGPA
School Education Andhra
Pradesh
Technical Skills
• Programming Languages: Python(Basics)
• Web Technologies: HTML, CSS
Projects
Title: Low Power and High-Speed Multi-Threshold data flip flop design with 18nm FINFET
technology
Description: A multi-threshold flip-flop designed using 18nm FINFET technology helps achieve both high
speed and low power consumption. It uses transistors with different threshold voltages to balance
performance and energy efficiency. FINFET technology improves control over leakage currents, making the
design more power-efficient compared to traditional CMOS approaches.
Achievements / Certifications
• Design and Analysis of VLSI Subsystems (NPTEL)
• Cloud computing (NPTEL)
Declaration
I hereby declare that the above information is true to the best of my knowledge.
OBUGANI RAVANAMMA

35
TEAM MEMBER-2
Personal Information
Name: Mangali janardhan
Father’s Name: Mangali Satya Narayana
Date of Birth: 30/05/2004
Gender: Male
Nationality: Indian
Marital Status: Single
Languages Known: English, Telugu
Contact: +91-7815979123
Email: [email protected]
Address: 1-125, Talamudipi,Nandyala, Andhra Pradesh,518501.
Educational Qualifications
Qualification Institution Board/University Year Percentage/CGPA
B.Tech (Electronics KSRM JNTUA University 2025 8.34 CGPA
and Communication College Of
Engineering) Engineering
Class XII Narayana Board of Intermediate 2021 91.1%
Junior Education Andhra
College Pradesh
Class X Sri Board of Secondary 2019 9.7 CGPA
Chaitanya Education Andhra
Techno Pradesh
School

Technical Skills
• Programming Languages: Python
• Web Technologies: HTML, CSS, MySQL

Projects
Title: Low Power and High-Speed Multi-Threshold data flip flop design with 18nm FINFET
technology
Description: A multi-threshold flip-flop designed using 18nm FINFET technology helps achieve both high
speed and low power consumption. It uses transistors with different threshold voltages to balance
performance and energy efficiency. FINFET technology improves control over leakage currents, making the
design more power-efficient compared to traditional CMOS approaches.

Achievements / Certifications
• Design and Analysis of VLSI Subsystems (NPTEL)
• Cloud computing (NPTEL)

Declaration
I hereby declare that the above information is true to the best of my knowledge.

MANGALI JANARDHAN

36
TEAM MEMBER-3
Personal Information
Name: Neela Jagadeesh
Father’s Name: Neela Hari Nadha
Date of Birth: 04/01/2003
Gender: Male
Nationality: Indian
Marital Status: Single
Languages Known: English, Telugu
Contact: +91-6301365568
Email: [email protected]
Address: 25-78, eguvagottiveedu, rayachoti, annamaya(dist), 516269.

Educational Qualifications
Qualification Institution Board/University Year Percentage/CGPA
B.Tech (Electronics KSRM JNTUA University 2025 8.3 CGPA
and Communication College Of
Engineering) Engineering
Class XII Sri Board of Intermediate 2020 7.7 CGPA
Chaitanya Education Andhra
boys jr Pradesh
college
Class X Sri Board of Secondary 2018 8.7 CGPA
Chaitanya Education Andhra
School Pradesh

Technical Skills
• Programming Languages: Java , Python(Basics)
• Web Technologies: HTML, CSS,SQL
Projects
Title: Low Power and High-Speed Multi-Threshold data flip flop design with 18nm FINFET
technology
Description: A multi-threshold flip-flop designed using 18nm FINFET technology helps achieve
both high speed and low power consumption. It uses transistors with different threshold voltages to
balance performance and energy efficiency. FINFET technology improves control over leakage
currents, making the design more power-efficient compared to traditional CMOS approaches.

Achievements / Certifications
• Design and Analysis of VLSI Subsystems (NPTEL)
• Cloud computing (NPTEL)
• PCB Design
Declaration
I hereby declare that the above information is true to the best of my knowledge.

NEELA JAGADEESH

37
TEAM MEMBER-4
Personal Information
Name: Nallagondu Venkata Sai Vamsi
Father’s Name: Nallagondu Ramaiah
Date of Birth: 03/08/2004
Gender: Male
Nationality: Indian
Marital Status: Single
Languages Known: English, Telugu
Contact: +91-6300323035
Email: [email protected]
Address: 1/93-A, bhakarapeta, sidhout(M), Kadapa(D),516247

Educational Qualifications
Qualification Institution Board/University Year Percentage/CGPA
B.Tech (Electronics KSRM JNTUA University 2025 6.93 CGPA
and Communication College Of
Engineering) Engineering
Class XII Sri Board of Intermediate 2021 87.7%
chaitanya jr Education Andhra
college Pradesh
Class X Gurukul Board of Secondary 2019 9.3 CGPA
vidyapeeth Education Andhra
Pradesh

Technical Skills
• Programming Languages: Python(Basics)
• Web Technologies: HTML, CSS,SQL

Projects
Title: Low Power and High-Speed Multi-Threshold data flip flop design with 18nm FINFET
technology
Description: A multi-threshold flip-flop designed using 18nm FINFET technology helps achieve both high
speed and low power consumption. It uses transistors with different threshold voltages to balance
performance and energy efficiency. FINFET technology improves control over leakage currents, making the
design more power-efficient compared to traditional CMOS approaches.

Achievements / Certifications
• Design and Analysis of VLSI Subsystems (NPTEL)
• Cloud computing (NPTEL)

Declaration
I hereby declare that the above information is true to the best of my knowledge.

NALLAGONDU VENKATA SAI VAMSI

38
TEAM MEMBER-5
Personal Information
Name: kasturi Radha Priyanjali
Father’s Name: kasturi Sudhakar
Date of Birth: 14/06/2004
Gender: Female
Nationality: Indian
Marital Status: Single
Languages Known: English, Telugu
Contact: +91-7989140022
Email: [email protected]
Address: 38/5603 ambedkar nagar,chinnachowk,Kadapa(D),516002

Educational Qualifications
Qualification Institution Board/University Year Percentage/CGPA
B.Tech (Electronics KSRM JNTUA University 2025 6.0 CGPA
and Communication College Of
Engineering) Engineering
Class XII Narayana Board of Intermediate 2021 65 %
junior Education Andhra
college Pradesh
Class X Nagarjuna Board of Secondary 2019 7.8 CGPA
high school Education Andhra
Pradesh

Technical Skills
• Programming Languages: Python(Basics)
• Web Technologies: HTML, CSS.

Projects
Title: Low Power and High-Speed Multi-Threshold data flip flop design with 18nm FINFET
technology
Description: A multi-threshold flip-flop designed using 18nm FINFET technology helps achieve
both high speed and low power consumption. It uses transistors with different threshold voltages to
balance performance and energy efficiency. FINFET technology improves control over leakage
currents, making the design more power-efficient compared to traditional CMOS approaches.

Achievements / Certifications
• Design and Analysis of VLSI Subsystems (NPTEL)
• Cloud computing (NPTEL)

Declaration
I hereby declare that the above information is true to the best of my knowledge.

KASTURI RADHA PRIYANJALI

39