0% found this document useful (0 votes)
27 views20 pages

Digital Logic

The document outlines examination questions for students at Tribhuvan University Institute of Engineering, covering topics in digital logic, including Gray code, De Morgan's theorem, K-map simplifications, circuit designs, and various types of flip-flops and counters. Candidates are instructed to provide answers in their own words and assume suitable data where necessary. The examination consists of multiple questions requiring explanations, circuit designs, and proofs related to digital electronics concepts.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
0% found this document useful (0 votes)
27 views20 pages

Digital Logic

The document outlines examination questions for students at Tribhuvan University Institute of Engineering, covering topics in digital logic, including Gray code, De Morgan's theorem, K-map simplifications, circuit designs, and various types of flip-flops and counters. Candidates are instructed to provide answers in their own words and assume suitable data where necessary. The examination consists of multiple questions requiring explanations, circuit designs, and proofs related to digital electronics concepts.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
You are on page 1/ 20
Examination Control Division sc. poe 10, 1. 12, 13. ‘TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING 2076 Chaitra Candidates are required to give their answers in their own words as far as practicable. Attempt All questions. The figures in the margin indicate Full Marks, Assume suitable data if necessary. Explain Gray code with suitable examples, State and prove the De-margin’s theorem and perform the addition (-47+27) by using 2° complement method. Simplify the function using K-map F=E (1,2,3,8,9,10,11,14) and D = 5 (0,4,12). Also realize the simplified circuit using NAND Gates. Describe the importance of parity bits in communication system. Explain 3 bits even parity generator circuit clearly. Realize a full subtractor circuit by combining only one 1:4 demultiplexer and standard gates. Explain the operation of 8:1 multiplexer with necessary diagrams. Construct 32:1 MUX using only 8:1 MUXs. Explain the serial in paraliel-out (SIPO) shift register with timing diagram of 1101 data input. Explain the operation of edge triggered J-K Flip-Flop with necessary diagram and excitation table. Differentiate between combinational and sequential logic circuits, Construct and explain mod-12 asynchronous down counter with negative edge clock triggering system. Use IK flip-flops and necessary logic gates. Design the synchronous decade counter using T flip-flop and also show its timing diagram, Explain the operation of TTL two input OR gate with schematic diagram and also define the propagation delay time and power dissipation. With the help of block diagram, explain the operation of digital frequency counter, Consider a sequential detector that receives binary data stream at its input ‘X° and signals when a serial sequence ‘101° arrives at the input by making its output’Y” high, otherwise output remains low. Design a sequence detector state machine using positive edge triggered T flip flops. one BI (343) [442] 244] [5] (343) [6] (6) [2+6) [8] [442 (4 [10] ‘TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING . be Examination Control Division | Programme | BEL, BEX, Brn 2075 Chaitra — Y Candidates are required to give their answers in their own words as far as practicable. Y Attempt AU questions. The figures in the margin indicate Full Marks, Assume suitable data if necessary. 1 . a) Explain excess-3 code with suitable examples. (2.5) b) Define combinational logic circuit. 12.5) 2. Simplify the function using K-map F=3(0,1,4,8,10,11,12) and D=¥(2,3,6,9,15). Also convert the result into only NAND gates. (6) 3. Design the operation of octal priority encoder with neat diagram. ral 4, Design a simplest logic circuit for 'b' segment of the BCD-to-7 segment display decoder. [6] Explain the operation of JK flip flop showing its logic diagram, characteristic table and then derive its characteristic equation and excitation table. {6} 6. Draw a 4 bit PISO shift register and explain its operation along with timing waveform with 1101 data load in input. [6] 7. Explain the working principle of 4 bit down asynchronous counter with neat timing diagram using negative clock edge triggering. 16] 8. Design a mod-6 synchronous counter using T Flip-Flops with timing diagrams. 7 9. Describe the voltage profile of TTL. Explain the working principle of tristate TTL inverter. [2+6] 10. Design a synchronous sequential machine such that it gives output Z=1 if input contains the sequence of message 011 and it retains in its own state in other condition giving ‘output zero, Use RS-Flip-Flop. ty 11. Draw the circuit diagram of 3 input CMOS gate and explain its operation, (6 12, Lustrate time measurement circuit with block diagram. (6) TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING [BE Examination Control Division | Programme | BEL, BE 2076 Ashwin L Y Candidates are required to give their answers in their own words as far as practicable. Y Attempt All questions. Y The figures in the margin indicate Full Marks Y Assume suitable data if necessary, 1, a) Whatis a gray code? Compare with binary numbers. GI b) List the advantages of digital signal over analog signal. B] 2. Describe De’ Morgan's laws with examples. Construct XOR gate using only 3-inputs NAND gates. [243] 3. What is a decoder? Realize a 2-to-4 line decoder as a full adder circuit. [+5] 4. Simplify the following function using K-map. And also draw reduced circuit using NOR gate y(A, B, C, D) = ITM (0,2,3,8,10,11,12,15) and d=TIM(7,13,14). [5+] 5., a) Explain the operation of two 4-bit parallel adder with neat diagram. [5] b) Realize the logic circuit of 1x16 DMUX using 1<4 DMUX and gates if necessary. B} 6. Differentiate between combination and sequential circuit. Explain briefly how latch can be used as bounce eliminator, [244] 7. Explain how 1001 data can be stored and retrieve n PISO shift register with neat diagram and truth table, 7 8. Construct a mod-12 asynchronous up counter with positive clock edge triggering Implement only T flip-flops, (3) 9. Design BCD synchronous counter with circuit diagram, truth table and timing waveform. Use T flip-flop. im 10.Draw the schematic diagram of 2-input TTL NAND gate and explain about CMOS characteristics. [442] 11. Design a sequential machine with one input x and one output z which gives output z=1 when serial input containts 1011 message. Use J-K flip-flop. 12) 12. With the help of block diagram explain the operation of frequency counter. 63) peed 7 ‘TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING =| Examination Control Division | Pr 2074 Chaitra ‘Year Y Candidates are required to give their answers in their own words as far as practicable. ¥ Attempt All questions. The figures in the margin indicate Full Marks. ¥ Assume suitable data if necessary. 1, a) Define TTL IC Signal levels for Input and Output logic with example. BI b) Convert 37.432 decimal number to binary. BI 2. a) State and prove De-Morgan’s theorems with necessary diagrams. Prove that negative logic OR Gate is equivalent to positive logic AND Gate. [442] b) What is Gray code? Explain with example. 2 3, a) Minize the expression and implement the reduced expression by using NAND gates. F=ABCD-+ ABCD +ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD [442] b) Whatido you mean by Max term? Explain with example Bl 4. Design the 32:1 Multiplexer using 4:1 multiplexers tree concept and implement the function F = ¥1(0,1,3,8,9,13) using suitable Multiplexer. [442] 5. a) Explain the operation of 3 bit magnitude comparator with truth table and draw the circuit. 15) b) Draw the circuit to add following bits 1011 and 1100. BI 6. a) Write down the drawback of SR Flip-Flop. Explain the operation of edge triggered JK Flip-Flop with timing diagram and truth table. DH] b) Explain the operation of 4 bit serial in serial out (SISO) register with timing diagram. [5] 7, Explain the operation of 3 bit Asynchronous up/down counter with timing diagram. (61 8. Design a synchronous sequential machine such that it gives output Z = 1 if input contains the message 110 and it retains in its own state for other condition giving output zero. Use EK Flip-Flop. [10] 9, What do you mean by static and dynamic hazards? Give example of static hazards and explain how do you eliminate such hazards? [442] 10. With the help of block diagram explain the operation of frequency counter. [4] 11. Draw the schematic diagram of TTL NOR gate and explain about totem pole. 6] a8 17, TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING Examination Control Division 2075 Ashwin Y Candidates are required to give their answers in their own words as far as practicable. Y Attempt All questions. Y The figures in the margin indicate Full Marks, Y Assume suitable data if necessary. . Deseribe in your own words the characteristics of an analog and a digital signal. Convert A2.64H1 into its octal and decimal equivalents. D+] 2. Explain BCD code with suitable examples. 5] 3. Simplify the funetion using K-map F=(0, 1, 4, 8, 10, 11, 12) and D=EQ, 3, 6, 9, 15). ‘Also realize the simplified circuit using NOR Gates. [442] 4, Explain the operation of octal to binary encoder with necessary diagrams. Convert A+B’C in to canonical form, (+3) 5, Describe the importance of parity bits in communication system. Explain 3 bits odd parity generator circuit clearly. B43] 6. Realize the circuit diagram for BCD decoder. Explain 1’s and 2’s complements with examples? 343] 7. Explain the operation of edge triggered S-R Flip-Flop with timing diagram and truth table. 6] 8. Design half subtractor circuit using HDL. 4 9. Define synchronous sequential circuits, Explain the operation of asynchronous mod-12 counter with necessary diagrams, [145] 10, Design a synchronous sequential machine from the state diagram given below. Use $-R Flip-Flop. 0) ee) on 4A - eee — 11, Explain the operation of 4 bit serial in parallel out (SIPO) register with timing diagram, (4 12. What is the role of hazards in asynchronous circuit design? Explain two bit magnitude comparator with necessary diagrams. [+4] 13, Draw the schematic diagram of TTL NAND gate and explain about the transistor switch. [243] 14, With the help of block diagram explain the operation of Time measuring circuit. [4] wee 27 _TRIBHUYAN UNIVERSIT SSE) INSTITUTE OF ENGINEER-NG Full Marks | 80 Examination Control Division Pass Marks |32 | 2073 Chaitra ime 3 hrs. = ‘Subject: - Digital Logic (EX502) Candidates are required to give their answers in their own words as far as practicable. Y. Aitempt All questions. Y The figures in the margin indicate Full Marks. ¥ Assume suitable data if necessary. 1. a) Define the positive logic and negative logic with examples. 2 b) Prove that NOR Gate is an universal gate. Realize EX-OR gate using only NAND gate. (61 2. Convert the decimal number 73 into gray code and perform the addition (-5+13) by using 2's complement method. [243] 3. Simplify the following funetion using K-map and implement the result using suitable gates. [442] F(A,B,C,D) = Em (7,9,12,13,14,15) +d (0,2,3,5) 4. a)» Design a circuit that compares two 4-bit numbers, A and B, to check if they are equal. ‘The circuit has one output x, so that x= 1 if A= B and x = 0 if A# B. 5] b) Implement the following function with a Multiplexer: [4] FAB,CD) = (0,1,3,4,8,9,15) 5. Define Flip-Flop. Explain the operation of positive edge trigger J-k Flip Flop with excitation table. Also derive its characteristic equation and draw state diagram. [ 1+342+2] 6. What is the difference between Asynchronous and Synchronous counter? Design Mod-13 synchronous counter using J-K flip flop and also draw its timing diagram. [2+6] 7. Explain the different types of registers with suitable block diagram. By 8. Explain the operation of 4-bit serial in serial out (SISO) shift left register with timing diagram. {61 9. Design a synchronous sequential machine such that it gives output Z = 1 ifit detects input message 011. Use D-Flip-Flop. (10) 10. What do you mean by static and dynamic hazards? Give example of static hazards and explain how do you eliminate such hazards? [2+4] 11, Draw the schematic diagram of TTL NAND gate and explain the propagation delay time. [6] 12, With the help of block diagram, explain the operation of digital frequency counter. [5] 27 ‘TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING __| BE Examination Control Division | Programme | BEL, BEX, BCT 2074 Ashwin : Year/Part_|i/T Candidates are required to give their answers in their own words as far as practicable. Attempt AU questions. The figures in the margin indicate Full Marks. Assume suitable data if necessary. v v v v + a) Explain digital wave form based on TTL compatible logic. (Both for input and output) [3] b) What is the importance of De-morgan's laws? Show how a two-input NOR gate can be constructed from a two-input NAND gate. [4] 2. Convert decimal 39 into binary and hexadecimal. Use 2'S complement method to perform the following addition (-28+17) [243] 3. Simplify the function using K-map F = )"(0,1,4,8,10,11,12) and D =23,6,9,15). Also realize the simplified logic circuit. {6 4. a) What is an encoder? Draw the logic circuit of an encoder that converts Octal number into binary. +4) b) What isa multiplexer tree? Design the 16 to 1 multiplexer using 4 to 1 multiplexer. [14] 5. What is the Setup time and hold time of a flip-flop? With the help of excitation table and K-map, convert R-S flip flop into D and J-K flip flops. [246] 6. Describe the operation of 4 bit serial in Serial Out shift register, with timing diagram. Consider the input 1011 to be entered into the register. (6) 7. List the advantages and disadvantages of a synchronous counter over asynchronous counter. Design a 3 bit synchronous counter which follow gray code sequence. [2+6] 8. Design a sequential machine that produces output Y = 1 when it detects the serial input X= 100, (10) 9. Define fan-in and fan-out with reference to TTL. With a circuit diagram explain the operation of 2-bit TTL NAND gate. [2+6] 10. Draw the block diagram with decoders to show hour, minute and second, (6) 11. Write short notes on: (any two) [23] i) Static and dynamic hazzard ii) ROM iii) DE-MUX tree one 27 ‘TRIBHUVAN UNIVERSITY Examination Control Division INSTITUTE OF ENGINEERING Level [Prosramne 2072 Chaitra ww raw Me _ Subject: Candidates are required to give their answers in their own words as far as practicable. Attempt All questions. The figures in the margin indicate Full Marks, Assume suitable data if necessary. Perform the following as indicated in the brackets: [2x4] a. (10.0101), (?)16 b, (101001001) sinay™ (Gray & 93)0= (P)excesss d (10.001),-(11.101), using 2’s complement method. a) Describe commutative and associati simplify A+A'B=A+B. ) Implement Excusive OR gate by using NAND gates only. (41 Simplify $1,2,3,89.10.113,14+d(0,4,7,12) by using K-Map and awrite its standard product of sum (POS) expression, [433] How do you design 32:1 Mux by using multiplexer tree? Implement logic function Y= ¥.m(0,1,3.8,9.13,15) by using suitable multiplexer. [443] Realize a full-subtractor using suitable demultiplexer and standard getes. (6) ‘Design a simplest logic circuit for 'b’ segment of the BCD to 7 segment decoder. m Design and draw the cireuit diagram of a3 bit gray code synchronous counter. a Draw ripple decade counter and sketch its timing diagram. {542] Draw 2-input TTL NAND gate and explain its working principle. : [5 How does second section of a digital clock work? Explain its working principle using block diagram, 1} Design a sequential machine that has a single input x’ and single output ‘2’. The machine is required to give high output when it detects the serial sequence of 011 message. Use JK flip-flops only. 112) 24 TRIBHUVAN UNIVERSITY (Exam, INSTITUTE OF ENGINEERING Level [BE Fall Marks Examination Control Division | Programme | BEL, BE 2073 Shrawan Year /Part | i/ [Near meses Ei : ~ Digital Logic (£502) __ Subjec Candidates are required to give their answers in their own words as far as practicable. Attempt All questions. The figures in the margin indicate Full Marks. Assume suitable data if necessary. S468] . a) Perform the following code conversions. [342] i) (110)gny = (aco i) (1430)10 = (2) Excess 3 b) Construct two input XOR gate using minimum number of 2-input NAND gates only. [5] 2, Implement a full adder circuit using 4:1 Multiplexers. 5) 3. Draw the circuit diagram and explain the working principle of 4-bit parallel in serial out (PISO) shift register. m 4.° Simplify, ¥51,2,38,10,13 + d(0,4,5,6,7,9,12) by using K-Map and write its standard SOP expression, (6) 5. Design 1:32 dimultiplexer tree using 1:8 DEMUXS and 1:2 DEMUXS only. 16] 6. Draw the schematic diagram of TTL Inverter. Explain the working principle of circuit. _[3+4] 7. Derive characteristic equation of a JK.flip flop. How do you make it a toggle flip flop? Draw the input and output wave form of JK flip flop. i (34242) 8. Differentiate between combinational and sequential circuits. Explain BCD-to-Decimal decoder circuit with suitable diagram. = [246] 9. Design a synchronous MOD-5 counter along with block diagram and timing diagrams. Also write the applications of counters and shift registers. 16 10. Sketch block diagram of digital frequency counter and describe its operation. 8] 11. sequential machine has to detect serial input sequance of 101, the machine output will be high. The machine contains two JK flip flops, A and B. Assume: single input, x and single output Y. 12) 27 ‘TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING Examination Control Division 2071 Chaitra Y Candidates are required to give their answers in their own words as far as practicable, ¥ Attempt All questions. V The figures in the margin indicate Full Marks, Y Assume suitable data if necessary. What is weighted code and non-weighted code? What will be the BCD, Excess-3 and Gray code for the decimal number 15? (243] 2, Perform the following addition using 2's complement -5+12 [4] 3. Implement Exclusive OR gate by using NAND gates only. B] 4, Simplify the following function using K-map and implement the result using only NOR gates. [443] F(A, B, C.D) =¥ m (, 2, 3, 5, 6, 8, 9) +d (10, 11, 12, 13, 14, 15) 5.: Design a 32:1 MUX using only 8:1 MUX. Use block diagrams. 5] 6. Design a combinational logic circuit with 3 input variables that will produce logic high output when more than one input variables are logic low. [4] 7. Show with design that a full-adder can be implemented using two half-adders. Subtract (16): from (14); using 2's complement method. (6+2] 8. Detive characteristic equation of a JK flip flop. How do you make it a toggle flip flop? Draw the input and output wave form of JK flip flop. [34242] 9. What is a Shift Register? What are its various types? List out some applications of Shift Register. [5] 10. Differentiate between synchronous and asynchronous counters. Describe the operation of asynchronous 3-bit binary down counter. [2+6] 11. Design a sequential circuit with two D flip flops and two inputs, P and Q. If P = 0, the circuit remains in the same state regardless of the value of Q. When P= 1 and Q=1, the circuit goes through the state transitions from 00 to O1 to 10 back to 00, and repeats, When P = 1 and Q = 0, the circuit goes through the state transitions from 00 to 10 to 01 back to 00, and repeats. The circuit is to be designed by treating the unused state (s) as don't care condition(s). U2] 12. Discuss the following TTL parameters: x4] i) Propagation delay }) Worst-Case input voltages iii) Fan-out iv) Power dissipation 13. Explain clearly the operation of frequency counter with necessary block diagram and timing diagrams. [4] 21. “TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING Level : = Examination Control Division | Programme | BEL, BEX, BCT| Pais Marks | 32 2072 Kartik Year /Part | W/i_ (Time [Shirs. Subject: - Digital Logic (EX502)__ Candidates are required to give their answers in their own words as far as practicable. Attempt All questions. The figures in the margin indicate Full Marks, Assume suitable data if necessary. SAK8 What are the major difference between Binary code and BCD code? 2 Explain the operation of gated D flip-flop with timing diagram and truth table. (4) 3. What are the major differences between asynchronous and synchronous counter?. Design a Mod-6 synchronous up binary counter using S-R flip flops and draw its timing diagram. [2+6] 4, What are the applications of shift registers? Explain any one of the application with y working circuit diagram. (61 5. Construct MOD-12 asynchronous up-counter with negative edge triggering system in clock. (5] ‘6. Draw the circuit diagram for 2-input CMOS NAND gate. What is Totem pole output? Explain, [333] 7. Convert the decimal number 168 into hexadecimal and gray code by first converting it into binary and perform the following addition using 2's complement 11+15 (24243) 8. Write the minterms of ACD+AB and simplify 21,2,3,8,9,10,11,13,14+d(0,4,12) by using K-Map and write its standard product of sum (POS) expression. [4+6] 9. Differentiate between synchronous and asynchronous inputs of a flip flop with suitable diagram. Derive characteristic equation of a JK flip flop. How do you make it a toggle flip flop? Explain with diagram, +5] 10. Draw the schematic diagram of TTL NOR gate. Explain thé operation of CMOS to TTL interface, [242] 11. Explain with block diagram to build the digital watch from a power supply system. Show second, minute and hour display using decoder, 8] 12, Suppose you have given the following word specification describing the sequential operation of some machine. This machine has a control input X and the clock and two state variables A and B and one output. If the input, is high thé machine will change state otherwise this machine is supposed to hold its present state. It also gives output when the sequence is 101. Derive state table and state diagram. Use only T flip-flops and necessary logic gates. [4+8] tHe 24RE—_TRIBHUVANUNIVERSITY INSTITUTE OF ENGINEERIN = Examination Control Division | Programme | BE! 2070 Chaitra Year /Part_| 117 ‘Subject: - Digital Logic (EX502) Candidates are required to give their answers in their own words as far as practicable. Attempt All questions. The figures in the margin indicate Full Marks, Assume suitable data if necessary. Sas | . Define digital signal and explain Gray code with example. [145] 2, Prove that positive X-OR is equivalent to negative X-NOR. (5] 3. a) Convert the following term into standard min term. A+B’C. BI b) Use K-map method to implement the following function and also draw the reduced circuit using NOR gate. [3] F (A, B,C, D)= Em (0, 2, 4, 6, 8 10, 15) and = En (3, 11, 14) 4.-a) Realize the logic circuit of the following using 8:1 MUX. (41 F(W, X, Y, Z) = 3m (1,2, 5, 7, 8 10, 12, 13, 15) b) When FFy is ANDed with CO what will be the resulting number? Subtract (26) 10 from (16) 10 using 2’s complement binary method, 2] 5. a) Differentiate between level and Edge triggering? BI ) Explain the operation of two bit magnitude comparator with truth table and circuit diagram. (5) 6. a) Describe different typesof registers with diagram. [8] b) Mlustrate how 1011 ‘data can be stored and retrieve in parallel in serial out shift register with neat timing diagram and truth table. 18] 7. Differentiate synchronous and asynchronous sequential circuits, Explain the operation of mod-12 synchronous counter with timing diagram. [246] 8. a) Define state diagram and state table with example. 2) ) Design a sequential machine that has one serial input and one output z. The machine is required to give an output z = 1 when the input X contains the message 110. [3] 9, Draw the schematic diagram of TTL two input NOR Gate. (6) 10. Explain briefly the block diagram of an instrument to measure frequency. (3) 24 ‘TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING E [Fall Marks Examination Control Division BEL, BEX, BCT | Pass Marks 2071 Shawan a "| Time (3 _ Subject: - Digital Logic (£x502)____ Y Candidates are required to give their answers in their own words as far as practicable. Y Attempt All questions. Y The figures in the margin indicate Full Marks, VY Assume suitable data if necessary. 1. Define digital operations. What is Excess-3 Code explain with example, [24] 2. Define universal Gate with example. Realise Ex-OR Gate using NAND gate only. [4] 3. Simplify the following using K-map and realize the simplified result with NAND gates only. [3+3] Din(2-5.7,8:10.13) + d(0,6,14,15) 4, Implement following combinational circuit with multiplexer. [4] F(A,B,C,D) = >), (3.4.1 112,13,14,15) "'5. Using seven segment display decoder realize the logic circuit for segment *b’,‘c’ and'd’. [5] 6. With neat and clean diagram explain the operation of adder-subtractor circuit. (4] “7. Explain the operation of positive edge triggered RS flip-flop with circuit diagram, trust table-and excitation table. [+8] 8. With-clear circuit and timing diagram, explain the operation of parallel in Serial out shift register. 8] 9. Design Synchronous MOD-12 counter using T-flip-flop, [8] 10. Design a sequential machine that can go through 2-bit gray code combination of states. ‘The machine changes its state when serial input is one and remains in same state when input is zero. The machine produces output one when it passes through all states and finally goes back to initial state. (use JK flip flop) [10] 11, What are the characteristics of TTL circuit for logic high and low level? Explain the operation of TTL NAND gate. [2+6] 12. Describe the operation of Digital Clock with block diagram. (6) vee 25 ‘TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING | Lew = i Examination Control Division | Programme | Boy 2069 Chaitra \Year/Part_[U/1 1 VY Candidates are required to give their answers in their own words as far as practicable. Y Attempt AUl questions. The figures in the margin indicate Full Marks. ¥ Assume suitable data if necessary. 1. Define digital 1C signal levels. What is Gray Code? Explain with example. B43] 2. Construct the given Boolean function: F = (A+B) (C+D) E using NOR gates only. 4] Simplify F (A,B,C.D) = (0,2,5,8,10) + 4(7,15). Write its standard SOP and implement the simplified circuit using NOR gates only. [444] 4, a) Whatis priority Encoder? Design octal to binary priority encoder. (2+4] b) Design a2 bit magnitude comparator. (4) 5. Design a combinational logic that performs multiplication between two 4 bit numbers ‘using binary parallel adder and other gates. {8} 6. Draw the circuit diagram and explain the operation of positive edge triggered JK flip-flop. What are the drawbacks of JK flip-flop? (+t 7. Explain the Serial in Serial out (SISO) shift register with timing diagram. 14) 8.° Design the synchronous decade counter and also show the timing diagram. is) 9, Design a sequential machine that detects three consecutive zeros from an input data stream X by making output, Y= 1. (12) 10, Draw the schematic circuit for CMOS NAND gates. What do you mean by totem-pole output? [4+4] 11. Describe the operation of a frequency counter. 4) wee 28 ‘TRIBHTUVAN UNIVERSITY INSTITUTE OF ENGINEERING Y Candidates are required to give their answers in their own words as far as practicable. Y Attempt All questions. Y. The figures in the margin indicate Full Marks, Y Assume suitable data if necessary: 1. a) What are the different logical operations? Explain. BI b) Explain different coding system used to represent data, BI 2. Explain the operation of NAND, NOR, XOR and NOT gates with Boolean expression and truth table. 4] 3. Simplify the Boolean function in both SOP and POS and the implement using basic gates only: F(A, B, C,D) = (0, 1, 3, 4, 8, 9, 15) 18] 4, a) Design 8- to -3 line priority encoder. [4] b) Design a combinational logic that produces square of 3 bit number using ROM. (6 5. a) Implement the full adder using two half adders. GI ) Explain the working principle of binary multiplication, (3) 6. Explain the operation of RS flip flop showing it's logic diagram, characteristic table and then derive its characteristics equation and excitation table, [8] 7. With clear circuit diagram, explain the operation of parallel in-Serial out shift register. i] 8. What do you mean by Presettable Counter? Design a modulo - 12 counter using T-Flip flop. +7] 9. Design a sequential machine that takes the one bit of serial data x as input and gives the one bit of data as output z. The machine gives an output z= 1 when the input sequence of x contains the message 0100. (12) 10. What are the parameters of TTL? Explain the operation of 74C00 CMOS. [2+6) 11, Explain the operation of digital clock with neat and clean diagram. - [41 one 25 TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING Candidates are required to give their answers in their own words as far as practicable. ¥- Attempt Al questions. Y The figures in the margin indicate Full Marks, Ca Assume suitable data if necessary. List out the name of universal gates and why they are called universal ay Relise Ex- 3 [2+2} OR Gate using only NAND gates. 2) 2. Explain Excess 3 code with suitable examples. © (a . Simplify the function using K-map F= 5(0,1,4,8,10,11,12) and D = £(2,3,69,15). Also convert the result into standard minterm. © [3+5] Design a32 to 1 multiplexer using 16 to 1 and 2 fo 1 multiplexers. @ {5] . Design a 3-bit even parity generator and 4-biteven party checker ciruit.. 5) [5] Draw the block diagram of n-bit full adder and explain its operation, @ 3] Write down the drawbacks of SR flip flop. Explain the operation of data flip flop with timing diagram and truth table @ [#7] .. With clear cireuit and timing diagram, “mse the operation of Serial in - Serial out shift register. 4] 9. Define tipple counter. Explain the operation of mode10 ripple counter with timing diagram. u+7 0. Design « sequential machine tht has one serial imput and one output 2, The machine is required to give an output z= 1 when the input x contains the message 1010. (12) H. Describe the voltage profile of TTL. Explain the operation of TTL to CMOS interface. [2+6] 712. What is frequency counter? Explain with block diagram. [4 oo 28 TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERIN' Examination Control Divi: 2069 Ashad [Wear/Part_ [1/1 Subject: - Digital Logic (EX 502) ¥ Candidates are required to give their answers in their own words as far as practicable. ¥. Attempt All questions. Y. The figures in the margin indicate Full Marks. Y Assume suitable data if necessary. 4. Describe in your own words the characteristics of an analog signal and a digital signal. (3) Z. Define positive and negative logic with examples (3) 3. Construct the basic gates using only universal gates. (4) 4,- Simplify the following using K-map. ¥n(3,4,6,8,10,15) + 4(0,2,7,14). GI 5. What are the static hazards in combinational circuit? Also explain how these hazards can * be covered. 5) 6. Explain the operation of BCD to decimal decode? with truth table anll circuit diagram, t Impleinent 1:4 demux using VHDL. (6+4) 7. Design a full adder circuit using HDL. i] 8, Whatis a Fast Adder? Explain with examples. (4 9. Draw the circuit diagram and explain the operation of edge triggered RS flip-flop. Convert RS flip-flop to IK flip-flop. [543] ; 19. Explain the working of serial in -serial out register clearly. ic 11. Differentiate between the synchonous and Asynchronous counter, Draw end explain the * operation of Asynchronous Decade counter with clear timing diagram. i2+6) 12, Design Synchronous sequential circuit for the given state diagram using JK flip flop. uy 13. Draw the schematic diagram of TTL NAND gate and explain about the CMOS characteristics. [2+6] 14, With the help of block diagram explain the operation of frequency counter. [4] see ‘Exam. ‘Reguiar/ Back. ‘INSTITUTE OF ENGINEERING [Tevet BE Full Marks [80 "“Exatnination Control Division, | programme | BEL B©> | ase naurus [32 BCT : 2068 Baishakh ar Part {1/1 Tine Sh. Subject: -Digitél Logie = Candidates are requived to give their answers in ther own words as far as practicable, et Y Attempl AU! questions. % The figueés in the margin indicate Full Marks © Assume suitable dts Pnécessary : aos Draw tte genefal input output voitege profile for TTL gates end lso-menifon the noise Soin margin, What do you mean by Gray code? (ee) oF 2. Why NAND and NOR gaites'tife culled Universal gates? illustrate with examplés” 1+" [4] 8) 2 Whit do you mean by HDL? Desig a2 to 4 line decoder civeull ising HDL. (243) sae Simplify 16,'4,5,8, 9, 11,15) using KeMtap and wie is standard SOP expitsion, [442] [8] j 5:/- Draw the cinguit 04 bit RCA. (Ripple Cary Added), using only Block diagrams, What are - 22 the problems associated withRCA. Explain how these problems tan’be eliminated." [442+2] . = 6. *Drivi the echemaiie diagram OFTTENOR, ‘Bate. Discuss the characteristics of TTL, 00 6] teries gates, : (6) [4] 7. Draw the cieuitdiggram of edge lrigated JK Hip Nop ‘and explain {5} Wiat‘ie e ehift fopister? With clear timing dian’ Aeshibe the operation of @4-bit = 7 if pull in sera - out (P1$0) ein eae, . 2 BHD py sigh a synchrorious state niachine-Wwith the following speci ication: [12] jo. oF input: ne : bVENo. ofoutputl “ utput ofthe siachine’ is to’te'set high When the.data in the input is. {10 in ee ivting from the MSB (Use SR fip= flop). < snple, sate and srolin the probléms assobiatel inthe desigit . ' ircuit, ie a . (6) RSS i ‘yc amewavomvensre ian Faas] INSTITUTE OF ENGINEERING ‘Level ‘BE [Full Marks | 80 i Examination Control Division. [Programme [BEY P* | pass Maris | $2 ; = © 2067-Ashadh erates Sime. SB, — 3 fe Ss Subject: “Digital Lo i r ¥. Candidzies ere required to give their answers in their own words as far as practicable. | ¥, sttenp? all questions, : : j The figeras inthe margin tndtecte Full Marks, ‘ i ¥ ssume suitable data if necessary, . [oy gaeeb BeRs EEC pS SRA: a : i 2) Octal 623.77 10 decimal, binary and hexadecimal b) ‘Hexadecimal 2AC5.D to. socal ‘octal and binary, ! | . (U20 Perform the subtrection with the following’ decimal. and binary. umbers using 9°5 and I's . | complezaeat respectively, ee 4 '2) 3370-2100 (Using’9"s Complément) 28°" os v | 2) 10010-10011 (Using 1's complement) S } “cg Prove the following Boolean expression: |). [4443] i eal = 1 B+ 5C¥ABCSAB+AC+BC “And siapliy 21,2,3,8,,20,11,14) and 004,12) by wing -mmap and waite its standard product of Sim (POS) expresion. : e scl hl’ it ‘input aba onb output, Ths state diag ‘ethos in figure, Designee seposil chl Wih Seopa rT) b) Gray code &) Pasty generator

You might also like