Chapter 7: Sequential Logic

Part 1: Latches

MS. ABEER ALGHAMDI

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Lecture Outline

 Introduction to Sequential logic.

 Define Latches.
 Explain the operation of a basic S-R latch.
 Explain the operation of a gated S-R latch.
 Explain the operation of a gated D latch.

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Introduction to Sequential Logic - Memory

 Memories are used to store information.

a) Long-term storage, e.g., hard disk, flash memories, CDs, magnetic tape, etc.
b) Short-term storage, e.g., RAM, registers, etc.
 Some operations, need to account for the previous outputs to produce current
output (feedback circuits).

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Sequential Logic

➢ Sequential Logic circuit is a family of digital

circuits with the following features:
a) Has a combinational part to compute the
output.
b) Contains memory circuits to store the previous
output/ state.
➢ Usually referred to as sequential machines,
sequential circuits have some form of inherent
memory built-in, shaped by feedback.

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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Sequential Logic

 Sequential Logic circuit considers the present

input, past input, and past output.
 Things happen in a sequence, and the clock
determines when things will happen next.
 In other words, sequential circuits are basically
combinational circuits with the additional
properties of storage, to remember past inputs
and feedback.
 Therefore, they are mainly used to store data.

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Latches

 The latch is a type of temporary storage device that has two stable
states (bistable).
 Latches are level sensitive device.
 Special latches are:
a) S-R (Set-Reset) latch
b) Gated S-R latch
c) Gated D latch

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The S-R (SET-RESET) Latch

 A latch is a type of bistable logic device or

multivibrator.
 Notice that the output of each gate is
connected to an input of the opposite gate
 This produces the regenerative feedback that is
characteristic of all latches.

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The S-R (SET-RESET) Latch

 The latch in Figure has two inputs, and , and two

outputs, Q and .
 Assume that both inputs and the Q output are HIGH,
which is the normal latched state. Since the Q
output is connected back to an input of gate G2 ,
and the input is HIGH, the output of G2 must be
LOW.
 This LOW output is coupled back to an input of gate
G1, ensuring that its output is HIGH

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The S-R (SET-RESET) Latch

 When the Q output is HIGH, the latch is in the SET state.

 It will remain in this state indefinitely until a LOW is
temporarily applied to the input.
 When the Q output is LOW, the latch is in the RESET state.
 The latch remains indefinitely in the RESET state until a
momentary LOW is applied to the input.

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The S-R (SET-RESET) Latch

 In normal operation, the outputs of a latch are always

complemented of each other.
 When Q is HIGH, is LOW, and when Q is LOW, is
HIGH.
 An invalid condition occurs when LOWs are applied to
both and at the same time. then both the Q and
outputs are forced HIGH, thus violating the basic
complementary operation of the outputs.
 Also, if the LOWs are released simultaneously, both
outputs will attempt to go LOW.

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DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The S-R (SET-RESET) Latch - Example

Q1: Find the output Q, given the inputs and assume Q is initially LOW.

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The S-R (SET-RESET) Latch - Example

Solution:
➢ Q goes high when goes low and is high.
➢ Q goes low when goes high and is low.
➢ No change if both are high.
➢ Q is high if both inputs are low.

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The Gated S-R Latch

 A gated latch requires an enable input, EN.

 The S and R inputs control the state to which the latch will
go when a HIGH level is applied to the EN input.
 The latch will not change until EN is HIGH; but as long as it
remains HIGH, the output is controlled by the state of the S
and R inputs.
 The gated latch is a level-sensitive device.
 In this circuit, the invalid state occurs when both S and R
are simultaneously HIGH and EN is also HIGH.

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The Gated S-R Latch

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The Gated S-R Latch - Example

 Q1: Determine the Q output waveform if the inputs shown in Figure 7–9(a)
are applied to a gated S-R latch that is initially RESET.

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The Gated S-R Latch - Example
 Solution:
 The Q waveform is shown in Figure. When S is HIGH and R is LOW, a HIGH on the EN input
sets the latch.
 When S is LOW and R is HIGH, a HIGH on the EN input resets the latch.
 When both S and R are LOW, the Q output does not change from its present state.

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The Gated D Latch

 Another type of gated latch is called the D latch. It differs

from the S-R latch because it has only one input in addition to
EN. This input is called the D (data) input.
 When the D input is HIGH and the EN input is HIGH, the latch
will set.
 When the D input is LOW and EN is HIGH, the latch will reset.
 Stated another way, the output Q follows the input D when EN
is HIGH.

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The Gated D Latch

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The Gated D Latch - Example

 Q1: Determine the Q output waveform if the inputs shown in Figure 7–11(a)
are applied to a gated D latch, which is initially RESET.

DAH I HECI I LOGC1201 I Fall 22-23 I Ms. Abeer Alghamdi

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The Gated D Latch - Example

 Solution:
 The Q waveform is shown in Figure. When D is HIGH and EN is HIGH, Q goes
HIGH.
 When D is LOW and EN is HIGH, Q goes LOW.
 When EN is LOW, the state of the latch is not affected by the D input.

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“
Thank you for listening ☺

”
Next topic chapter_7_part_2: Flip Flop

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