Silicon Processing Technology for Microelectronics

Fundamentals, Practice and Modeling

CHAPTER 2
Modern CMOS/Device Technology
ENE531000
Fall Semester

Instructor: Dr. Chao-Hui Yeh

(EE/NTHU)
 MOSFET Architecture
Spacer

LG

LDD

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Terms Tech. NMOS PMOS
P well (Ion implant doping) N well (Ion implant doping)
Body
“Boron” “Phosphorus”
N+ doping (Arsenic) P+ doping (Boron)
Source/
NMOS: implant with higher dose PMOS: implant with higher
Drain
of 2 – 4x1015 cm-2 dose of 1 – 3x1015 cm-2
Dielectric SiO2 SiO2
Gate Polysilicon (N-type) Polysilicon (N-type)

Terms Terms Terms

Ion Buried Accumulation
離子佈植 深埋層 累積層
implantation layer layer
Depletion
LOCOS ‐‐Local 空乏區
Epitaxial region
Oxide of 矽局部氧化 磊晶層 (空間電
layer (Space charge
Silicon 荷區)
region)
LDD ‐‐
STI ‐‐ Shallow 淺溝槽隔絕
Lightly 輕參雜汲極
Trench 技術 Inversion layer 反轉層
Doped (淺輕摻雜)
Isolation
Drain
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 2-2 CMOS process flow

In the simplest modern CMOS

technology, we need to realize simply
NMOS and PMOS transistors which
meet the demands for circuits
applications like those illustrated below.

IN1 IN2 Out

put
0 0 1
0 1 0
1 0 0
1 1 0

…………….
CMOS NOR Figure 2-1 Cross section of the final CMOS integrated
circuit. A PMOS transistor is shown on the left, an NMOS
device on the right.
OUTPUT= 𝐈𝐍𝟏 𝐈𝐍𝟐
Flip‐flop (at least 20 transistors)/Single Bit Full Adder ( > 8 transistors)
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 Well/Active channel formation
Standard Process Flow Charts (without option process)
*Define PMOS & NMOS regions Ion implantation
Field oxide Bird’s beak
(a) (b) (c) (d)

Si (100) Oxide diffusion

Crystal orientation
Mask 1 Mask 2
(option: STI)

(e) (f) Well-defined N/P well (g) (h)

Mask 3 Caution: Latch-up Mask 4 Mask 5

(option: Buried layer)

(i) (j) (k) (l)

Mask 6 Mask 7

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 Ion implant Anisotropic etching
(Spacer formation)
(m) (n) (o) (p)

Mask 8 Mask 9

10 nm amorphous oxide
=> To prevent from Channeling

(q) (r) (s) (t)

Mask 10

(u) (v) (w) (x)

Mask 11

TiSi2 TiN
ohmic contact (10 Ω/sq)
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(y) (z) (aa)

Mask 12

(cc)
(bb)

Mask 13

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2.2.1 Choosing a substrate
(a) Wafer size and type (N or P)
(b) Resistivity (doping level): moderate resistivity
(25-50 Ωꞏcm) with doping level of ~1015 cm-3 <
Well doping level of 1016-1017 cm-3
(c) Crystal orientation: mainly (100) due to less
defects and higher quality of Si/SiO2 interface

…………….
Figure 2-2 Following initial cleaning, an SiO2 layer is
Compressive Tensile thermally grown on the silicon substrate. A Si3N4 layer is
then deposited by LPCVD. Photoresist is spun on the
2.2.2 Active region formation wafer to prepare for the first masking operation.

Local oxidation of Si (LOCOS) for electrical

isolation from each devices :

(a) Thermal growth of thin SiO2 layer (~40 nm): 15 min at 900 ℃ in an H2O atmosphere or 45
min at 1000 ℃ in pure O2 atmosphere SiO2 is under compressive stress.
(b) Growth of thin nitride layer (~80 nm) by LPCVD: 3SiH4 + 4NH3 → Si3N4 + 12H2 The Si3N4 is
under tensile stress, and can be partially compensated by the underlying SiO2, reducing the
stress in Si.
(c) Spinning and patterning of photoresist
(d) Dry etching of Si3N4 (using CF4 or NF3 gas): Si3N4 + 12F → 3SiF4 + 2N2
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(e) Remove the resist by using O2 plasma or sulfuric acid:
both of them do not attack Si3N4 and SiO2.
(f) LOCOS at 1000 ℃ for 90 min in H2O to grow ~500 nm
of SiO2 on the exposed region Si3N4 is a very dense
material and prevents H2O and O2 from diffusing to the
underlying Si.
The lateral diffusion of oxidant (H2O) from SiO2 cause
bird’s beak and reduce the active region (decrease
…………….
device density). Figure 2-3 Mask 1 patterns the photoresist. The Si3N4
( g ) Stripping Si3N4 in hot phosphoric acid. layer is removed where it is not protected by photoresist
The acid is highly selective between Si3N4 and SiO2. by dry etching.
Active region shrinking
(Bird’s beak)
(h) Alternative to SiO2/Si3N4 stack:
Poly SiO2/Si3N4/SiO2 (Poly-buffered LOCOS)
Poly SiO2 (~100 nm) is formed by LPCVD. Expansion of field oxide
Poly SiO2 helps release large stresses which
would cause defects in Si during the LOCOS.

This stack allows us to use a thicker Si3N4 and

…………….
thinner SiO2, both of which reduce the lateral Figure 2-4 After photoresist stripping, the field oxide is
diffusion of oxidant and bird’s beak accordingly. grown in an oxidizing ambient.

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2.2.3 Process option for device isolation – shallow
trench isolation (STI) Si3N4 Resist
SiO2
In this section we will see a process option which can
eliminate bird’s beak.

(a) We start with the same process as LOCOS does:

First grow SiO2 and then Si3N4 layer with similar …………….
Figure 2-5 After mask 1 defines the photoresist,
thickness. the Si3N4, SiO2 and Si trenches are successively
plasma etched to create the shallow trenches for
(b) Photoresist is then applied, exposed, and developed. isolation.
(c) Si3N4 and SiO2 are etched using resist as a mask.
(d) A Si trench is created by bromine-based plasma
etching.
The trench needs to be vertical with a little undercut.
The trench will be filled by depositing SiO2. A sharp
trench is important for avoiding voids in filling with Liner oxide (SiO2)
SiO2. A little undercut rounds the corners and avoid
electrical effects associated with sharp corners. …………….
Figure 2-6 A thin “liner” oxide is thermally grown
(e) Next step is to thermally grow a thin (10-20 nm) “liner” in the trenches. The nitride prevents any
additional oxidation on the top surface of the
oxide which enhance the Si/SiO2 interface. wafer.
(f) Then fill the trench with SiO2 by CVD.
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(g) Polishing the excess surface SiO2 by
chemical mechanical polishing (CMP). In this
process, a high-pH (base) silica slurry is used
for polishing and the nitride layer serves as a
polishing stop.
…………….
Figure 2-7 SiO2 is deposited to completely fill
the trenches. This would typically require 0.5 – 1
µm of SiO2 to be deposited, depending on the
trench depth and geometry.

(h) There are three advantages in STI compared

with LOCOS:
There is no long high-temperature oxidation, so
less defects are generated.

The bird’s beak can be eliminated.

Produce a more compact isolation. …………….
Figure 2-8 The deposited SiO2 layer is
polished back using CMP to produce a planar
structure.

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2.2.4 N and P well formation
The well properties such as doping level are important in terms of MOS transistor threshold
voltage, I-V characteristics, and PN junction capacitance.

(a) Using optical lithography to define the region where P well is to be formed.
(b) Implantation of boron ions for P well.
(c) Strip resist chemically or in O2 plasma.
The energy of the boron ions must be large enough to (d) Thermal annealing for repairing the damaged
go through “thin” and “thick” oxide regions, but small lattice: Ex.10 sec. at 1000 ℃ or 30 min at 800 ℃
enough not to go through the resist layer. (e) Follow similar procedure of optical lithography
for the N well formation.
The energy is in the range of 150 – 200 keV. (Boron)
Thick oxide ~ 0.5 μm. Thin oxide
The dose depends on the desired doping level in the ~ < 0.1 μm. Photoresist ~ 1 μm.
well. For doping level 1017cm-3, we need dose on the (f) Implantation of phosphorus ions for N well.
13
order of 10 cm . -2
The energy of the phosphorus ions
must be large enough to go through
“thin” and “thick” oxide regions, but
small enough not to go through the
resist layer.
The energy is in the range of 300 – 400
keV to reach the same depth in Si
Thick oxide ~ 0.5 μm Thin oxide
because phosphorus is a heavier atom.
(Phosphorus)
(field oxide) < 0.1 μm
…………….
To avoid parasitic Figure 2-9 Photoresist is used to mask the regions where PMOS devices
inversion problem will be built using mask 2. A boron implant provides the doping for the P
wells for NMOS devices.
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(g) Removing the resist and anneal at 1000-1100 ℃
for 4-6 hrs to reach a junction depth of 2-3
µm (drive-in process).

(h) Phosphorus has a bit smaller diffusion

coefficient compared with boron, so the P and
N well are capable of having similar junction …………….
Figure 2-10 Photoresist is used to mask the regions
depth after the drive-in annealing. where NMOS devices will be built using mask 3. A
phosphorus implant provides the doping for the N wells for
the PMOS devices.
(i) Other dopants for N well are As and Sb.

They are heavier (higher implantation

energy) and have smaller diffusion
coefficients.
Drive‐in annealing
Areal Does: Total amount in normalized area
Concentration: …………….
Figure 2-11 A high temperature drive-in completes
the formation of the N and P wells.

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2.2.5 Process option
(i) Field implants under LOCOS regions

This option ensures that the dopants go through the field

oxide. The deepest ions often penetrate through the resist
when the shallowest ions go far enough to get through the
field oxide, e.g., the processes, as illustrated in Figs. 2.9
and 2.10 (as shown in Slide 12 & Slide 13), which are kind
of sensitive to layer thicknesses and implant energy.

(a) Do the ion implantation prior to the LOCOS. In this way, a

low-energy (~50 keV) boron can be used which is easily ……………
masked by the resist/Si3N4/SiO2 stack. Figure 2-12 Process option for active region formation.
A boron implant prior to LOCOS oxidation increases the
substrate doping locally under the field oxide to
(b) Do the LOCOS for field oxide. Some of the boron diffuse minimize field inversion problems.
ahead and some are incorporated in the field oxide.

Field implant
Drive‐in process
………………… …………………
Figure 2-13 Process option for active region formation after Figure 2-14 Process option for active region formation after the
LCCOS. The boron implanted regions diffuse ahead of growing P and N wells are formed.
oxide producing the P-doped regions under the field oxide.
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 (ii) Buried and epitaxial layer
This option is to shunt the parasitic PNPN structures with low
resistance, preventing the PNPN devices (letch up) from
turning on.
(a) High-dose (1015 cm-2) is used to implant N+
buried layer.
Due to the thin oxide layer, a low-energy (~50 keV) N+ for low-resistance shunt
is sufficient. We do not want the implanted atoms
diffuse too far away in subsequent high temperature
process, so we use low diffusion-coefficient As or Sb.
…………….
(b) Remove the resist and do the LOCOS at Figure 2-15 Process option incorporating buried and
1000 ℃ for 2 hrs. epitaxial layers. Mask 1 defines the regions for N+
buried layers. An AS+ implant dopes the silicon locally.
It drives in the N+ layer to a depth of 1~2 μm.
It grows a thick oxide layer on top of N+ buried layer.
The thick oxide form a mesa which indicates the
location of buried layer and hence acts as an
alignment marker for later process.

(c) Strip the Si3N4 and then implant P+ buried layer.

Boron is used for the P+ buried layer.
Boron must go through the thin oxide but be …………….
stopped by the thick oxide, so the energy is ~50 keV. Figure 2-16 Process option incorporating buried and
Lower dose ~1014 cm-2 is used to keep it from diffusing epitaxial layers. The N+ buried layers is driven in an
too far at high temperature process. oxidizing after the photoresist is stripping. The LOCOS
oxide forms only above the N+ regions.
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(d) High temperature drive-in process:

Diffuse both boron and arsenic deeper into the

substrate.
No additional oxidation is needed (in N2 or Ar
atmosphere).
Few hours at 1000 ℃ for having similar depth.
…………….
Figure 2-17 Process option incorporating buried and
epitaxial layers. The P+ regions buried layer is
implanted using thick SiO2 layer as a mask.

…………….
Figure 2-18 Process option incorporating buried and
epitaxial layers. The P+ and N+ buried layer are driven
together.

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(e) Form a lightly doped (1016 – 1017 cm-3) P and
N well above each buried layer :
No precise counterdoping available.

(f) Remove the SiO2 by HF solution.

The step is inherent from the oxide and can be
(g) Epitaxy by CVD: used for alignment.
SiH4 or SiH2Cl2 as Si source and B2H6 or AsH3
…………………
for the P- and N-type doping.
Figure 2-19 Process option incorporating buried and
Epi at 800 – 1000 ℃. epitaxial layers. The surface SiO2 layer is stripped off
The step is inherent from the oxide and can be the wafer and an epitaxial layer is then grown.
used for alignment.
(h) Then follow the LOCOS steps.
(i) Form the P and N wells.
In this step, the temperature treatment must account
for the upward diffusion from the buried layer, which
determines the temperature and time.

Now we are ready for the fabrication of active device. …………………

Figure 2-20 Process option incorporating buried and
epitaxial layers.

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 Latch‐up effect

Figure S5 CMOS structure with latch‐up parasitics in cross section view & equivalent
circuit for latch‐up parasitics.

1. Noise at the output terminal

2. ESD (Electrostatic discharge)
3. Ionizing radiation

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2.2.6 Gate formation
In this section we would like to adjust the most important
MOS parameter – threshold voltage, which is about 0.5 – 0.8V
for both the NMOS and PMOS.
(a) The threshold voltage is given by

2ε 𝑞𝑁 2ф
𝑽𝑻𝑯 𝑉 2ф
𝐶
𝑉 Gate voltage required to compensate for work
function difference between the gate and substrate

𝜙 Fermi level with respect to the intrinsic level

…………………
𝜀 Permittivity of Si Figure 2-21 Process option for active region formation.
A boron implant prior to LOCOS oxidation increases the
substrate doping locally under the field oxide to
𝑁 Doping concentration The only two parameters minimize field inversion problems.
you can play around for VTH !
𝐶 Oxide capacitance

Because NA achieved by ion implantation is not constant (nonuniform profile), we modify the above
equation with the first order approximation of the implant dose QI.
ф 𝒒𝑸𝑰
𝑽𝑻𝑯 𝑉 2ф
𝑪𝒐𝒙
Therefore, the VTH can be obtained by adjusting QI through (b) to (d), and COX through (e) to (f).

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(b) Optical lithography is applied to define the areas
where NMOS devices are located.
(c) A boron implant is used to adjust VTH of NMOS,
with dose of 1012 cm-2 at an energy of 50 keV.
The dose QI is calculated based on the above
equation to achieve a given VTH.
The energy is chosen to be high enough to go
through the thin oxide, but low enough to keep
the boron near the surface.
(d) The same process and conditions for arsenic …………………
implant to PMOS. Figure 2-22 After spinning photoresist on the wafer,
(e) Strip the original thin oxide (10-20 nm) by mask 5 is used to define the PMOS transistors. An
arsenic implant adjusts the P-channel VTH.
using HF etching.
This is because the original oxide is too thick to
serve as gate oxide.
This is also because the original oxide is
damaged by several implants.
The etching should be timed, not to etch field
oxide too much.
…………………
(f) A gate oxide (< 10 nm) is grown in O2 at Figure 2-23 After etching back the thin oxide to bare
800℃ for 2 hrs or in H2O at 800 ℃ for 25 min. silicon, the gate oxide is grown for the MOS transistors.

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Deposit the polysilicon gate electrode by LPCVD at 600 ℃
for 0.3-0.5 μm: SiH4 → Si + 2H2

(h) Obtain a low-resistance polysilicon gate electrode:

“in situ” dope the polysilicon as it is formed in LPCVD.
Or use high dose (1015 cm-2) to implant poly after the …………………
LPCVD. The energy must be low enough not to Figure 2-24 A layer of polysilicon is deposited.
Ion implantation of phosphorus follows the
penetrate through the poly. A post annealing can deposition to heavily dope the poly.
enhance the doping uniformity because dopants
rapidly redistribute along the grain boundary at
elevated temperature.

(i) Chlorine- or bromine-based plasma etching of patterned

poly. The plasma has good selectivity to SiO2. The poly
lines can be used as “local interconnects”. For long
interconnect, the RC delays associated with long poly is …………………
significant. Figure 2-25 Photoresist is applied and mask 6 is
used to define the regions where MOS gates are
located. The polysilicon layer is then etched using
plasma etching.

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2.2.7 Tip or extension (LDD) formation
The conventional MOS devices are operated at 5 V. Scaling N-channel
down the device dimension causes increased electric field in Curve B:
Curve A:
L=6.25 µm
VDS = 0.5 V

the channel. However, the supply voltage cannot be simply Curve C:

L=1.25 µm
L=1.25 µm
VDS = 0.5 V

scaled down as the dimension does because then new ICs VDS = 5 V

are not compatible with older parts, system power has to be

redesigned and circuit noise margins becomes inadequate. 5 kT/q

Ex. For 5 V applied across 2-μm channel MOS device, …………………

the electric field is 2.5x104 V/cm. Decreasing the Figure 2-26 Surface potential energy profile
of N-MOSFET with various channel lengths.
channel length to 0.2 μm without reducing the supply
voltage increases the field to 2.5x105 V/cm. This field
gives rise to “impact ionization”. (Later electric field)

When the channel length is short and the field is high,

“short channel effect” shows up. This effect happens
when the drain electric field penetrates through the
channel region and begins to affect the potential barrier
between the source and channel regions. The result is …………………
that the gate cannot effectively control the drain current. Figure 2-27 Mask 7 is used to cover the
PMOS devices. A phosphorus implant is used
to form the tip or extension (LDD) regions in
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To reduce this problem, the technique of “Lightly Doped
Drain (LDD)” is used.

N+N–P profile between the drain and channel in NMOS

P+P–N profile between the drain and channel in PMOS
LDD structure are often called “tip” or “extension” region.
This allows the drain voltage to be dropped over a
larger distance than would be the case if an abrupt N+P
junction were formed. This reduces the peak value of …………………
the electric field in the near drain region. Figure 2-28 Mask 8 is used to cover the
NMOS devices. A boron implant is used to
(a) For NMOS: phosphorus implant with dose of form the tip or extension (LDD) regions in the
PMOS devices.
5x1013 – 5x1014 cm-2 at low energy is used.
(b) For PMOS: boron implant with similar conditions is
used.
(c) Next step is to form a conformal spacer dielectric
layer (SiO2 or Si3N4) by LPCVD.
SiH4+ O2 → SiO2 + 2H2 at 400 ℃ or
SiH2Cl2 + N2O → SiO2 + 2N2 + 2HCl at 900 ℃
…………………
(d) Anisotropic etching (only vertically but not horizontally) Figure 2-29 A conformal layer of SiO2 is
deposited on the wafer in preparation for side-
leaves sidewall spacers along the edges of the polysilicon. wall spacer formation.
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 2.2.8 Source/Drain formation

(a) Formation of screen oxide (~10 nm)

In previous step we have stripped the oxide layers which
If we use anisotropic etching and etch only
are above the drain and source region. We need this
a fixed depth, the thicker spacer oxide will
oxide layer to prevent from “impurity” and “channeling”. have a part left. (no mask is required in this step)
The thin amorphous oxide can randomize the direction of
implanted ions and hence minimize channeling. …………………
Figure 2-30 The deposited SiO2 layer is etched back
(b) For NMOS: Arsenic implant with higher dose of anisotropically, leaving sidewall spacers along the
edges of the polysilicon.
2 – 4x1015 cm-2 at an energy of 75 keV
(c) For PMOS: Boron implant with higher dose of
1 – 3x1015 cm-2 at an energy of 5 – 10 keV

It should be noted that the polysilicon gate regions which is

initially N-doped receive several high-dose implants,
including N+ and P+. We normally use N-type gate in both
the PMOS and NMOS. In this case, we must keep the P+
dose in the current step smaller than that of N+. “tip” or “extension”

(d) Annealing to repair the implant damage and drive

the junctions to their final depth: …………………
900 for 30 min or 1000 ℃ for 1 min. Figure 2-31 After growing a thin “screen” oxide,
photoresist is applied and mask 9 is used to protect
the PMOS transistors, An arsenic implant the forms
the NMOS source and drain regions.
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2.2.9 Contact and local interconnect formation
The first level interconnect is often called
“local interconnect”
(a) First remove the oxide on top of the drain, source,
and gate region by short dip in a buffered HF.
Because the oxide is thin, the etching will not
much reduce the thickness of oxide elsewhere.
The spacer is important for providing graded
(b) Sputter a thin layer of Ti, with thickness of N+N- or P+P- drain junctions.
50 – 100 nm.
(c) Annealing in an N2 ambient at 600 – 700 ℃: …………………
Figure 2-32 After applying photoresist, mask 10 is
On the side where Ti contacts with Si a layer used to protect the NMOS transistors. A boron
of TiSi2 is formed. It gives low-resistance implant then forms the PMOS source and drain
regions.
contacts to N+ and P+ silicon or polysilicon.

Annealing drives in the P+ or N+ to the desired depth.

………………… …………………
Figure 2-34 An unmasked oxide etch removes the SiO2 from Figure 2-33 A final high-temperature drive-in
the devices source drain regions and from the top surface of activates all the implanted dopants and diffuses
the polysilicon. junctions to their final depth.
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On the side where Ti exposes to N2 a layer of TiN
is formed. It is also conductive, but not as high as normal Ti film
metals. It can be used for local interconnect, but not for
long-distant interconnect in which significant RC delays
occur.
(d) Optical lithography to define the pattern where we want
to remain TiN on the wafer.
(e) The remaining TiN is etched in NH4OH:H2O2:H2O
(1:1:5). …………………
(f) Annealing in an Ar ambient at ~800 ℃ for 1 min to Figure 2-35 Titanium is deposited on the wafer
reduce the resistivity of the TiN and TiSi2 to the final surface by sputtering.

value.
TiN forms a continuous film on top

The spacer also serves the function of separating TiSi2 is only formed in the area contacted
the TiSi2 on the poly gates from contacting the Si
doped regions.
…………………
………………… Figure 2-36 Titanium is reacted in an N2
Figure 2-37 Photoresist is applied and mask 11 is used to define the ambient, forming TiSi2 where it contacts silicon
regions where TiN local interconnects will be used. The TiN is then or polysilicon (black regions in the figure) and
2024/Fall NTHU‐ENE53100 TiN elsewhere. 2‐26
2.2.10 Multilevel metal formation
Till now, the surface is full of hills and valleys which make
the subsequent metal interconnects discontinuous. We
need to flatten the surface topography.
(a) The first method is to grow a fairly thick
SiO2 layer by CVD.
The SiO2 layer (~1 μm) is thicker than the largest steps.
This SiO2 layer is often doped with phosphorus and
sometimes with boron as well, known as PSG
(phosphosilicate glass) and BPSG (borophosphosilicate …………………
Figure 2-38 After stripping the photoresist, a
glass), respectively. conformal SiO2 layer is deposited by LPCVD.
Phosphorus provides some protection against mobile
ions like Na+ which causes instabilities in MOS
devices. (Chap. 4)
Boron reduces the temperature at which the glass “flows”.
Spinning a layer of photoresist to make the whole wafer
flat because resist is a liquid and can fill up the valleys
well.
Plasma etching with a recipe which has 1:1 etching rate
for the resist and SiO2 until the underlying SiO2 is etched …………………
everywhere. Figure 2-39 Chemical-Mechanical Polishing
(CMP) or resist etchback is used to polish or
(b) The second method which is widely used etchback the deposited SiO2 layer. This
today is chemical mechanical polishing (CMP). planarizes the wafer surface.

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(d) Optical lithography to define the pattern where we
want to make contacts.
(e) SiO2 is then etched by plasma.
(f) Strip the resist.
(g) Blanket deposition of a thin TiN or Ti/TiN layer (tens
of nm) by CVD. It provides good adhesion to the SiO2
and also acts as an effective diffusion barrier.
(h) Blanket deposition of W layer by CVD: …………………
WF6 + 3H2 → W + 6HF Figure 2-40 Photoresist is spun onto the wafer. Mask
12 is used to define the contact holes. The deposited
(i) Use CMP to planarize the wafer. It removes the W SiO2 layer is then etched to allow connections to the
and TiN everywhere except in the contact holes. silicon, polysilicon and local interconnect regions.

………………… …………………
Figure 2-42 CMP is used to polish back the W and TiN Figure 2-41 A thin TiN barrier/adhesion layer is
layers, leaving a planar surface on which the first level deposited on the wafer by sputtering, followed by
of metal can be deposited. deposition of a W layer by CVD.
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(j) Al with a small percentage of Si and Cu is
deposited and then etched, as shown in Fig. 2-43.
The containing Si is to
prevent the absorption of Si from underlying Si-rich
layers. The Cu is added to prevent from
electromigration in Al.

(k) Repeating the same procedures multilevel of

interconnects can be built. …………………
Figure 2-43 Aluminum is deposited on the wafer by
sputtering. Photoresist is spun on the wafer and
(l) At the end, the top layer is covered with SiO2 or mask 13 is used to define the first level of metal. The
Si3N4 for protection. Al is then plasma etched.

…………………
Figure 2-44 The steps to form the second level of Al
interconnect follow those in Figures 2-38 to 2-43.
Mask 14 is used to define via holes between metal 2
and metal 1. Mask 15 is used to define metal 2. The
last step in the process is deposition of a final
passivation layer, usually Si3N4 deposited by PECVD.
The last mask “16” is used to open holes in this mask
over the bonding pads.

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 Appendix-- FinFET

Figure S1 3-D FinFET structure & FinFET-based CMOS architecture

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 Appendix -- FinFET fabrication procecess

Figure S2 FinFET fabrication process

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 Moving to GAA FETs

Figure S3 Approach to fabricate 3-D stacked-Si nanosheet for GAA (GAA = gate-all-around)
devices. (a) Stack of Si/SiGe superlattice grown on SOI substrate. (b) Anisotropic plasma
etching achieved in an inductively coupled plasma (ICP) reactor. (c) Innovative process
proposed to achieve the isotropic and selective etching of SiGe layers in an Reactor
protection system (RPS) reactor: cycle of a two-step process alternating oxidation and etch.
(d) Release of horizontal Si nanowires.

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Figure S4 Process flow of vertically stacked Si-nanosheet FET . a) A photoresist line is defined on t he Si
wafer. b) A specified process is performed to produce a scalloped trench. c) Wet oxidation . d) A thick
photoresist is spin-coated in order to fill the cavities formed around the trench. e) The oxide removal step free
the Si-nanosheets withouth removing the oxide at the bottom of the cave. f) Si-nanosheets are vertically
stacked and electrically isolated from the substrate. g) A high quality dry oxide is formed. h) LPCVD
polysilicon deposit ion. i) Gate patterning
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 Interconnect – Via & TSV (Through Silicon Via)

3D view of via & TSV architecture

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 Appendix -- Via/TSV Technology

(Double
side
polished)
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 Latch‐up effect

Figure S5 CMOS structure with latch‐up parasitics in cross section view & equivalent
circuit for latch‐up parasitics.

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Figure S6 Cross section of a long n‐channel MOSFET (a) at flat band and (b)at inversion.

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Figure S7 (a) Equipotential plot along the surface of a long-channel MOSFET. (b)
Equipotential plot along the surface of a short-channel MOSFET before and after
punch-through.

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Figure S8 The energy-band diagram
of a MOS capacitor with a p-type
substrate for (a) Flat band – a zero
applied gate bias showing the ideal
case (b) Accumulation layer of holes
(c) induced space charge region (d)
Inversion layer of electrons.

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•The layout implementation of an Inverter
VDD
VDD

Input Outpu
t Input Output

GND
GND
Diffusion layer drawing Well layer drawing Metal layer drawing

Poly layer drawing Contact layer drawing Labeling, DRC LVS

VDD

Input Output

GND
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