Field Effect Transistors 515 516 Principles of Electronics

Example 19.1. Fig. 19.14 shows the transfer charac-

teristic curve of a JFET. Write the equation for drain
current.
Solution. Referring to the transfer characteristic curve
in Fig. 19.14, we have,
IDSS = 12 mA
VGS (off) = − 5 V
2
⎡ VGS ⎤
∴ ID = I DSS ⎢1 − V ⎥
⎣ GS (off ) ⎦

2
ID = 12 ⎡1 + GS ⎤ mA Ans.
V Fig. 19.14
or
⎢⎣ 5 ⎥⎦ Fig. 19.15 Fig. 19.16
Example 19.2. A JFET has the following parameters: IDSS = 32 mA ; VGS (off) = – 8V ; VGS
Example 19.5. Determine the value of drain current for the circuit shown in Fig. 19.16.
= – 4.5 V. Find the value of drain current.
Solution. It is clear from Fig. 19.16 that VGS = – 2V. The drain current for the circuit is given by;
2
⎡ VGS ⎤ 2
Solution. ID = I DSS ⎢1 − ⎥ ⎛ ⎞
ID = IDSS ⎜ 1 − VGS ⎟
⎣ VGS (off ) ⎦ ⎜ ⎟
⎝ VGS (off ) ⎠
2
(− 4.5) ⎤
= 32 ⎡1 −
2
⎢⎣ − 8 ⎥⎦
mA = 3 mA ⎛⎜1 − − 2V ⎞⎟
⎝ − 6V ⎠
= 6.12 mA = (3 mA) (0.444) = 1.33 mA
Example 19.3. A JFET has a drain current of 5 mA. If IDSS = 10 mA and VGS (off) = – 6 V, find the Example 19.6. A particular p-channel JFET has a VGS (off) = + 4V. What is ID when VGS = + 6V?
value of (i) VGS and (ii) VP.
Solution. The p-channel JFET requires a positive gate-to-source voltage to pass drain current
2
⎡ VGS ⎤ ID. The more the positive voltage, the less the drain current. When VGS = 4V, ID = 0 and JFET is cut
Solution. ID = I DSS ⎢1 − V ⎥ off. Any further increase in VGS keeps the JFET cut off. Therefore, at VGS = + 6V, ID = 0A.
⎣ GS (off ) ⎦

2 19.12 Advantages of JFET

or 5 = 10 ⎡1 + VGS ⎤
⎣⎢ 6 ⎦⎥ A JFET is a voltage controlled, constant current device (similar to a vacuum pentode) in which
variations in input voltage control the output current. It combines the many advantages of both
VGS bipolar transistor and vacuum pentode. Some of the advantages of a JFET are :
or 1+ = 5 /10 = 0.707
6 (i) It has a very high input impedance (of the order of 100 MΩ). This permits high degree of
(i) ∴ VGS = − 1.76 V isolation between the input and output circuits.
(ii) and VP = − VGS (off) = 6 V (ii) The operation of a JFET depends upon the bulk material current carriers that do not cross
junctions. Therefore, the inherent noise of tubes (due to high-temperature operation) and those of
Example 19.4. For the JFET in Fig. 19.15, VGS (off) = – 4V and IDSS = 12 mA. Determine the
transistors (due to junction transitions) are not present in a JFET.
minimum value of VDD required to put the device in the constant-current region of operation.
(iii) A JFET has a negative temperature co-efficient of resistance. This avoids the risk of thermal
Solution. Since VGS (off) = – 4V, VP = 4V. The minimum value of VDS for the JFET to be in
runaway.
constant-current region is
VDS = VP = 4V (iv) A JFET has a very high power gain. This eliminates the necessity of using driver stages.
In the constant current region with VGS = 0V, (v) A JFET has a smaller size, longer life and high efficiency.
ID = IDSS = 12 mA 19.13 Parameters of JFET
Applying Kirchhoff’s voltage law around the drain circuit, we have, Like vacuum tubes, a JFET has certain parameters which determine its performance in a circuit. The
VDD = VDS + VR = VDS + ID RD main parameters of a JFET are (i) a.c. drain resistance (ii) transconductance (iii) amplification factor.
D
(i) a.c. drain resistance (rd). Corresponding to the a.c. plate resistance, we have a.c. drain
= 4V + (12 mA) (560Ω) = 4V + 6.72V = 10.72V
resistance in a JFET. It may be defined as follows :
This is the value of VDD to make VDS = VP and put the device in the constant-current region.

Field Effect Transistors 517 518 Principles of Electronics

It is the ratio of change in drain-source voltage (ΔVDS) to the change in drain current (ΔID) at V 15 V
∴ Gate to source resistance = GS = −9 = 15 × 109 Ω = 15,000 MΩ Ω
constant gate-source voltage i.e. IG 10 A
Δ VDS This example shows the major difference between a JFET and a bipolar transistor. Whereas the
a.c. drain resistance, rd = at constant VGS
Δ ID input impedance of a JFET is several hundred MΩ, the input impedance of a bipolar transistor is only
For instance, if a change in drain voltage of 2 V produces a change in drain current of 0.02 mA, then, hundreds or thousands of ohms. The large input impedance of a JFET permits high degree of isolation
between the input and output.
2V
a.c. drain resistance, rd = = 100 k Ω Example 19.8. When VGS of a JFET changes from –3.1 V to –3 V, the drain current changes
0.02 mA
from 1 mA to 1.3 mA. What is the value of transconductance ?
Referring to the output characteristics of a JFET in Fig. 19.8, it is clear that above the pinch off
voltage, the change in ID is small for a change in VDS because the curve is almost flat. Therefore, Solution. ΔVGS = 3.1 − 3 = 0.1 V ... magnitude
drain resistance of a JFET has a large value, ranging from 10 kΩ to 1 MΩ. ΔID = 1.3 − 1 = 0.3 mA
(ii) Transconductance ( g f s ). The control that the gate voltage has over the drain current is Δ ID 0.3 mA
∴ Transconductance, gf s = = = 3 mA/V = 3000 µ mho
measured by transconductance gf s and is similar to the transconductance gm of the tube. It may be ΔVGS 0.1V
defined as follows :
Example 19.9. The following readings were obtained experimentally from a JFET :
It is the ratio of change in drain current (ΔID) to the change in gate-source voltage (ΔVGS) at
VGS 0V 0V − 0.2 V
constant drain-source voltage i.e.
Δ ID VDS 7V 15 V 15 V
Transconductance, gf s = at constant VDS ID 10 mA 10.25 mA 9.65 mA
Δ VGS
Determine (i) a. c. drain resistance (ii) transconductance and (iii) amplification factor.
The transconductance of a JFET is usually expressed either in mA/volt or micromho. As an
example, if a change in gate voltage of 0.1 V causes a change in drain current of 0.3 mA, then, Solution. (i) With VGS constant at 0V, the increase in VDS from 7 V to 15 V increases the drain
0.3 mA −3
current from 10 mA to 10.25 mA i.e.
Transconductance, gf s = = 3 mA/V = 3 × 10 A/V or mho or S (siemens) Change in drain-source voltage, ΔVDS = 15 − 7 = 8 V
0.1 V
−3 6
= 3 × 10 × 10 µ mho = 3000 µ mho (or μS) Change in drain current, ΔID = 10.25 − 10 = 0.25 mA
(iii) Amplification factor ( µ ). It is the ratio of change in drain-source voltage (ΔVDS) to the Δ VDS 8V
∴ a.c. drain resistance, rd = = = 32 kΩ Ω
change in gate-source voltage (ΔVGS) at constant drain current i.e. Δ ID 0.25 mA
Δ VDS (ii) With VDS constant at 15 V, drain current changes from 10.25 mA to 9.65 mA as VGS is
Amplification factor, µ = at constant ID changed from 0 V to – 0.2 V.
ΔV GS
Δ VGS = 0.2 − 0 = 0.2 V
Amplification factor of a JFET indicates how much more control the gate voltage has over drain
current than has the drain voltage. For instance, if the amplification factor of a JFET is 50, it means Δ ID = 10.25 − 9.65 = 0.6 mA
that gate voltage is 50 times as effective as the drain voltage in controlling the drain current. Δ ID 0.6 mA
∴ Transconductance, gf s = = = 3 mA/V = 3000 µ mho
ΔVGS 0.2 V
19.14 Relation Among JFET Parameters 3 −6
(iii) Amplification factor, µ = rd × gfs = (32 × 10 ) × (3000 × 10 ) = 96
The relationship among JFET parameters can be established as under :
Δ VDS 19.15 Variation of Transconductance (gm or gfs) of JFET
We know µ =
ΔVGS We have seen that transconductance gm of a JFET is the ratio
Multiplying the numerator and denominator on R.H.S. by ΔID, we get, of a change in drain current (ΔID) to a change in gate-source
voltage (ΔVGS) at constant VDS i.e.
Δ VDS Δ I D ΔVDS Δ I D
µ = × = × ΔI D
ΔVGS Δ I D Δ I D ΔVGS gm =
ΔVGS
∴ µ = rd × g f s The transconductance gm of a JFET is an important pa-
i.e. amplification factor = a.c. drain resistance × transconductance rameter because it is a major factor in determining the volt-
Example 19.7. When a reverse gate voltage of 15 V is applied to a JFET, the gate current is age gain of JFET amplifiers. However, the transfer charac-
−3
10 µA. Find the resistance between gate and source. teristic curve for a JFET is nonlinear so that the value of gm
−3 −9 depends upon the location on the curve. Thus the value of gm
Solution. VGS = 15 V ; IG = 10 µA = 10 A at point A in Fig. 19.17 will be different from that at point B.
Luckily, there is following equation to determine the value of
gm at a specified value of VGS : Fig. 19.17
 Field Effect Transistors 519 520 Principles of Electronics
⎛ VGS ⎞ 19.17 JFET Biasing by Bias Battery
gm = gmo ⎜ 1 − ⎟⎟
⎜ Fig. 19.18 shows the biasing of a n-channel JFET by a bias battery
⎝ VGS (off ) ⎠
where gm = value of transconductance at any point on the transfer characteristic curve – VGG. This method is also called gate bias. The battery voltage – VGG
ensures that gate – source junction remains reverse biased.
gmo = value of transconductance(maximum) at VGS = 0
Since there is no gate current, there will be no voltage drop
Normally, the data sheet provides the value of gmo. When the value of gmo is not available, you
across RG.
can approximately calculate gmo using the following relation :
∴ VGS = VGG
2 I DSS We can find the value of drain current ID from the following
gmo =
| VGS (off ) | relation :
2
⎛ VGS ⎞
Example 19.10. A JFET has a value of gmo = 4000 μS. Determine the value of gm at VGS = – 3V. ID = IDSS ⎜ 1 − ⎟⎟
⎜
Given that VGS (off) = – 8V. ⎝ VGS (off ) ⎠
Solution. The value of VDS is given by ;
⎛ VDS = VDD – ID RD Fig. 19.18
VGS ⎞
gm = gmo ⎜⎜ 1 − ⎟⎟
⎝ VGS (off ) ⎠ Thus the d.c. values of ID and VDS stand determined. The operating point for the circuit is VDS, ID.

⎛ – 3V ⎞ Example 19.12. A JFET in Fig. 19.19 has values of VGS (off) = – 8V and IDSS = 16 mA. Determine
= 4000 μS ⎜ 1 –
⎝ – 8V ⎟⎠ the values of VGS, ID and VDS for the circuit.
Solution. Since there is no gate current, there will be no
= 4000 μS (0.625) = 2500 μS
voltage drop across RG.
Example 19.11. The data sheet of a JFET gives the following information : IDSS = 3 mA, VGS (off) ∴ VGS = VGG = – 5V
= – 6V and gm (max) = 5000 μS. Determine the transconductance for VGS = – 4V and find drain 2
current ID at this point. ⎛ VGS ⎞
Now ID = IDSS ⎜ 1 −
⎜ ⎟⎟
Solution. At VGS = 0, the value of gm is maximum i.e. gmo. ⎝ VGS (off ) ⎠
∴ gmo = 5000 μS 2
⎛ −5⎞
= 16 mA ⎜ 1 −
⎛ VGS ⎞ ⎝ − 8 ⎠⎟
Now gm = gmo ⎜⎜1 − V ⎟⎟
⎝ GS (off ) ⎠ = 16 mA (0.1406) = 2.25 mA
⎛ – 4V ⎞ Also VDS = VDD – ID RD
= 5000 μS ⎜1 – – 6V ⎟ Fig. 19.19
⎝ ⎠ = 10 V – 2.25 mA × 2.2 kΩ = 5.05 V
= 5000 μS ( 1/3) = 1667 μS Note that operating point for the circuit is 5.05V, 2.25 mA.
2
⎛ VGS ⎞
Also ID = IDSS ⎜1 − ⎟⎟ 19.18 Self-Bias for JFET
⎜
⎝ VGS (off ) ⎠ Fig. 19.20 shows the self-bias method for n-channel JFET. The re-
2
⎛ −4⎞ sistor RS is the bias resistor. The d.c. component of drain current
= 3 mA ⎜ 1 − = 333 μA
⎝ − 6 ⎠⎟ flowing through RS produces the desired bias voltage.
Voltage across RS, VS = ID RS
19.16 JFET Biasing
Since gate current is negligibly small, the gate terminal is at
For the proper operation of n-channel JFET, gate must be negative w.r.t. source. This can be achieved d.c. ground i.e., VG = 0.
either by inserting a battery in the gate circuit or by a circuit known as biasing circuit. The latter
∴ VGS = VG − VS = 0 − ID RS
method is preferred because batteries are costly and require frequent replacement.
1. Bias battery. In this method, JFET is biased by a bias battery VGG. This battery ensures that or VGS = − *ID RS
gate is always negative w.r.t. source during all parts of the signal. Thus bias voltage VGS keeps gate negative w.r.t. source.
Fig. 19.20
2. Biasing circuit. The biasing circuit uses supply voltage VDD to provide the necessary bias. ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

Two most commonly used methods are (i) self-bias (ii) potential divider method. We shall discuss * VGS = VG – VS = Negative. This means that VG is negative w.r.t. VS. Thus if VG = 2V and VS = 4V, then VGS
each method in turn. = 2 – 4 = – 2V i.e. gate is less positive than the source. Again if VG = 0V and VS = 2V, then VGS = 0 – 2 =
– 2V. Note that VG is less positive than VS.

Field Effect Transistors 521 522 Principles of Electronics

Operating point. The operating point (i.e., zero signal ID and VDS) can be easily determined. Example 19.16. Select resistor values in Fig. 19.22 to set up an approximate midpoint bias. The
Since the parameters of the JFET are usually known, zero signal ID can be calculated from the following JFET parameters are : IDSS = 15 mA and VGS (off) = – 8V. The voltage VD should be 6V (one-half of
relation : 2 VDD).
⎛ VGS ⎞
ID = I DSS ⎜ 1 − V ⎟ Solution. For midpoint bias, we have,
⎝ GS (off ) ⎠
I DSS 15 mA
Also VDS = VDD − ID (RD + RS) ID j = = 7.5 mA
2 2
Thus d.c. conditions of JFET amplifier are fully specified i.e. operating point for the circuit is VGS (off ) − 8
VDS, ID. and VGS = = = – 2.35 V
3.4 3.4
|VGS |
Also, RS = |VGS | 2.35V
|ID | ∴ RS = = = 313ΩΩ
| I | 7.5 mA
Note that gate resistor *RG does not affect bias because voltage across it is zero. D
Now VD = VDD – ID RD
Midpoint Bias. It is often desirable to bias a JFET near the midpoint of its transfer characteris-
tic curve where ID = IDSS/2. When signal is applied, the midpoint bias allows a maximum amount of V − VD 12V – 6V
∴ RD = DD = Ω
= 800Ω
drain current swing between IDSS and 0. It can be proved that when VGS = VGS (off) / 3.4, midpoint bias ID 7.5 mA
conditions are obtained for ID. Example 19.17. In a self-bias n-channel JFET, the operating point
2 2
⎛ VGS ⎞ ⎛ VGS (off ) / 3.4 ⎞ is to be set at ID = 1.5 mA and VDS =10 V. The JFET parameters are IDSS
ID = IDSS ⎜⎜ 1 − ⎟⎟ = IDSS ⎜⎜1 − ⎟ = 0.5 IDSS Fig. 19.22
⎝ VGS (off ) ⎠ ⎝ VGS (off ) ⎠⎟ = 5 mA and VGS (off) = − 2 V. Find the values of RS and RD. Given that
VDD = 20 V.
To set the drain voltage at midpoint (VD = VDD/2), select a value of RD to produce the desired
voltage drop. Solution. Fig. 19.23 shows the circuit arrangement.
2
Example 19.13. Find VDS and VGS in Fig. 19.21, given that ID = 5 mA. ⎛ VGS ⎞
ID = I DSS ⎜ 1 − V ⎟
Solution. ⎝ GS (off ) ⎠

VS = ID RS = (5 mA) (470 Ω) = 2.35 V ⎛ V ⎞

2

and VD = VDD – ID RD or 1.5 = 5 ⎜ 1 + GS ⎟

⎝ 2 ⎠
= 15V – (5 mA) × (1 kΩ) = 10V VGS
or 1+ = 1.5 / 5 = 0.55
∴ VDS = VD – VS = 10V – 2.35 V = 7.65V 2
Since there is no gate current, there will be no voltage drop across RG or VGS = − 0.9 V
and VG = 0. Now VGS = VG − VS
Now VGS = VG – VS = 0 – 2.35V = – 2.35 V
or VS = VG − VGS
Example 19.14. The transfer characteristic of a JFET reveals that
= 0 − (− 0.9) = 0.9 V
when VGS = – 5V, ID = 6.25 mA. Determine the value of RS required.
VS 0.9 V
Solution. ∴ RS = = = 0.6 k Ω
ID 1.5 mA
|VGS |
RS = = 5V = 800 Ω Applying Kirchhoff’s voltage law to the drain circuit,
| I D | 6.25 mA Fig. 19.21
we have,
Example 19.15. Determine the value of RS required to self-bias a p-channel JFET with IDSS = VDD = ID RD + VDS + ID RS
25 mA, VGS (off) = 15 V and VGS = 5V. Fig. 19.23
or 2 0 = 1.5 mA × RD + 10 + 0.9
Solution.
2 2 (20 − 10 − 0.9) V
⎛ VGS ⎞ ⎛ 5V ⎞ ∴ RD = = 6kΩ
ID = IDSS 1− 1− 2 1.5 mA
⎜⎜ ⎟⎟ = 25 mA ⎝⎜ 15 V ⎠⎟ = 25mA (1 – 0.333) = 11.1 mA
⎝ VGS (off ) ⎠ Example 19.18. In the JFET circuit shown in Fig. 19.24, find (i) VDS and (ii) VGS .
|VGS |
∴ RS = = 5V = 450 Ω Solution.
| I D | 11.1 mA (i) VDS = VDD − ID (RD + RS) = 30 − 2.5 mA (5 + 0.2) = 30 − 13 = 17 V
VGS = − ID RS = − (2.5 × 10−3) × 200 = − 0.5 V
○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

* RG is necessary only to isolate an a.c. signal from ground in amplifier applications. (ii)
 Field Effect Transistors 523 524 Principles of Electronics
D.C. potential of source of second stage to ground is
VS = ID RS = 9.15 mA × 0.22 kΩ = 2.01 V

19.19 JFET with Voltage-Divider Bias

Fig. 19.26 shows potential divider method of bias-
ing a JFET. This circuit is identical to that used for
a transistor. The resistors R1 and R2 form a voltage
divider across drain supply VDD. The voltage V2
(= VG)across R2 provides the necessary bias.
VDD
V2 = VG = × R2
R +R
1 2
Now V2 = VGS + ID RS
or VGS = V2 − ID RS
Fig. 19.24 The circuit is so designed that ID RS is larger
Example 19.19. Figure 19.25 shows two stages of JFET amplifier. The first stage has ID = than V2 so that VGS is negative. This provides cor-
2.15mA and the second stage has ID = 9.15mA. Find the d.c. voltage of drain and source of each rect bias voltage. We can find the operating point
stage w.r.t. ground. as under :
V − VGS
Solution. Voltage drop in 8.2 kΩ = 2.15 mA × 8.2 kΩ = 17.63 V ID = 2
RS
D.C. potential of drain of first stage w.r.t. ground is and VDS = VDD − ID (RD + RS)
VD = VDD − 17.63 = 30 − 17.63 = 12.37 V
Although the circuit of voltage-divider bias is
a bit complex, yet the advantage of this method of
biasing is that it provides good stability of the oper- Fig. 19.26
ating point. The input impedance Zi of this circuit is
given by ;
Zi = R1 || R2
Example 19.20. Determine ID and VGS for the JFET with voltage-divider bias in Fig. 19.27,
given that VD = 7V.
Solution.
VDD − VD 12V – 7V
ID = =
RD 3.3 kΩ
5V
= = 1.52 mA
3.3 kΩ
VS = ID RS = (1.52 mA) (1.8 kΩ) = 2.74V
VDD 12V
VG = R + R × R2 = 7.8 MΩ ×1 MΩ = 1.54V
1 2
Fig. 19.25 ∴ VGS = VG – VS = 1.54 V – 2.74 V = – 1.2V
D.C. potential of source of first stage to ground is Example 19.21. In an n-channel JFET biased by potential
VS = ID RS = 2.15 mA × 0.68 kΩ = 1.46 V divider method, it is desired to set the operating point at ID = 2.5
mA and VDS = 8V. If VDD = 30 V, R1 = 1 MΩ and R2 = 500 kΩ,
Voltage drop in 2 kΩ = 9.15 mA × 2 kΩ = 18.3 V find the value of RS. The parameters of JFET are IDSS = 10 mA
D.C. potential of drain of second stage to ground is and VGS (off) = – 5 V.
Solution. Fig. 19.28 shows the conditions of the problem. Fig. 19.27
VD = VDD − 18.3 = 30 − 18.3 = 11.7 V

Field Effect Transistors 525 528 Principles of Electronics

2
⎛ VGS ⎞
ID = I DSS ⎜ 1 − V ⎟
⎝ GS (off ) ⎠

2
⎛ V ⎞
or 2.5 = 10 ⎜1 + GS ⎟
⎝ 5 ⎠
VGS
or 1+ = 2.5/10 = 0.5
5
or VGS = − 2.5 V
VDD
Now, V2 = × R2
R1 + R2
30 × 500
=
1000 + 500
= 10 V Fig. 19.33
Now V2 = VGS + ID RS As for a given circuit, VDD and (RD + RS) are constant, therefore, exp. (i) is a first degree equation
or 10 V = − 2.5 V + 2.5 mA × RS and can be represented by a straight line on the drain characteristics. This is known as d.c. load line
for JFET and determines the locus of ID and VDS (i.e. operating point) in the absence of the signal. The
RS = 10 V + 2.5 V = 12.5 V d.c. load line can be readily plotted by locating the two end points of the straight line.
Fig. 19.28
∴
2.5 mA 2.5 mA (i) The value of VDS will be maximum when ID = 0. Therefore, by putting ID = 0 in exp. (i)
= 5 kΩ above, we get,
Max. VDS = VDD
19.20 JFET Connections This locates the first point B (OB = VDD) of the d.c. load line on drain-source voltage axis.
There are three leads in a JFET viz., source, gate and drain terminals. However, when JFET is to be (ii) The value of ID will be maximum when VDS = 0.
connected in a circuit, we require four terminals ; two for the input and two for the output. This VDD
difficulty is overcome by making one terminal of the JFET common to both input and output termi- ∴ Max. ID =
RD + RS
nals. Accordingly, a JFET can be connected in a circuit in the following three ways :
This locates the second point A (OA = VDD / RD + RS) of the d.c. load line on drain current axis.
(i) Common source connection (ii) Common gate connection
By joining points A and B, d.c. load line AB is constructed [See Fig. 19.33 (ii)].
(iii) Common drain connection
The operating point Q is located at the intersection of the d.c. load line and the drain curve which
The common source connection is the most widely used arrangement. It is because this connec-
corresponds to VGS provided by biasing. If we assume in Fig. 19.33 (i) that VGS = – 2V, then point Q
tion provides high input impedance, good voltage gain and a moderate output impedance. However,
is located at the intersection of the d.c. load line and the VGS = – 2V curve as shown in Fig. 19.33 (ii).
the circuit produces a phase reversal i.e., output signal is 180° out of phase with the input signal. Fig.
The ID and VDS of Q point are marked on the graph.
19.29 shows a common source n-channel JFET amplifier. Note that source terminal is common to
both input and output. Example 19.22. Draw the d.c. load line for the JFET amplifier shown in Fig. 19.34 (i).
Note. A common source JFET amplifier is the JFET equivalent of common emitter amplifier.
Both amplifiers have a 180° phase shift from input to output. Although the two amplifiers serve the
same basic purpose, the means by which they operate are quite different.

19.21 Practical JFET Amplifier

It is important to note that a JFET can accomplish faithful amplification only if proper associated
circuitry is used. Fig. 19.29 shows the practical circuit of a JFET. The gate resistor RG serves two
purposes. It keeps the gate at approximately 0 V dc ( Q gate current is nearly zero) and its large value
(usually several megaohms) prevents loading of the a.c. signal source. The bias voltage is created by
the drop across RS. The bypass capacitor CS bypasses the a.c. signal and thus keeps the source of the
JFET effectively at a.c. ground. The coupling capacitor Cin couples the signal to the input of JFET
amplifier.

Fig. 19.34
 Field Effect Transistors 529 530 Principles of Electronics
Solution. To draw d.c. load line, we require two end points viz., max VDS and max. ID points.
Max. VDS = VDD = 20V
This locates point B (OB = 20V) of the d.c. load line.
VDD
= 20V
Max. ID =
RD + RS (150 + 50) Ω
= 20V = 100 mA
200Ω
This locates point A (OA = 100 mA) of the d.c. load line. Joining A and B, d.c. load line AB is
constructed as shown in Fig. 19.34 (ii).
Example 19.23. Draw the d.c. load line for the JFET amplifier shown in Fig. 19.35 (i). Fig. 19.36 (i)
ΔI D
g m = ΔV
GS
id
or gm = v
gs
or id = gm vgs
Putting the value of id (= gm vgs) in eq. (i),
we have,
vout = gm vgs RAC
Now vin = vgs so that a.c. output voltage is
vout = gm vin RAC Fig. 19.36 (ii)
or vout /vin = gm RAC
But vout /vin is the voltage gain (Av) of the amplifier.
∴ Voltage gain, Av = gm RAC ... for loaded amplifier
Fig. 19.35 = gm RD ... for unloaded amplifier
Solution.
Max. VDS = VDD = 20V Example 19.24. The JFET in the amplifier of Fig. 19.37 has a transconductance gm = 1 mA/V.
If the source resistance RS is very small as compared to RG, find the voltage gain of the amplifier.
This locates the point B (OB = 20V) of the d.c. load line.
VDD 20V
Max. ID = R = 500Ω = 40 mA
D
This locates the point A (OA = 40 mA) of the d.c. load line.
Fig. 19.35 (ii) shows the d.c. load line AB.
19.24 Voltage Gain of JFET Amplifier
The a.c. equivalent circuit of JFET amplifier was developed in Art. 19.22 and is redrawn as Fig. 19.36
(i) for facility of reference. Note that R1 || R2 and can be replaced by a single resistance RT. Similarly,
RD || RL and can be replaced by a single resistance RAC (= total a.c. drain resistance). The a.c. equiva-
lent circuit shown in Fig. 19.36 (i) then reduces to the one shown in Fig. 19.36 (ii).
We now find the expression for voltage gain of this amplifier. Referring to Fig. 19.36 (ii), output
voltage (vout) is given by ;
vout = id RAC ... (i)
Remember that we define gm as :
Fig. 19.37
Solution.
Transconductance of JFET, gm= 1 mA/V

Field Effect Transistors 531 532 Principles of Electronics

–6
= 1000 μ mho = 1000 × 10 mho RD RL (3.3 kΩ) (4.7 kΩ)
= R + R = 3.3 kΩ + 4.7 kΩ = 1.94 kΩ
The total ac load (i.e. RAC) in the drain circuit consists of the parallel combination of RD and RL i.e. D L
–6 3
Total a.c. load, RAC = RD || RL ∴ Voltage gain, Av = gm RAC = (779 × 10 ) (1.94 × 10 ) = 1.51
12 × 8 Output voltage, vout = Av vin = 1.51 × 100 mV = 151 mV (r.m.s.)
= 12 kΩ || 8 kΩ = 12 + 8 = 4.8 kΩ
∴ Voltage gain, Av = gm × RAC 19.25 Voltage Gain of JFET Amplifier
–6 3
= (1000 × 10 ) × (4.8 × 10 ) = 4.8 (With Source Resistance RS)
Example 19.25. The transconductance of a JFET used as a voltage amplifier is 3000 μmho and Fig. 19.39 (i) shows the JFET amplifier with source resistor RS unbypassed. This means that a.c.
drain resistance is 10 kΩ. Calculate the voltage gain of the amplifier. signal will not be bypassed by the capacitor CS.
Solution.
Transconductance of JFET, gm = 3000 μmho = 3000 × 10–6 mho
3
Drain resistance, RD = 10 kΩ = 10 × 10 Ω
–6 3
∴ Voltage gain, Av = gm RD = (3000 × 10 ) (10 × 10 ) = 30
Example 19.26. What is the r.m.s. output voltage of the unloaded amplifier in Fig. 19.38? The
IDSS = 8 mA, VGS (off) = – 10V and ID = 1.9 mA.

Fig. 19.39
Fig. 19.39 (ii) shows the simplified a.c. equivalent circuit of the JFET amplifier. Since
gm = id/vgs, a current source id = gm vgs appears between drain and source. Referring to Fig. 19.39 (ii),
vin = vgs + id RS
vout = id RD
Fig. 19.38 vout id RD
∴ Voltage gain, Av = =
Solution. vin vgs + id RS
3
VGS = – ID RS = – 1.9 mA × 2.7 × 10 Ω = – 5.13V g m vgs RD g m vgs RD
2 I DSS 2 × 8 mA = = ( Q id = gm vgs)
gmo = = –3
= 1.6 × 10 S vgs + g m vgs RS vgs (1 + gm RS )
|VGS (off ) | 10 V
g m RD
⎛ VGS ⎞ ∴ Av = ... for unloaded amplifier
–3 ⎛ – 5.13V ⎞ –6 1 + g m RS
∴ gm = gmo ⎜⎜ 1 − ⎟⎟ = 1.6 × 10 ⎜⎝ 1 – – 10V ⎟⎠ = 779 × 10 S
⎝ VGS (off ) ⎠ gm RAC
–6 3 = ... for loaded amplifier
Voltage gain, Av = gm RD = (779 × 10 ) (3.3 × 10 ) = 2.57 1 + g m RS
∴ Output voltage, vout = Av vin = 2.57 × 100 mV = 257 mV (r.m.s.) Note that RAC (= RD || RL) is the total a.c. drain resistance.
Example 19.27. If a 4.7 kΩ load resistor is a.c. coupled to the output of the amplifier in Fig. Example 19.28. In a JFET amplifier, the source resistance RS is unbypassed. Find the voltage
19.38 above, what is the resulting r.m.s. output voltage? gain of the amplifier. Given gm = 4 mS; RD = 1.5 kΩ and RS = 560Ω.
Solution. The value of gm remains the same. However, the value of total a.c. drain resistance RAC Solution.
changes due to the connection of load RL (= 4.7 kΩ). g m RD
Voltage gain, Av =
Total a.c. drain resistance, RAC = RD || RL 1 + g m RS
–3 3
Here gm = 4mS = 4 × 10 S ; RD = 1.5 kΩ = 1.5 × 10 Ω ; RS = 560Ω
 Field Effect Transistors 533 Field Effect Transistors 539
−3 3 positive or negative voltage is applied to the gate. For this reason, the input impedance of D-MOSFET
(4 × 10 ) (1.5 × 10 ) 6
∴ Av = = = 1.85 is very high, ranging from 10,000 MΩ to 10,000,00 MΩ.
1 + (4 × 10 − ) (560) 1 + 2.24
3

(iv) The extremely small dimensions of the oxide layer under the gate terminal result in a very
If RS is bypassed by a capacitor, then,
–3 3 low capacitance and the D-MOSFET has, therefore, a very low input capacitance. This characteristic
Av = gm RD = (4 × 10 ) (1.5 × 10 ) = 6 makes the D-MOSFET useful in high-frequency applications.
Thus with unbypassed RS, the gain = 1.85 whereas with RS bypassed by a capacitor, the gain is 6.
Therefore, voltage gain is reduced when RS is unbypassed. 19.31 D-MOSFET Transfer Characteristic
Example 19.29. For the JFET amplifier circuit shown in Fig. 19.40, calculate the voltage gain Fig. 19.49 shows the transfer characteristic curve (or transconductance curve) for n-channel D-MOSFET.
with (i) RS bypassed by a capacitor (ii) RS unbypassed. The behaviour of this device can be beautifully explained with the help of this curve as under :
(i) The point on the curve where VGS = 0, ID = IDSS. It is expected because IDSS is the value of ID
when gate and source terminals are shorted i.e. VGS = 0.
(ii) As VGS goes negative, ID decreases below the value of IDSS till ID reaches zero when VGS =
VGS (off) just as with JFET.
(iii) When VGS is positive, ID increases above the value of IDSS. The maximum allowable value of
ID is given on the data sheet of D-MOSFET.

Fig. 19.40
Solution. From the d.c. bias analysis, we get, *ID = 2.3 mA and VGS = – 1.8V.
The value of gm is given by;
2 I DSS ⎛ VGS ⎞
gm = ⎜1 − ⎟
|VGS (off ) | ⎝⎜ VGS (off ) ⎠⎟ Fig. 19.49

2 × 10 ⎛ − 1.8 ⎞ Note that the transconductance curve for the D-MOSFET is very similar to the curve for a JFET.
1− =
= (5.7 mS) (0.486) = 2.77 mS
3.5 ⎜⎝ − 3.5 ⎟⎠ Because of this similarity, the JFET and the D-MOSFET have the same transconductance equation
viz.
(i) The voltage gain with RS bypassed is 2
⎛ VGS ⎞
Av = gm RD = (2.77 mS) (1.5 kΩ) = 4.155 ID = IDSS ⎜ 1 − ⎟⎟
⎜
⎝ VGS (off ) ⎠
(ii) The voltage gain with RS unbypassed is
g m RD
= 4.155 Example 19.30. For a certain D-MOSFET, IDSS = 10 mA and VGS (off) = – 8V.
Av = = 1.35
1 + g m RS 1 + (2.77 mS) (0.75 kΩ) (i) Is this an n-channel or a p-channel ?
19.26 JFET Applications (ii) Calculate ID at VGS = – 3V.
(iii) Calculate ID at VGS = + 3V.
The high input impedance and low output impedance and low noise level make JFET far superior to
the bipolar transistor. Some of the circuit applications of JFET are : Solution.
○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
(i) The device has a negative VGS (off). Therefore, it is n-channel D-MOSFET.
2
2 ⎛ VGS ⎞
⎡ VGS ⎤ (ii) ID = IDSS ⎜⎜ 1 − V ⎟⎟
* ID = IDSS ⎢1 − V ⎥ and VGS = – ID RS ⎝ GS (off ) ⎠
⎣⎢ ⎥
GS (off ) ⎦
2
⎛ − 3⎞
The unknown quantities VGS and ID can be found from these two equations. = 10 mA ⎜ 1 − = 3.91 mA
⎝ − 8 ⎠⎟

540 Principles of Electronics Field Effect Transistors 541

2
⎛ VGS ⎞
(iii) ID = IDSS ⎜⎜ 1 − ⎟⎟
⎝ VGS (off ) ⎠
2
⎛ + 3V ⎞
= 10 mA ⎜ 1 − = 18.9 mA
⎝ − 8V ⎠⎟
Example 19.31. A D-MOSFET has parameters of VGS (off) = – 6V and IDSS = 1 mA. How will you
plot the transconductance curve for the device ?
Solution. When VGS = 0 V, ID = IDSS = 1 mA and when VGS = VGS (off), ID = 0A. This locates two
points viz IDSS and VGS (off) on the transconductance curve. We can locate more points of the curve by
*changing VGS values.
2
⎛ – 3V ⎞
When VGS = – 3V ; ID = 1 mA ⎜ 1 – = 0.25 mA
⎝ – 6V ⎟⎠ Fig. 19.50 Fig. 19.51
2
⎛ − 1V ⎞ We can use the simple circuit of Fig. 19.51 to provide zero bias. This circuit has VGS = 0V and ID
When VGS = – 1V ; ID = 1 mA ⎜ 1 − = 0.694 mA
⎝ − 6V ⎠⎟ = IDSS. We can find VDS as under :
⎛ + 1V ⎞
2 VDS = VDD – IDSS RD
When VGS = + 1V ; ID = 1 mA ⎜ 1 − = 1.36 mA
⎝ − 6V ⎟⎠ Note that for the D-MOSFET zero bias circuit, the source resistor (RS) is not necessary. With no
2 source resistor, the value of VS is 0V. This gives us a value of VGS = 0V. This biases the circuit at ID =
⎛ + 3V ⎞
When VGS = + 3V ; ID = 1 mA ⎜ 1 − = 2.25 mA IDSS and VGS = 0V. For mid-point biasing, the value of RD is so selected that VDS = VDD/2.
⎝ − 6V ⎠⎟
Thus we have a number of VGS – ID readings so that transconductance curve for the device can be Example 19.32. Determine the drain-to-source voltage (VDS) in the circuit shown in Fig. 19.51
readily plotted. above if VDD = +18V and RD = 620Ω. The MOSFET data sheet gives VGS (off) = – 8V and IDSS = 12 mA.
Solution. Since ID = IDSS = 12 mA, the VDS is given by;
19.32 Transconductance and Input Impedance of D-MOSFET
VDS = VDD – IDSS RD
These are important parameters of a D-MOSFET and a brief discussion on them is desirable.
= 18V – (12 mA) (0.62 kΩ) = 10.6V
(i) D-MOSFET Transconductance (gm). The value of gm is found for a D-MOSFET in the
same way that it is for the JFET i.e. 19.34 Common-Source D-MOSFET Amplifier
⎛ VGS ⎞ Fig. 19.52 shows a common-source amplifier using n-channel D-MOSFET. Since the source terminal
gm = gmo ⎜⎜ 1 − ⎟⎟
⎝ VGS (off ) ⎠ is common to the input and output terminals, the circuit is called *common-source amplifier. The
(ii) D-MOSFET Input Impedance. The gate impedance of a D-MOSFET is extremely high. circuit is zero biased with an a.c. source coupled to the gate through the coupling capacitor C1. The
For example, a typical D-MOSFET may have a maximum gate current of 10 pA when VGS = 35V. gate is at approximately 0V d.c. and the source terminal is grounded, thus making VGS = 0V.
35V 35V 12
∴ Input impedance = = = 3.5 × 10 Ω
10 pA 10 ×10 –12 A
With an input impedance in this range, D-MOSFET would present virtually no load to a source
circuit.
19.33 D-MOSFET Biasing
The following methods may be used for D-MOSFET biasing :
(i) Gate bias (ii) Self-bias
(iii) Voltage-divider bias (iv) Zero bias
The first three methods are exactly the same as those used for JFETs and are not discussed here.
However, the last method of zero-bias is widely used in D-MOSFET circuits.
Zero bias. Since a D-MOSFET can be operated with either positive or negative values of VGS, we
can set its Q-point at VGS = 0V as shown in Fig. 19.50. Then an input a.c. signal to the gate can Fig. 19.52 Fig. 19.53
produce variations above and below the Q-point. ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

* It is comparable to common-emitter transistor amplifier.

* We can only change VGS because the values of IDSS and VGS (off) are constant for a given D-MOSFET.
542 Principles of Electronics Field Effect Transistors 545
2
Operation. The input signal (Vin) is capacitively coupled to the gate terminal. In the absence of ID = K (VGS – VGS (th))
the signal, d.c. value of VGS = 0V. When signal (Vin) is applied, Vgs swings above and below its zero The constant K depends on the particular E-MOSFET and its
value ( Q d.c. value of VGS = 0V), producing a swing in drain current Id. value is determined from the following equation :
(i) A small change in gate voltage produces a large change in drain current as in a JFET. This I D (on)
fact makes MOSFET capable of raising the strength of a weak signal; thus acting as an amplifier. K = 2
(VGS (on) − VGS (th) )
(ii) During the positive half-cycle of the signal, the positive voltage on the gate increases and
produces the enhancement-mode. This increases the channel conductivity and hence the drain cur- Any data sheet for an E-MOSFET will include the current ID(on)
rent. and the voltage VGS (on) for one point well above the threshold volt-
(iii) During the negative half-cycle of the signal, the positive voltage on the gate decreases and age as shown in Fig. 19.58.
produces depletion-mode. This decreases the conductivity and hence the drain current. Example 19.34. The data sheet for an E-MOSFET gives ID(on) Fig. 19.58
The result of above action is that a small change in gate voltage produces a large change in the = 500 mA at VGS = 10V and VGS (th) = 1V. Determine the drain
drain current. This large variation in drain current produces a large a.c. output voltage across drain current for VGS = 5V.
resistance RD. In this way, D-MOSFET acts as an amplifier. Fig. 19.53 shows the amplifying action of Solution. Here VGS (on) = 10 V.
2
D-MOSFET on transconductance curve. ID = K (VGS – VGS (th)) ... (i)
Voltage gain. The a.c. analysis of D-MOSFET is similar to that of the JFET. Therefore, voltage I D (on) 500 mA 2
Here K = = 2 = 6.17 mA/V
gain expressions derived for JFET are also applicable to D-MOSFET. (VGS (on) − VGS (th) )
2
(10V − 1V)
Voltage gain, Av = gm RD ... for unloaded D-MOSFET amplifier Putting the various values in eq. (i), we have,
= gm RAC ... for loaded D-MOSFET amplifier 2
ID = 6.17 (5V – 1V) = 98.7 mA
Note the total a.c. drain resistance RAC = RD || RL.
Example 19.35. The data sheet for an E-MOSFET gives ID (on) = 3 mA at VGS = 10V and VGS (th)
Example 19.33. The D-MOSFET used in the amplifier of Fig. 19.54 has an IDSS = 12 mA and gm = 3V. Determine the resulting value of K for the device. How will you plot the transconductance
= 3.2 mS. Determine (i) d.c. drain-to-source voltage VDS and (ii) a.c. output voltage. Given vin = 500 curve for this MOSFET ?
mV. Solution. The value of K can be determined from the following equation :
I D (on)
K = 2
(VGS (on) − VGS (th) )
Here ID (on) = 3 mA ; VGS (on) = 10V ; VGS (th) = 3V
3 mA 3 mA
∴ K = 2
= 2
= 0.061 × 10–3 A/V2
(10V − 3V) (7V)
2
Now ID = K (VGS – VGS (th))
In order to plot the transconductance curve for the device, we shall determine a few points for the
curve by changing the value of VGS and noting the corresponding values of ID.
–3 2
For VGS = 5V ; ID = 0.061 × 10 (5V – 3V) = 0.244 mA
For VGS = 8V ; ID = 0.061 × 10–3 (8V – 3V)2 = 1.525 mA
–3 2
For VGS = 10V ; ID = 0.061 × 10 (10V – 3V) = 3 mA
–3 2
For VGS = 12V ; ID = 0.061 × 10 (12V – 3V) = 4.94 mA
Fig. 19.54 Thus we can plot the transconductance curve for the E-MOSFET from these VGS/ID points.
Solution.
19.37 E-MOSFET Biasing Circuits
(i) Since the amplifier is zero biased, ID = IDSS = 12 mA.
One of the problems with E-MOSFET is the fact that many of the biasing circuits used for JFETs and
∴ VDS = VDD – IDSS RD
D-MOSFETs cannot be used with this device. For example, E-MOSFETs must have VGS greater than
= 15V – (12 mA) (0.62 kΩ) = 7.56V the threshold value (VGS (th)) so that zero bias cannot be used. However, there are two popular meth-
(ii) Total a.c. drain resistance RAC of the circuit is ods for E-MOSFET biasing viz.
RAC = RD || RL = 620Ω || 8.2 kΩ = 576Ω (i) Drain-feedback bias
(ii) Voltage-divider bias
∴ vout = Av × vin = (gm RAC) (vin)
–3 (i) Drain-feedback bias. This method of E-MOSFET bias is equivalent to collector-feedback
= (3.2 × 10 S × 576 Ω) (500 mV) = 922 mV
bias in transistors. Fig. 19.59 (i) shows the drain-feedback bias circuit for n-channel E-MOSFET. A

546 Principles of Electronics Field Effect Transistors 547

high resistance RG is connected between the drain and the gate. Since the gate resistance is superhigh, I D (on)
no current will flow in the gate circuit (i.e. IG = 0). Therefore, there will be no voltage drop across RG. K = 2
(VGS (on) − VGS (th) )
Since there is no voltage drop across RG, the gate will be at the same potential as the drain. This fact
is illustrated in the d.c. equivalent circuit of drain-feedback bias as in Fig. 19.59 (ii). 500 mA 2
= 2 = 6.17 mA/V [ Q VGS (on) = 10V]
∴ VD = VG and VDS = VGS (10V − 1V)
2 2 2
∴ ID = K (VGS – VGS (th)) = 6.17 mA/V (3.13V – 1 V) = 28 mA
∴ VDS = VDD – ID RD = 24V – (28 mA) (470Ω) = 10.8V
Example 19.37. Determine the values of ID and VDS for the circuit shown in Fig. 19.62. The
data sheet for this particular MOSFET gives ID (on) = 10 mA when VGS = VDS.

Fig. 19.59
The value of drain-source voltage VDS for the drain-feedback circuit is
VDS = VDD – ID RD
Since VDS = VGS , VGS = VDD – ID RD Fig. 19.62
Since in this circuit VDS = VGS ; ID = ID (on). Solution. Since in the drain-feedback circuit VGS = VDS ,
Therefore, the Q-point of the circuit stands determined. ∴ ID = ID (on) = 10 mA
(ii) Voltage-divider Bias. Fig. 19.60 shows voltage divider bias- The value of VDS (and thus VGS) is given by ;
ing arrangement for n-channel E-MOSFET. Since IG = 0, the analysis of VDS = VDD – ID RD
the method is as follows :
= 20V – (10 mA) (1 kΩ) = 20V – 10V = 10V
VDD
VGS = × R2 Example 19.38. Determine the value of ID for the circuit shown in Fig. 19.63. The data sheet for
R1 + R2
this particular MOSFET gives ID (on) = 10 mA at VGS = 10 V and VGS (th) = 1.5 V.
and VDS = VDD – ID RD
where ID = K (VGS – VGS (th))2 Fig. 19.60
Once ID and VDS are known, all the remaining quantities
of the circuit such as VD etc. can be determined.
Example 19.36. Determine VGS and VDS for the E-
MOSFET circuit in Fig. 19.61. The data sheet for this par-
ticular MOSFET gives ID (on) = 500 mA at VGS = 10V and
VGS (th) = 1V.
Solution. Referring to the circuit shown in Fig. 19.61,
we have,
VDD
VGS = × R2
R1 + R2
24V ×15 kΩ = 3.13V
=
(100 + 15) kΩ
The value of K can be determined from the following Fig. 19.61 Fig. 19.63
equation :
548 Principles of Electronics
Solution. The value of K can be determined from the following equation :
I D (on)
K= 2
(VGS (on) − VGS (th) )
10 mA –1 2
= 2 = 1.38 × 10 mA/V [ Q VGS (on) = 10V]
(10 V − 1.5V)
From the circuit, the source voltage is seen to be 0V. Therefore, VGS = VG – VS = VG – 0 = VG. The
value of VG (= VGS) is given by ;

VG (or VGS) =
VDD
× R2 = 10V ×1MΩ = 5V
R1 + R2 (1 + 1) MΩ
2
∴ ID = K (VGS – VGS (th))
= (1.38 × 10–1 mA/V2) (5V – 1.5V)2 = 1.69 mA
19.38 D-MOSFETs Versus E-MOSFETs
Table below summarises many of the characteristics of D-MOSFETs and E-MOSFETs

Devices:

Schematic
symbol:

Transconduc-
tance curve:

Modes of Depletion and Enhancement only.

operation: enhancement.

Commonly Gate bias Gate bias

used bias Self bias Voltage-divider bias
circuits: Voltage-divider bias Drain-feedback bias
Zero bias

MULTIPLE-CHOICE QUESTIONS
1. A JFET has three terminals, namely ....... (i) diode (ii) pentode
(i) cathode, anode, grid (iii) triode (iv) tetrode
(ii) emitter, base, collector 3. A JFET is also called ....... transistor.
(iii) source, gate, drain (i) unipolar (ii) bipolar
(iv) none of the above (iii) unijunction (iv) none of the above
2. A JFET is similar in operation to ....... valve. 4. A JFET is a ....... driven device.