CHAPTER 11

LATCHES AND FLIP-FLOPS

11.1 Introduction
11.2 Set-Reset Latch
11.3 Gated D Latch
11.4 Edge-Triggered D Flip-Flop
11.5 S-R Flip-Flop
11.6 J-K Flip-Flop
11.7 T Flip-Flop
11.8 Flip-Flops with Additional Inputs
 Sequential Circuits
• Sequential switching circuits have the property that the
output depends not only on the present input but also on
the past sequence of inputs.

• It means that those circuits must be able to “remember”

something about the past history of the inputs in order to
produce the present output.
 Latches and flip-flops

• Latches and flip-flops are commonly used memory devices in

sequential circuits.
– Latch: a memory element that has no clock input.
– Flip-flop: a memory element that has a clock input for changing
output in response to a data input.
• Several common types of latches and flip-flops are described
in this chapter: S-R type, D type, J-K type, T type.
 Feedback Circuit
• A circuit has feedback if the output of one of the gates is
connected back into the input of a gate in the circuit so as to
form a closed loop.
• Feedback in the circuit is needed to construct a switching circuit
that has memory.
Oscillator using odd number of inverters
• An oscillator can be created using any odd number of inverters.

• The oscillator waveform has a high and a low time that is the
sum of the propagation times of the inverters. For example, with
n inverters and with all having the same delay, the oscillator
waveform high time is (n + 1)/2 times the high-to-low (or low-
to-high) inverter propagation delay plus (n − 1)/2 times the low-
to-high (or high-to-low) inverter propagation delay.
 Simple Memory Elements
• A feedback loop which has two inverters in it has two stable
conditions (stable states).

• The simple loop of two inverters lacks any external means

of initializing the state to one of the stable states. The set-
reset latches in Section 11.2 will have inputs for this
initialization.
 Set-Reset Latch
• A simple latch can be constructed by introducing feedback into a
NOR-gate circuit.

• This circuit is said to have memory because its output depends

not only on the present inputs, but also on the past sequence of
inputs.
• If we restrict the inputs so that R = S = 1 is not allowed, the
stable states of the outputs P and Q are always complements,
that is, P = Q′.
 Cross-Couple Form of S-R Latch
• Cross-couple form and latch symbol

• If S = R = 1, the latch will not operate properly.

– First, P ≠ Q′ violates a basic rule of latch operation that requires the

latch outputs to be complements.
– Second, if S and R are simultaneously changed back to 0, P and Q
may both change to 1. Then, after the 1’s propagate through the gates,
P and Q will become 0 again, and the latch may continue to oscillate
if the gate delays are equal.
 Timing Diagram for S-R Latch
• ε represents the response time or delay time of the latch.
• The duration of the S (or R) input pulse must normally be at least
as great as ε in order for a change in the state of Q to occur. If S =
1 for a time less than ε, the gate output will not change and the
latch will not change state.
 Bistable Element
• Theoretically, the two-inverter circuit of Figure 11-2 and the set-reset of
Figure 11-3 can exist in a third stable state. This is the situation where
the voltage level at the output of the two inverters or gates is
approximately halfway between the voltage levels for a logic 0 and a
logic 1. This state is referred to as a metastable state.
• Even though a circuit in the metastable state will quickly enter a stable
state, events causing the circuit to enter the metastable state must be
avoided.
Inverter 1

Inverter 2
Next-State Equation of S-R Latch
• Q(t + ε) = R(t)′[S(t) + Q(t)] = R(t)′S(t) +R(t)′Q(t)
• P(t) = S(t)′Q(t)′

Q+ = SR′ + R′Q P = S′Q′

Stable states are circled. Note that

for all stable states, P = Q′ except
when S = R = 1. This is one of the
reasons S = R = 1 is not allowed.

Q+ = S + R′Q
(SR = 0)
A useful application of the S-R latch
• An useful application of the S-R latch is for de-bouncing
switches.

• As the switch leaves a, bounces occur at the R input; when the

switch reaches b, bounces occur at the S input.
 NAND Gate S-R Latch
• An alternative form of the S-R latch uses NAND gates.
• We will refer to this circuit as an S-R latch
 Gated Latches
• Gated latches have an additional input called the gate (enable) input. When it
is inactive, the state of the latch cannot change. A NAND-gate version of a
gated S-R latch is given below.
Q+ = SG + Q(R′ + G′) P = Q′ + RG

• The first reason that S = R = 1 input combination is not allowed is given

below .Note that P = Q′ whenever the latch is in a stable state except for the
input combination G = S = R = 1; consequently, S = R = 1 input combination
is disallowed.
 Karnaugh Map for Q+ (I)
• The second reason that Disallows S = R = 1 input combination can also
be illustrated by considering a change in G from 1 to 0 with S = R = 1.
• When G changes, both inputs to the basic S-R NAND gate latch change
from 0 to 1. Race conditions exist and the propagation delays of the
gates determine whether the latch Q oscillates or stabilizes with 0 or 1.

Example 1: 若所有的gates延遲相同，產生震盪(左圖)。
Example 2: 當左上角的NAND gate有較短的延遲則Q的值最終為0(中圖)。
Example 3: 當左下角的NAND gate有較短的延遲則Q的值最終為1(右圖)。

0→1 0→1→1 0→0→1

1→0→1→… 1→0 1→1

1→1 1→0
1→0→1→… 0→0→1
0→1 0→1→1
 Karnaugh Map for Q+ (II)
• The race condition 也可用Q+ 有static 1-hazard 來說明。當 SRGQ: 1111→ 1101.
Thus, when G: 1 → 0, it is possible to cause Q to remain at 0. That is, SRGQ :
1111→ 1101→ 1100 → 1100

Q+ = SG + Q(R′ + G′) = SG + QR′ + QG′

• Q+ has a static 1-hazard for SRGQ: 1101→ 1111. Thus, when G: 0 → 1, it is

possible for Q: 1 → 0 . But in this case Q is forced back to 1.
 Gated D Latch
• It can be obtained from a gated S-R latch by connecting S to D and R to D′.
• This latch is also referred to as a transparent latch since Q becomes equal to
D while G is active
 Timing Problem of Gated D Latch
• Most digital systems use a clock signal to synchronize the
change in outputs of the system’s flip-flops.
• It is not a practical approach that gated latches are used as flip-
flops where the clock signal is connected to the gate inputs of
the latches.
• For example: let Clk = 1 and x = 1. D = Q′ causes Q to change.
If Clk remains 1, the change in Q will feed back and cause Q
to change again. If Clk remains at 1, Q will oscillate.
 Flip-Flop
• To avoid this timing problem, more complicated flip-flops restrict
the flip-flop outputs to only change on an edge of the clock.
• If the inputs to the flip-flop only need to be stable for a short period
of time around the clock edge, then we refer to the flip-flop as edge-
triggered.

• The term master-slave flip-flop refers to a particular implementation

that uses two gated latches in such a way that the flip-flop outputs
only change on a clock edge.
 Edge-Triggered D Flip-Flop
• A D flip-flop has two inputs, D (data) and Ck (clock). The arrowhead on
the flip-flop identifies the clock input.
• If the output changes in response to a 0 to 1 transition on the clock input,
the flip-flop is triggered on the rising edge (positive edge). If the output
changes in response to a 1 to 0 transition on the clock input, the flip-flop
is triggered on the falling edge (or negative edge). An bubble on the
clock input indicates a falling-edge trigger.
D Flip-Flop (Rising-Edge Trigger)
• A rising-edge-triggered D flip-flop can be constructed from two
gated D latches and an inverter.
 Setup and Hold Times
• The propagation delay (tp) of a flip-flop is the time between the active
edge of the clock and the resulting change in the output.
• The D input must be held at a constant value for a period of time
before and after the active edge of the clock.
– Setup time (tsu): the amount of time that must be stable before the active
edge. D is allowed to change in the shaded area.
– Hold time (th): the amount of time that must be the same value after the
active edge. D is allowed to change in the shaded area.
 Minimum clock period
• Suppose the inverter has a propagation delay of 2 ns, and the flip-
flop has a propagation delay of 5 ns and a setup time of 3 ns.
S-R Flip-Flop (Rising-Edge Trigger)
• The circuit is often referred to as a master-slave flip-flop.
• When the clock changes from 1 to 0, the value of P is held in the master
latch and when the clock changes from 0 to 1, the Q value is latched in
the slave.

We can solve this problem if we only allow the S and R inputs to

change while the clock is high.
J-K Flip-Flop (Rising-Edge Trigger)
• The J-K flip-flop is an extended version of the S-R flip-flop.
The J input corresponds to S, and K corresponds to R.
T Flip-Flop (Falling-Edge Trigger)
• The T flip-flop, also called the toggle (切換) flip-flop, is
frequently used in building counters.
 T Flip-Flop Implementation
• One way to implement a T flip-flop is to connect the J and
K inputs of a J-K flip-flop together.
• Another way to realize a T flip-flop is with a D flip-flop and
an exclusive-OR gate
Flip-Flops with Additional Inputs
• ClrN and PreN are often referred to as asynchronous clear and
preset inputs because their operation does not depend on the clock.
 D Flip-Flop with Clock Enable
• When designing such systems, we may want some flip-flops to hold
existing data even though the data input may be changing.
• Gate the clock has two problems: AND gate delays may cause the
clock to arrive at some flip-flops at different times than at other flip-
flops, and if En changes at the wrong time, the flip-flop may trigger
due to the change in En. All results in loss of synchronization.
• Rather than gating the clock, a better way is to use a flip-flop with a
clock enable (CE)
Asynchronous Sequential Circuits
• Consider starting the circuit in total stable state xPQ = 111 and
changing x from 1 to 0. The table indicates that the next state is
PQ = 10
• Assume the inverter for x has a long delay.

• This incorrect state transition is due to the static 1-hazard in P+.

• This problem can be eliminated by designing the circuits to be
free of hazards.
 Asynchronous Sequential Circuit
• Even if the circuit is free of hazards, delays in the “wrong” places in the
circuit can also cause incorrect state transitions.
• Starting the circuit in total stable state xPQ = 010 and changing x to 1;
the next-state table indicates the next state should be PQ = 00
• If there is a large delay in the line labeled d, the circuit will transition to
state PQ = 11

• Essential hazards cannot be eliminated by modifying the circuit’s logic.

To prevent incorrect operation due to essential hazards, it is necessary to
control the delays in the circuit by inserting delays in the feedback loops,
Asynchronous Sequential Circuit
• A similar problem can exist if two (or more) inputs to an asynchronous
circuit can change.
• Consider starting in total state xyPQ = 1111 and changing both x and y
from 11 to 0 at the same time. The table indicates the next state should
be PQ = 11.
• If the y change propagates through the circuit first, then the circuit enters
total state xyPQ = 1011. Then after the x change propagates through the
circuit, the total state becomes xyPQ = 0011.
• If the x change propagates through the circuit first, the total state
becomes xyPQ = 0100. Then, after the y change propagates through the
circuit, the total becomes xyPQ = 0000
Asynchronous Sequential Circuit
• A similar race problem can occur if more than one state variable
changes.
• The total state xPQR = 0000 has next state PQR = 011 when x
changes from 0 to 1.
• If Q changes first, the circuit will transition to state PQR = 010
and then to PQR = 011.
• If R changes first, the circuit transitions to state PQR = 001 and
may stabilize there.