FPGA Implementation of Fast FIR Low Pass

Filter for EMG Removal from ECG Signal

Rakesh Chand, Pawan Tripathi, Abhishek Mathur, K. C. Ray

FIR lowpass filter for Electromyogram, here after referred as

Abstract- This paper presents the hardware implementation of EMG (Electrical activity due to muscle contractions lasting
fast FIR low pass filter for Electromyogram (EMG) removal around 50ms between DC and 10000Hz with an averag
from Electrocardiogram (ECG) signal. We designed the amplitude of 10% of the Full Scale Deflection (FSD) on the
architecture having less critical delay then convention FIR design
ECG) removal from ECG signal so that signal to noise ratio
and fast enough to remove EMG from ECG signal. We Proposed
branched tree architecture for adder connection to reduce the could be increased and to process data fast.
critical delay. The Proposed architecture has been implemented
on FPGA using Verilog Hardware Description Language (HDL). FIR digital filter works on a digital input (Quantized
Since coefficient quantization technique is used, so this Analog Signal) and produces a digital output. Designing an
implementation consumes lesser area that reduces the Hardware FIR filter involves arriving at the filter coefficients, which
consumption. We have used target device Virtex-5 (“xc5vlx110t-
represents the impulse response of filter. These coefficients,
2-ff1136”), which is a preferred device in the field for modern
Digital Signal Processing (DSP) applications. when linearly convoluted with the input signal results in the
desired output. We designed Branched Tree Adder (BTA)
connection FIR filter to remove EMG from ECG signal. Filter
Keywords-- Electromyogram, Electrocardiogram, Hardware
Description Language, Linear Time-Invariant (LTI) filter, Full
coefficient for FIR lowpass filter are generated using
Scale Deflection, Finite Impulse Response. MATLAB tool to increase its speed and for reducing the
hardware consumption we quantised coefficients in Q(16,14)
format where total bit length of coefficient is 16bit among
I. INTRODUCTION
them 14 bits are fraction and MSB represent the sign bit.
P HYSICAL condition of the heart is diagnosed with the
help of ECG. Where ECG [1], [2], [3], [4] is the recording
of the electrical activities of the heart generated by heart Rest of the paper structures as follows: section (II)
muscles on body surface. Health of heart is diagnosed in terms Describes the mathematical model of FIR filter, Section (III)
of HRV (Heart Rate Variability) [5]. It is defined as the Describes the various architecture of FIR filter, Section (IV)
variation in the R-R wave where R wave represents the peak of Includes simulation result by using Xilinx ISE simulator and
the QRS complex. Till this time numerous software MATLAB for result validation of proposed architecture,
approaches have been adopted for R wave detection. Various Section (V) presents Synthesis report: the device utilization
algorithms [6] have been suggested by the researchers for summary and macro- statistics, section (VI) Follows
detection of the QRS complex based on the noise present in Conclusion.
ECG signal. As software processing of the ECG is not very
fast so to get rid of this problem we are moving towards the II. LOW PASS FIR FILTER
fast hardware processing of the ECG signal.
Generally a digital filter system consists of an analog-to-
As original ECG signal contains various type of noise digital converter (for input signal sampling), microprocessor
(electrode contact noise, power line interface noise, muscle (specialized digital signal processor for signal processing), and
contraction noise) which can lead to falls detection of the QRS for converting digital signal back to analog, a digital-to-analog
complex which is not desired, so it is very essential to filter the converter
noise (a collective term for fluctuations or disturbances which
are not part of wanted signal or Which interfere with its
intelligibility or usefulness, such as muscle activity ) from the
ECG signal. This filtering permits the use of the low threshold
thereby increases the detection sensitivity. Digital bandpass
Input signal Output
filter [7], [8], [9] is used to filter out the interference present in signal
the ECG signal. Digital filters thus reduce the noise source and
improve the signal to noise ratio [9]. Here we designed the fast Fig. 1. Operation of digital filter.
Authors are from Indian Institute of Information Technology, Allahabad, According to Dr. U. Meyer- Basese [10], “Linear Time-
India Invariant (LTI) filter is the most common digital filter”. We

978-1-4244-8542-0/10/$26.00 ©2010 IEEE

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can design LTI filter by generating the filter coefficients which passband, in order to satisfy the stricter requirements in the
represents the impulse response of filter design. Coefficients in stopband.
linear convolution with the input sequence give the desired
output. Let Second, for most windows, the ripple is not uniform neither
in the passband nor in the stopband and generally it decreases
Y = f *x (1) when moving away from the transition band.

Where: f represents the filters impulse response, x represents A typical description of filter contains the specification of
the input signal, and y represents the convolved output. The passband ωp frequency, stopband ωs frequency, ideal gain and
linear convolution process is formally defined by allowed deviation (ripple) from the desired transfer function. A
special class of filter that satisfies above said criteria is called
(2) equiripple FIR filter [10]. Equiripple design method minimizes
Y [ n] = x[ n] * f [ n] = ∑ x[ k ] f [ n − k ] = ∑ f [ k ] x[ n − k ]
k k
the maximum deviation (ripple error) from the ideal transfer
function. This method is formulated as Chebyshev
approximation problem. It spread the weighted approximation
Here, Y [n] represents the output of the filter, x[n] represents
error evenly between the desired frequency response and
the digital input to the filter, f[k] represents the impulse actual frequency response across the passband and stopband of
response of the LTI filter and the operator ‘*’represents the the filter to minimizing the maximum error. So the resulting
convolution operation. The extent of the summation is design has ripple in passband as well as in stopband. In this
governed by k, which represents the extent of the impulse method, [14] following terms are defined Hd ( ω ) represents
response of the filter [10], [12]. A filter with a finite value for
the desired (real) frequency response of the filter. H (ω ) is the
k is said to be a Finite Impulse Response (FIR) filter.
frequency response of the designed filter. w ( ω ) is the
Class of digital filters that use only current and past input
frequency response of the weighting function. Weighting
samples and none of the filter's previous output samples, to
function gives the ability to the designer to choose the relative
obtain a current output sample value [13] are called FIR filter.
size of the error in different frequency bands. Below given
Because of that FIR filters are sometimes called non-recursive
table is showing the frequency response of linear phase filters.
filters. From time-domain point of view, the operation of FIR
filter is sometimes called a moving-average filter [13]. − j ω ( M −1 ) / 2 j( p / 2)L
H (ω ) = e e H * (ω ) (3)

TABLE I
DIFFERENT EXPRESSION OF H * ( e j ω ) FOR DIFFERENT TYPE OF
FILTER[16]

Case L jω
H*( e )
Case1- M odd 0
Symmetrical
impulse ( M −1) / 2
response ∑ n =0
a (n) cos(ωn)

Case2-M even 0
Symmetrical
Fig. 2. FIR filter of order L.
impulse ( M −1) / 2
response ∑ n =1
b(n) cos(ω (n − 1 / 2))
Equiripple Design Method for Linear Phase FIR filter
Case3- M odd 1
The design of an FIR low-pass filter using the window Anti-
design technique is simple and generally results in a filter with symmetrical
impulse ( M −1) / 2
relatively good performance. However, in two respects these
filters are not optimal: response ∑ n =1
c(n) sin(ωn)

First, the passband and stopband deviations are Case4-M even 1

approximately equal. Although it is common to require Anti-
passband deviation to be much smaller than stopband symmetrical ( M −1) / 2
deviation these parameters cannot be independently controlled impulse ∑ n =1
d (n) sin(ω (n − 1 / 2))
in the window design method. Therefore, with the window response
design method it is necessary to overdesign the filter in the
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Now the expressions for H*(ω) can be written as product Here, ‘S’ represents the sign bit, ‘M’ represents the non
of fixed function of ω, Q(ω) and a term P(w) which is a fractional magnitude and ‘MF’ represents the fractional
the sum of cosines. magnitude.
TABLE II
VALUES OF P ( ω ) AND Q ( ω )
III. FIR FILTER ARCHITECTURE
Case Q(ω) P(ω)
Case 1 1 ( M −1) / 2 FIR filter can be realized in various ways depending on
∑ n =0
a ' (n) cos(ωn) design issues, latency and filter operation. FIR filter
Case 2 Cos(ω/2) ( M / 2 −1) architectures are described in paper [12], [15], [16], [17].
∑ n =0
b' (n) cos(ωn)
Case 3 Sin(ω) ( M − 3) A. Low Pass Serial FIR Filter architecture
∑ n =0
c' (n) cos(ωn)
Below show figure shows the architecture of series FIR
Case 4 Sin(ω/2) ( M / 2 −1) filter it require one adder, one multiplier and one delaying unit.
∑ n =0
d ' (n) cos(ωn)
So with respect to hardware efficiency it is a good option but
FIR filter made using this architecture is very slow and
The weighted error of approximation E(ω) can be defined as : throughput of the device is very low
E (ω ) = W (ω )[ H d (ω ) − H * (ω )] (4)
E(ω) = W (ω)[Hd (ω) − P(ω)Q(ω)] (5)
As Q(w) is a function of frequency,
E (ω ) = W (ω )Q(ω )[ H d (ω ) / Q(ω ) − P (ω )] (6)
Then two more terms are defined
W ' (ω ) = W (ω )Q(ω ) (7)
Hd*( ω ) = Hd( ω )/Q( ω )
Now we can error function can written be as
E (ω ) = W '[ Hd (ω ) − P (ω )Q(ω )] (8)
Thus the Chebyshev approximation is about finding the set of
Fig. 3. Architecture of serial FIR Filter.
coefficients to minimize the maximum absolute value of
E (ω ) over the frequency bands in which the B. Low Pass Parallel FIR Filter architecture
approximation is being performed. Mathematically the
Chebyshev approximation problem may be written as It is the type of FIR filter architecture that process data
E (ω ) = min[max E (ω ) ] (9) parallely instead of processing one by one. It gives high
throughput on the cost of hardware. We can see from
Coefficients of the FIR filter are generated using the
architecture shown below that all adders are connected with
Matlab2007a FDA tool. The accuracy of the filter response
the output of previous adder such that the output which we get
depends on the word length of the filter coefficients; ideal
at the output terminal is the sum of the output of the all adders.
filter requires the filter coefficients of the infinite word length
It gives the valid output after 38 clock cycle (being a 37 order
which is practically not possible to implement on hardware,
filter) or in other words we can say that it having the latency of
due to hardware constrain. One approach to solve the problem
38 clock cycles except that one more problem which is
is to round off coefficients to a b-bit representation. This
associated with it is critical delay, which is very high and equal
reduces the hardware use [12], so to minimize the hardware
to sum of delay of one multiplier and 38 adder which may
use; we quantized the filter coefficients in to 16 bit data using
create the problem, to get rid of the high critical delay
the format Q16.14 [12]. Means in the 16 bit data length 1st bit
branched adder architecture is proposed which is shown in the
form MSB side denotes the sign of data called sign bit than 2nd
figure no5.
bit denotes the integer bit and rest 14 bit denotes the fraction
magnitude. Although minimization of filter coefficients affects Input
the performance of filter especially when no. of Tabs are very
high. Cft
TABLE III 0
NUMERIC REPRESENTATION FORMAT Q16.14- BIT DISTRIBUTION

MSB Bit Bit Bit Bit Bit Bit Bit

(15) (14) (13) (12) (11) (10) (9) (8)
S M MF MF MF MF MF MF Output
Bit Bit Bit Bit Bit Bit Bit LSB
(7) (6) (5) (4) (3) (2) (1) (0) Fig. 4. Architecture of parallel Low Pass FIR filter with series adder
MF MF MF MF MF MF MF MF connections.
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In parallel architecture of lowpass FIR filter (Fig. 4.), adders

are connected in branch tree form they add data parallely
instead of serial addition as it was connected in serial adder
FIR design so the advantage of this design compared to
previous design this that it reduces the critical delay of the FIR
filter architecture (Maximum delay offered by the design) .
Input
Cft

Fig. 6. Fast lowpass FIR filter response.

Fig. 7. ECG signal with EMG.

Fig. 5. Architecture of parallel Low Pass FIR filter with Branch Tree adder
connection.

Specifications of the designed lowpass FIR filter for EMG

removal from ECG signal are given below in the table.
TABLE IV
LOWPASS FILTER SPECIFICATIONS[1]

f1 (Hz) f1 (Hz) Rs (dB) Rp (dB) fs (Hz) Order

35 45 48.25 1.925 256 37

Fig. 8. ECG signal after Fast FIR lowpass filtering.
Rs represents the attenuation between frequencies f1 and f2 (the
transition band), Rp represents the ripple in the pass band, fs V. SYNTHESIS REPORT
represents the sampling frequency and the order of filter is one
less than the number of coefficients/Tabs, required to meet the This proposed design has been synthesized by using Xilinx
attenuation criteria. XST tool, targeting a FPGA device Virtex-5 (“xc5vlx110t-2-
ff1136”). The synthesis result achieved by Xilinx XST tool
shown in table V and table VI.
IV. SIMULATION RESULT AND DISCUSSION TABLE V
For the validation of proposed architecture, initially DEVICES UTILIZATION SUMMARY

mathematical equations are simulated with the help of

MATLAB. Synthetic ECG signal has been taken as an Input Device Utilization Summary
signal. For testing purpose MATLAB generated sampled data Logic Utilization Used Available Utilization
are used as input test vector for the Xilinx ISE 10.1 simulator. Number of Slice Registers 1808 69120 2%
This proposed VLSI architecture of running fast FIR lowpass Number of Slice LUTs 4722 69120 6%
filter has been described by verilog HDL. For the
Number of fully used LUT-FF 4722 1144 9%
implementation of prototype module here preferred input and pairs
output data formats are in 16-bit fixed point representation. Number of bonded IOBs 0 640 0%
The internal precession of each block has been chosen
Number of DSP48Es 38 64 59%
according to avoid maximum truncation error
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TABLE VI
HDL SYNTHESIS REPORT- MACRO STATICS
VII. REFERENCES
[1]. John R. Hampton”ECG Made Easy. Elsevier Health Sciences, 2008.
Component Name Number of Components [2]. Zainul Abedin and Robert,Conner ,ECG interpretation ‘The self
assessment approach, Blackwell Publishing, 2008.
[3]. John R. Hampton,”The ECG in Practice” Elsevier Health
#Multipliers 38 Sciences,2008.
[4]. A. Bayes de Luna, Basic Electrocardiography ‘normal and abnormal’
16x16-bit multiplier 38 ECG patterns, Blackwell Publishing,2007
[5]. S ChatlaPalli, H NAzeran, V Melarkod, R Krishnam, E Estrada, E.
Estrada, Y b Pamula, SCabrera, “Accurate Derivation of Heart Rate
#Adders/Subtractors 154 Variability Signal for Detection of Sleep Disordered Breathig in
Children” Proc.26th IEEE/EMBS Cancun Maxico sept. 1-5, 2004.
16-bit adder 76 [6]. Gary M. Friesen, Thomas C. Jannett, Manal Afify jadallah, Atandford L.
Yates, Stephen R. Quint, Troy Nagle ”A comparison of the Noise
sensitivity of Nine QRS Detection Algorithms” IEEE Tnas.Biol. Madi.
32-bit adder 78 Eng.vol37.no.1, 1990.
[7]. Gari D. Clifford, “Signal Processing Methods for Heart Rate
Variability” PhD. Thesis at St. Cross College, Oxford University, 2002.
64-bit adder 5 [8]. J.Fraden M.R. Neuman, ”QRS wave detection” Med. & Biol. Eng. &
Comput., 1980, vol.18, p.125-132.
# Registers 1808 [9]. Jiapu P and Tompkins WJ: A real-time QRS detection algorithm. IEEE
Trans.Bio med. Eng. 1985; vol.32: p. 230-236.
[10]. Dr. Ume Meyer-Basese ,Digital Singnal Processing with Field
Flip-Flops 1808 Programmable Gate Array, Springer-Verlag Berlin Heidelberg,
Newyork,2001.
# Xors 38 [11]. Shanthala S , S. Y. Kulkarni, 2009, High Speed and Low Power FPGA
Implementation of FIR Filter for DSP Applications, European Journal of
Scientific Research pp.19-28, Vol.31 No.1 (2009).
1-bit xor2 38 [12]. Richard G. Lyons, Understanding Digital signal Processing, New jersey
Prentice- Hall, 2004.
[13]. L.R. Rabiner and B. Gold, Theory and Applications of Digital Signal
Processing, New Jersey: Prentice-Hall, 1975.
VI. CONCLUSION [14]. Zhangwen Tang, Jie Zhang and Hao Min ,“A High-Speed,
Programmable,CSD Coefficient FIR Filter”, IEEE Transactions on
Powerful computer based software tools are commonly used Consumer Electronics, Vol 48, No. 4, 2002.
to perform the ECG signal filter. But when we talk about the [15]. Joseph B. Evans: Y. C. Limt and Bede Liu,“A High Speed
Programmable Digital FIR Filter” IEEE CH2847-2/90/0000 -0969
implementing filter on hardware, the biggest challenge is to '1990.
achieve specified speed of data processing at minimum [16]. Joseph B. Evans,” Efficient FIRFilter Architectures Suitable for FPGA
hardware cost. This paper presents a new design approach to Implementation” IEEE Trans on Circuits and Systems-11: Analog and
design the fast FIR lowpass filter for filtering EMG from ECG Digital.
[17]. John G. proakis, Dimitris G. Manoakis, Digital Signal Processing
signal. Figure1. showing the filter response and figure3. (Principles, algorithms, and applications), Prentice-Hall, New Delhi,
showing the MATLAB simulation result of designed filter. 1996.
The Filter has been designed, coded using Verilog-HDL and [18]. Practical FIR Filter Design in MATLAB R. Ricardo, A. Losada the
finally implemented on Virtex-5 FPGA (xc5vlx110t-3-ff1136) MathWorks, Inc. 2004.
device as a prototype to ASIC (Application Specific Integrated
Circuit).