Department of Electrical Engineering

National Institute of Technology,

Srinagar

Microprocessors

Credits: 4 Course code:

EET-352 L:3 T:1 P:0

Course Evaluation Scheme

Mid-Semester Continuous End-Semester

(26 marks) Assessment (24 marks) (50 marks)

Tutorial/assignments (8)
Quiz/Presentation (8)
Attendance/Class response (8)

B.Tech (6th Semester) Course Incharge: Dr. Zahid Afzal Thoker

Machine Cycle, Addressing Modes & Memory Interfacing

Machine Cycle

It is the time required by the microprocessor to complete the operation of accessing the memory
devices or I/O devices.
In a machine cycle various operations like opcode fetch, memory read, memory write, I/O
read, I/O write are performed.

T-State

Each clock cycle is called as T-state. Each machine cycle is composed of many clock cycles. Since,
the data and instructions, both are stored in the memory, the microprocessor performs fetch
operation to read the instruction or data and then execute the instruction.

The status signals: IO/M, S1, and S0 are generated at the beginning of each machine cycle.
The unique combination of these 3-status signals identify read or write operation and remain valid
for the duration of the cycle.

The time taken by any microprocessor to execute one instruction is calculated in terms of the
clock period.
The execution of instruction always requires read and writes operations to transfer data to or
from the microprocessor and memory or I/O devices.
Each read/ write operation constitutes one machine cycle (MC1).
Each machine cycle consists of many clock periods/ cycles, called T-states.

State-1 State-2 State-3 State-4 State-5 State-6 State-7

1 1

CLK period Leading edge Lagging edge

Machine cycle one MC1 Machine cycle two MC2

Instruction Cycle

An instruction cycle is defined as the time required to fetch and execute an instruction.
For executing any program, basically 2-steps are followed sequentially with the help of clocks.
a) Fetch b) Execute
The time taken by the microprocessor in performing the fetch and execute operations are called
fetch and execute cycle.
Thus, sum of the fetch and execute cycle is called the instruction cycle as indicated in Fig.

Each read or writes operation constitutes a machine cycle. The instructions of 8085 require 1-5
machine cycles each containing 3-6 states (clocks). The first machine cycle of any instruction is
always an Op-Code fetch cycle in which the processor decides the nature of instruction.
It is of at least 4-states. It may go up to 6-states.

T1 T2 T3 T4 T5 T6 T7

Fetch cycle Execute cycle

Instruction cycle = Fetch cycle + Execute cycle

Fetch cycle

In FC, microprocessor fetches opcode (the machine code of an instruction) from the memory.
During op-code FC, microprocessor provides address of next instructions to memory and
responding op-code reads and transfers this to instruction Register (IR). OPCODE FETCH
requires 4T-states. In case of slow memory the CPU has to wait till the memory sends the
opcode. The clock cycle for which the CPU waits is called “wait cycle”.

Execution cycle
It begins after FC. If the operand is GPR (general purpose register), execution is immediately
performed. But in some of the operations the data or operand address which are still in the
memory or I/O devices, the microprocessor will perform MEMR or MEMW or IO/R or IO/W
operations to complete this execution of the instruction.

MOV A,B opcode fetch = 4T

MVI A,25 opcode fetch + 1 MEMR = 4T + 3T = 7T

Timing diagram of op-code fetch in 8085 with an example of one-byte instruction

MOV B,C opcode = 41H T1 T2 T3 T4 T1 T2 T3

Memory Address = 1000 H

CLK
Add Data
IO/M S1=1 S0=1
1000H 41H IO/M= 0
S1, S0

A15-A8 10H Unspecified

AD7-AD0 00 H 41H opcode

ALE

RD

WR =1

• A low IO/M means microprocessor wants to communicate with memory.

• The microprocessor sends a high on status signal S1 and S0 indicating fetch operation.
• The microprocessor sends 16-bit address. AD bus has address in 1st clock of the 1st MC,T1.

• AD7 to AD0 address is latched in the external latch when ALE = 1.

• AD bus now can carry data.

• In T2, the RD control signal becomes low to enable the memory for read operation.

• The memory places opcode on the AD bus.

• The data is placed in the data register (DR) and then it is transferred to IR.

• During T3 the RD signal becomes high and memory is disabled.

• During T4 the opcode is sent for decoding and decoded in T4.

• The execution is also completed in T4 if the instruction is single byte.

Timing diagram of Memory Read

T1 T2 T3 T4 T1 T2 T3

CLK

A15-A8 Unspecified

AD7-AD0

ALE

Timing diagram of Memory Write

T1 T2 T3 T4 T1 T2 T3

CLK

Microprocessor Interfacing

In a microprocessor based system the designer has to select suitable memories and I/O devices
for performing his task and so they interface to the microprocessor.

Several memory chips and I/O devices are connected to a microprocessor.

Memory I/O devices

Address bus
Microprocessor
8085

Data bus

Control bus

An address decoding circuit is employed to select the required I/O device of a memory chip.
Figure shows the schematic of a decoder circuit.
If IO/M is high; decoder 2 is activated and the required I/O device is selected.
If IO/M is low, decoder 1 is activated and the required memory is selected.

Y0
Memory PROM
Y1 Y0
Chip PROM Enable Input Device
Select Y2 RAM Y1
Input Device
Signals Y3 RAM Y2
Output Device
Decoder-1 Y4 RAM Y3
Output Device
Decoder-2 Y4
Y5
Unused
Y5 Unused
IO/M Enable Y6 reserved
reserved
for I/O
Y7 Future
Devices Y6 for
Future
Select Y7
Signals

Memory Interfacing

During the execution of a program the microprocessor needs to access memory quite frequently to
read the instruction codes and enable that access.
The primary function of memory interfacing is that the microprocessor should be able to read
from and write into a given register of memory chip.

To perform these operations, the microprocessor should be able to:

1.Select chip 2.Identify the register 3. Enable the appropriate buffer

VCC

IO/M Y0
G2A G2B G1
A15 A Y1
Y2

A14 IC Y3
B
Y4
Y5

A13 C Y6
Y7

3 to 8 decoder

Here G1, G2A and G2B are enable signals. G1 is an active high signal where as G2A and G2B are
active low signals.
Thus, to enable the decoder G1 should be high and G2A and G2B should be low.

A, B and C are the select lines and Y0 to Y7, are output lines.

By applying the proper logic to these lines any one of the outputs can be selected.

The Intel 8085 uses 16-bit address bus for addressing memory chips and I/O devices, thus can
access 2^16 = 64kB memory and I/O devices. The entire memory address has been divided into 8
zones (0000 H to FFFF H). Address lines A15, A14 and A13 have been applied to the select line A,
B and C of 74LS138 . The logic applied to these lines selects a particular memory device (EPROM
or RAM). Rest of the address lines (A12-A0) directly connected to the memory chip thus decide
the address of memory location. IO/M is connected to G2B, it goes low for memory read/write
operations. G1 is connected to Vcc and G1A is grounded.

Interfacing of ROM with 8085 Microprocessor (MPU)

A15 D7
A12
A11 MPU
A0
RD D0
Address
Decoder
Data bus

Address OE D0
bus A0 4Kx8
A11 ROM
CS D7

Interfacing of ROM with MPU

The chip is first enabled by sending a low (0) to CS input of ROM.

The required address is sent on the address bus by the MPU. The built in decoder of ROM connects
to the required 12 bit address. A short time later a low (0) on the Read line enables the output (OE)
of the ROM.
Stored data is placed on the data bus and fed to the MPU.

In this one critical time limitation is the Read Access Time, i.e. the time it takes to locate the correct
memory word (byte) after the chip is enabled, by the ROM's internal decoder.

Thus while interfacing the MPU with the ROM, the important considerations are addressing and timing.

Since a ROM can only be read, the data bus will be in the output mode only and the Read line only
will be connected to it.

The Data output from the ROM is first moved to the Accumulator of the MPU and then processed.

Like wise, data input to the input port register is moved to the Accumulator and then moved to memory
location.

Interfacing of RAM with 8085 Microprocessor (MPU)

The internal decoder of the RAM chooses A15 D7

the required 12 bit address word. A12
A11
The difference between ROM and RAM is A0 MPU
the write line. WR
RD D0
When the write WR of the MPU is Low, Address
R/W is enabled and a word can be Decoder
written at the chosen address.
Data bus

OE
If WR line carries a HIGH and RD line
D0
carries a Low, the output is enabled and R/W
Address
data from the required address is placed on A0 4Kx8
bus
the output terminal. RAM
A11
D7
CS

Memory Word Size

The size of the memory chip is specified in terms of the total number of bits it can store.

The memory size in a given system is specified in terms of bytes. Hence, it is essential to
design a byte size memory word.

n
The size of memory = 2 x M bits
Where, M = data lines
n = number of address lines

10
For e.g. a memory chip size of 2 x 4 = 1024 x 4 has 1024 memory location and each memory
location can store 4-bits.
Thus, it can store total of (1024 x 4 = 4096 bits).

To design a 1 KB (1024 x 8) memory we required two chips such that, each chip will provide
four data lines.

Memory Size Expansion

In many applications the capacity 2n x M of the single available memory chip is not sufficient.
The process of increasing the capacity of memory chip is known as memory expansion.

Expansion of word size (increasing M) Expansion of word capacity (increasing n)

Expansion of word size (increasing M)

If we have to interface 8 K x 8 chip and the available chip is 8K x 4; then this conversion
will require expansion of word size from 4 to 8

Expansion of word capacity (increasing n)

If the available chips are 16K x 4 and we want to have 32K x 4 memory then, the word
capacity expansion is required.
Thus this conversion require expansion of word capacity from 16 to 32

If word size (data lines) are different then the memory chips are connected in parallel with same
chip selection.
If word capacity is different the required chips are connected in cascade with different chip
selection.

Example: In 4 KB RAM, Calculate the number of memory locations, width of address bus, width
of data-bus, total number of chips to make 16 KB memory

The size of memory

The size of the memory can be determined from the given memory range e.g.: The size of the
memory whose range is 9000 H to AFFF H is given by

AFFF
-9000

1FFF
+1

2000 H

Example: If the initial address of a 4 K memory is 4000 H then the address of last byte will be:

Example: Interface 4K x 8 EPROM and 2K x 8 RAM to 8085 if available chips are 1K x 4 RAM
and 2K x 8 EPROM:

B.Tech (6th Semester) Course Incharge: Dr. Zahid Afzal Thoker