Name: CS120 Fall 2023 Final Prep N

1 Definition Questions [1 point each]

a. Intentionally restricting design choices: discipline
b. Hiding details when they aren’t important abstraction
c. Dividing a system into modules and submodules: hierarchy
d. Encouraging uniformity, so modules can be reused: regularity
e. Having well-defined functions and interfaces: modularity

2 Convert from Decimal to 8-bit (2 digit) hex in 2’s complement

43 -17
43 = 32 + 8 + 2 + 1 17 = 16 + 1
0010 1011 0001 0001
0x2B 1110 1111 (flip and add 1)
0xEF

3
Simplify the following Boolean equation
Y = (ABC + AB!C)(!A!B + C)
(AB)(C + !C)(!A!B + C)
AB(!A!B + C)
A!AB!B+ABC)
ABC

4
Fill out the Karnaugh map, and simplify. 4 inputs ABCD, with
1 for m2, m3, m7, m9, m14
X for m0, m4, m12, m13, m15

AB AB
00 01 11 10 Simplified circuit:
CD AB + A!CD + !ACD + !A!BC
X X X
00
There are other valid answers
01 X 1 A !CD (the !A CD could shift right,
or we could have the !A!BC wrap
!A CD around top to bottom, for
11 1 1 X
example)

10 1 1
!A !B C
Name: CS120 Fall 2023 Final Prep N

5 The machine code for the TinyProc is formatted DR SR1 SR2 OpCode or DR value OpCode
2 bits for the registers, or 4 bits (in 2’s complement) for immediate mode
The op codes are 00: ADD 01: SUB 10: MUL 11: LDI
Convert the following machine code values into assembly language
0x17 0x77 0x86
00010111 binary
01110111 binary 10000110 binary
00 0101 11 split for LDI
01 1101 11 split for LDI 10 00 01 10 split for SUB
ldi r0, 5
ldi r1, -3 sub r2, r0, r1

6 Consider the MIPS assembly code below, and answer the questions. The data segment
starts at 0x10010000, and the text segment starts at 0x400000
What number (in hex) is in $t0
.data when the code runs?
0x10010000 — this is WHERE x is
x: .word 33
y: .word 100 What number (in decimal) is in $s1
z: .word 42 when the code runs?
.text 33 - that’s the number stored at x
main: la $t0, x
lw $s1, 0($t0) What number (in decimal) is in $s2
lw $s2, 4($t0) when the code runs?
100 - that’s the value four bytes past
the address of x
7 You have to write a subroutine “foo” in MIPS assembly. This subroutine will use
the register $s2 to do some work, and also needs to call another subroutine.
At the start of the subroutine, you’ll need to do something with the stack, and then
something else just before you return. Write the things you’ll do in MIPS assembly.

At the start of foo At the end of foo

addi $sp, $sp, -8 lw $ra, 0($sp)

sw $ra, 0($sp) lw $s2, 4($sp)
sw $s2, 4($sp) addi $sp, $sp, 8

# Order of ra and s2 jr $ra

# could swap.
# We push both on the # Pop off ra and s2,
# stack # move stack pointer back,
# and then return
Name: CS120 Fall 2023 Final Prep N

8 Convert this C code into MIPS assembly. You can use the registers as suggested by
the variable names in the C code.

bne $t0, $0, else

if (t0 == 0) addi $s1, $s1, 4
{ j done
s1 = s1 + 4;
else:
} add $s2, $s0, $s1
else
{ done:
s2 = s0 + s1;
}

9 Translate this C code into MIPS assembly.

t1 = 10; li $t1, 10
li $t0, 0
t0 = 0; while: beq $t1,$0, done
while (t1 != 0)
{ add $t0, $t0, $t1
t0 = t0 + t1; addi $t1, $t1, -1
j while
t1 = t1 - 1;
} done:

10 Translate this C code into MIPS assembly.

# If this has not already

# been done, put ra on the stack!
// t2, s0, s1, are all # the jal will overwrite ra!
// integers. # Typically, ra goes on the
t2 = foo(s0, s1); # stack at the start of a function

move $a0, $s0

# add $a0, $s0, $0 works too
move $a1, $s1
jal foo
move $t2, $v0
Name: CS120 Fall 2023 Final Prep

11 We have a single-cycle processor, which has five stages. We’ll convert it to multi-cycle,
and then to pipelined. The stages are:
FETCH: 100ps
DECODE: 30ps
EXECUTE: 90ps
MEMORY: 70ps
WRITE BACK: 50ps

How long does an instruction take if this is a “single cycle” machine?

100+30+90+70+50 = 340
340 ps
How long does an instruction take if we use a multi-cycle approach (without pipeline)
Slowest step is fetch, at 100ps. 5 stages, so
500 ps
Ignoring hazards, a pipelined machine would complete an instruction every ???? ps…

Pipeline is limited by the slowest step — the instructions are overlapping.

We COMPLETE an instruction every 100ps

Yes, a single instruction still takes 500ps.. But we’re interested how often they
complete, and that’s every 100ps.

12 There are two major types of hazards for pipeline machines. Name both types, and
give MIPS examples for each

First type: Second type:

# DATA HAZARD # CONTROL HAZARD

add $s0, $s1, $s2 beq $t0, $t1, elsewhere
add $t0, $s0, $s0 add $t0, $t1, $t2

# NOTE the first line changes # NOTE that when we branch,

# $s0, and we use it again # we don’t know if we do the
# in the next line. That’s # next instruction or not - so
# the data hazard # the add might not happen.

13 Have you filled out the SOOT survey? If not, go do it! Today is the last day!