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The document is a VHDL testbench for a component called CHC_Accumulator_U_Accumulate. It includes signal declarations, clock generation, and a stimulus process to test the accumulator's functionality by applying various input values. The testbench sets up the necessary signals and timing to verify the behavior of the accumulator component.

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luuvuduc81
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3 views

FPGA

The document is a VHDL testbench for a component called CHC_Accumulator_U_Accumulate. It includes signal declarations, clock generation, and a stimulus process to test the accumulator's functionality by applying various input values. The testbench sets up the necessary signals and timing to verify the behavior of the accumulator component.

Uploaded by

luuvuduc81
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Accumulate_tb IS
END Accumulate_tb;

ARCHITECTURE behavior OF Accumulate_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT CHC_Accumulator_U_Accumulate
PORT(
CLOCK : IN std_logic;
DONE : OUT std_logic;
RESET : IN std_logic;
RESET_DONE : OUT std_logic;
START : IN std_logic;
TOTAL_O : OUT std_logic_vector(31 downto 0);
VALUE_I : IN std_logic_vector(31 downto 0)
);
END COMPONENT;

--Inputs
signal CLOCK : std_logic := '0';
signal RESET : std_logic := '0';
signal START : std_logic := '0';
signal VALUE_I : std_logic_vector(31 downto 0) := (others => '0');

--Outputs
signal DONE : std_logic;
signal RESET_DONE : std_logic;
signal TOTAL_O : std_logic_vector(31 downto 0);

-- Clock period definitions


constant CLOCK_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: CHC_Accumulator_U_Accumulate PORT MAP (
CLOCK => CLOCK,
DONE => DONE,
RESET => RESET,
RESET_DONE => RESET_DONE,
START => START,
TOTAL_O => TOTAL_O,
VALUE_I => VALUE_I
);

-- Clock process definitions


CLOCK_process :process
begin
CLOCK <= '0';
wait for CLOCK_period/2;
CLOCK <= '1';
wait for CLOCK_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
RESET <= '1';
START <= '0';
VALUE_I <= CONV_STD_LOGIC_VECTOR(0,32);
-- hold reset state for 100 ns.
wait for 100 ns;

RESET <= '0';

wait for CLOCK_period*10;

-- insert stimulus here


START <= '1';
VALUE_I <= CONV_STD_LOGIC_VECTOR(64,32);

wait for CLOCK_period;


START <= '0';

wait for CLOCK_period*3;


START <= '1';
VALUE_I <= CONV_STD_LOGIC_VECTOR(128,32);

wait for CLOCK_period;


START <= '0';

wait;
end process;

END;

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