a Next Generation OP07

Ultralow Offset Voltage Operational Amplifier

OP77
FEATURES PIN CONNECTIONS
Outstanding Gain Linearity
Ultrahigh Gain 5000 V/mV Min Epoxy Mini-Dip (P-Suffix)
Low VOS Over Temperature 60 ␮V Max 8-Pin Hermetic DIP
Excellent TCVos 0.3 ␮V/ⴗC Max
High PSRR 3 ␮V/V Max
VOS TRIM 1 8 VOS TRIM
Low Power Consumption 60 mW Max OP07
–IN 2 7 V+
Fits OP07, 725,108A/308A, 741 Sockets
+IN 3 6 OUT
Available in Die Form
V– 4 5 NC

NC = NO CONNECT

TO-99
GENERAL DESCRIPTION
(J-Suffix)
The OP77 significantly advances the state-of-the-art in precision
op amps. The OP77’s outstanding gain of 10,000,000 or more VOS TRIM
is maintained over the full 10 V output range. This exceptional
gain-linearity eliminates incorrectable system nonlinearities VOS TRIM 1
OP07
V+
common in previous monolithic op amps, and provides superior
performance in high closed-loop gain applications. Low initial –IN 2 OUT

VOS drift and rapid stabilization time, combined with only 50

+IN 3 NC
mW power consumption, are significant improvements over
previous designs. These characteristics, plus the exceptional 4V– (CASE)
TCVOS of 0.3 µV/°C maximum and the low VOS of 25 µV maxi- NC = NO CONNECT
mum, eliminates the need for VOS adjustment and increases
system accuracy over temperature.
PSRR of 3 µV/V (110 dB) and CMRR of 1.0 µV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding char-
acteristics makes the OP77 ideally suited for high-resolution
instrumentation and other tight error budget systems.

V+
7 R2A (OPTIONAL R2B R7
NOTE: NULL) C1
R2A AND R2B ARE 1 8
R1A R1B Q19
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY. Q9 Q10

Q11 Q12 R9 OUTPUT

Q7 Q8
Q5 Q3 Q6 Q4 6
C2 Q17 R10
NON- Q27 C3 Q16
3 R3
INVERTING R5
INPUT Q1 Q26 Q20
Q21 Q23
Q15
2 R4 Q22 Q24 Q25
INVERTING Q2 Q18
INPUT Q14

Q13 R6 R8
4
V–

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
OP77–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = ⴞ15 V, T = 25ⴗC, unless otherwise noted.)
s A

OP77A
Parameter Symbol Conditions Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 25 µV
LONG-TERM INPUT OFFSET
VOLTAGE STABILITY1 DVOS/Time 0.2 µV/Mo
INPUT OFFSET CURRENT IOS 0.3 nA
INPUT BIAS CURRENT IB –0.2 1.2 2.0 nA
INPUT NOISE VOLTAGE 2
enp-p 0.1 Hz to 10 Hz 0.35 0.6 µV p-p
2
INPUT NOISE VOLTAGE DENSITY en fO = 10 Hz 10.3 18.0 V
fO = 100 Hz 10.0 13.0
fO = 1000 Hz 9.6 11.0
INPUT NOISE CURRENT2 inp-p 0.1 Hz to10 Hz 14 30 pA p-p
2
INPUT NOISE CURRENT DENSITY in fO = 10 Hz 0.32 0.80 pA/√Hz
fO = 100 Hz 0.14 0.23
fO = 1000 Hz 0.12 0.17
INPUT RESISTANCE
Differential Mode3 RIN 26 45 MV
Common Mode RINCM 200 GV
INPUT VOLTAGE RANGE IVR ± 13 ± 14 V
COMMON-MODE
REJECTION RATIO CMRR VCM = ± 13 V 0.1 1.0 µV/V
POWER SUPPLY
REJECTION RATIO PSRR VS = ± 3 V to ± 18 V 0.7 3 µV/V
LARGE-SIGNAL
VOLTAGE GAIN AVO RL ≥ 2 kΩ ≥ VO = ± 10V 5000 12000 V/mV
OUTPUT VOLTAGE SWING VO RL ≥ 10 kΩ ± 13.5 ± 14.0 V
RL ≥ 2 kΩ ± 12.5 ± 13.0
RL ≥ 1 kΩ ± 12.0 ± 12.5
SLEW RATE2 SR RL ≥ 2 kΩ 0.1 0.3 V/µs
2
CLOSED-LOOP BANDWIDTH BW AVCL = +1 0.4 0.6 MHz
OPEN-LOOP OUTPUT RESISTANCE RO 60 Ω
POWER CONSUMPTION Pd VS = ± 15 V, No Load 50 60 mW
VS = ± 3 V, No Load 3.5 4.5
OFFSET ADJUSTMENT RANGE RP = 20 kΩ ±3 mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V OS during the first 30 operating days are typically 2.5 µV.
2
Sample tested.
3
Guaranteed by design.

–2– REV. B
 OP77
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = ⴞ15 V, –55ⴗC ≤ T ≤ 125ⴗC, unless otherwise noted.)
s A

OP77A
Parameter Symbol Conditions Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 25 60 µV
AVERAGE INPUT OFFSET
VOLTAGE DRIFT1 TCVOS 0.1 0.3 µV/°C
INPUT OFFSET CURRENT IOS 0.5 2.2 nA
AVERAGE INPUT OFFSET
CURRENT DRIFT2 TCIOS 1.5 25 pA/°C
INPUT BIAS CURRENT IB –0.2 2.4 4 nA
AVERAGE INPUT BIAS
CURRENT DRIFT2 TCIB 8 25 pA/°C
INPUT VOLTAGE RANGE IVR ± 13 ± 13.5 0.6 V
COMMON-MODE
REJECTION RATIO CMRR VCM = ± 13 V 0.1 1.0 µV/V
POWER SUPPLY
REJECTION RATIO PSRR VS = ± 3 V to ± 18 V 1 3 µV/V
LARGE-SIGNAL
VOLTAGE GAIN AVO RL ≥ 2 kΩ ≥ VO = ± 10 V 2000 6000 V/mV
OUTPUT VOLTAGE SWING VO RL ≥ 10 kΩ ± 12 ± 13.0 V
POWER CONSUMPTION Pd VS = ± 15 V, No Load 60 75 mW
NOTES
1
OP77A: TCVCS is 100% tested.
2
Guaranteed by design.

REV. B –3–
OP77–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, T = 125ⴗC, unless otherwise noted.)
s A

OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 25 20 60 µV
LONG-TERM
STABILITY1 VOS/Time 0.3 0.4 µV/Mo
INPUT OFFSET CURRENT IOS 0.3 1.5 0.3 2.8 nA
INPUT BIAS CURRENT IB –0.2 1.2 2.0 –0.2 1.2 2.8 nA
INPUT NOISE VOLTAGE2 enp-p 0.1 Hz to 10 Hz 0.35 0.6 0.38 0.65 µVp-p
INPUT NOISE
VOLTAGE DENSITY en fO = 10 Hz 10.3 18.0 10.5 20.0 nV/X/i
fO = 100 Hz2 10.0 13.0 10.2 13.5
fO = 1000 Hz 9.6 11.0 9.8 11.5
INPUT NOISE CURRENT2 inp-p 0.1 Hz to 10 Hz 14 30 15 35 pAp-p
INPUT NOISE
CURRENT DENSITY in fO = 10 Hz 0.32 0.80 0.35 0.90 pA√Hz
fO = 100 Hz2 0.14 0.23 0.15 0.27
fO = 1000 Hz 0.12 0.17 0.13 0.18
INPUT RESISTANCE
Differential Mode3 RIN 26 45 18.5 45 M⍀
Common Mode RINCM 200 200 G⍀
INPUT RESISTANCE
Common Mode RINCM 200 200 G⍀
INPUT VOLTAGE RANGE IVR ⫾13 ⫾14 ⫾13 ⫾14 V
COMMON-MODE
REJECTION RATIO CMRR VCM = ⫾13 V 0.1 1.0 0.1 1.6 µV/V
POWER SUPPLY
REJECTION RATIO PSRR VS = 3 V to 18 V 0.7 3.0 0.7 3.0 µV/V
LARGE-SIGNAL
VOLTAGE GAIN AVO RL ≥ 2 k⍀ 5000 12000 2000 6000 V/mV
OUTPUT VOLTAGE
SWING VO RL ≥ 10 k⍀ ⫾13.5 ⫾14.0 ⫾13.5 ⫾14.0 V
RL ≥ 2 k⍀ ⫾12.5 ⫾13.0 ⫾12.5 ⫾13.0
RL ≥ 1 k⍀ ⫾12.0 ⫾12.5 ⫾12.0 ⫾12.5
SLEW RATE2 SR RL ≥ 2 k⍀ 0.1 0.3 0.1 0.3 V/µs
CLOSED-LOOP
BANDWIDTH2 BW AVCL 1 0.4 0.6 0.4 0.6 MHz
OPEN-LOOP OUTPUT
RESISTANCE RO 60 60 ⍀
POWER CONSUMPTION Pd VS = ⫾15 V, No Load 50 60 50 60
VS = ⫾3 V, No Load 3.5 4.5 3.5 4.5 mW
OFFSET ADJUSTMENT
RANGE Rp = 20 kn ⫾3 ⫾3 mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V OS during the first 30 operating days are typically 2.5 µV.
2
Sample tested.
3
Guaranteed by design.

–4– REV. B
 OP77
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, –25ⴗC ≤ T ≤ +85ⴗC for OP77E/FJ and OP77E/FZ, unless otherwise noted.)
s A

OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE V J. Z Packages 10 45 20 100 µV
10 55 20 100
AVERAGE INPUT OFFSET TVCOS J. Z Packages 0.1 0.3 0.2 0.6 µV/°C
VOLTAGE DRIFT1 03 0.6 0.4 1.0
INPUT OFFSET CURRENT IOS 0.5 2.2 0.5 4.5 nA
AVERAGE INPUT OFFSET
CURRENT DRIFT2 TCIOS 1.5 4.0 1.5 85 pA/⬚C
INPUT BIAS CURRENT IB E, F -0.2 2.4 4.0 -0.2 2.4 6.0 nA
AVERAGE INPUT BIAS
CURRENT DRIFT2 TCIB 8 40 15 60 pA/°C
INPUT VOLTAGE RANGE IVR ⫾13.0 ⫾13.5 ⫾13.0 ⫾13.5 V
COMMON-MODE
REJECTION RATIO CMRR VCM = ⫾13 V 0.1 1.0 0.1 3.0 pVlV
POWER SUPPLY
REJECTION RATIO PSRR VS = ⫾3 V to ⫾18 V 1.0 3.0 1.0 5.0 µV/V
LARGE-SIGNAL
VOLTAGE GAIN AVO RL ≥ 2 kΩ 2000 6000 1000 4000 V/mV
VO = ⫾10 V
OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ⫾12 ⫾13.0 ⫾12 ⫾13.0 V
POWER CONSUMPTION Pd VS = ⫾15 V, No Load 60 75 60 75 mW
NOTES
1
OP77E: TCVOS is 100% tested on J and Z packages.
2
Guaranteed by end-point limits.

REV. B –5–
OP77–SPECIFICATIONS
WAFER TEST LIMITS (@ V = ⴞ15 V, T = 25ⴗC, for OP77N devices, unless otherwise noted.)
s A

OP77N
Parameter Symbol Conditions Limit Unit
INPUT OFFSET VOLTAGE VOS 40 µV Max
INPUT OFFSET CURRENT IOS 2.0 nA Max
INPUT BIAS CURRENT IB ±2 nA Max
INPUT RESISTANCE
Differential Mode RIN 26 MΩ Min
INPUT VOLTAGE RANGE IVR ± 13 V Min
COMMON-MODE REJECTION RATIO CMRR VCM = ± 13 V 1 µV/V Max
POWER SUPPLY REJECTION RATIO PSRR VS = ± 3 V to ± 18 V 3 µV/VMax
OUTPUT VOLTAGE SWING VO RL = 10 kΩ ± 13.5 V Min
RL = 2 kΩ ± 12.5
RL = 1 kΩ ± 12.0
LARGE-SIGNAL VOLTAGE GAIN AVO RL = 2 kΩ 2000 V/mV Min
VO = ± 10 V
DIFFERENTIAL INPUT VOLTAGE ± 30 V Max
POWER CONSUMPTION Pd VOUT = 0 V 60 mW Max
NOTES
1
Guaranteed by design.
2
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, T = 25ⴗC, unless otherwise noted.) s A

OP77N
Parameter Symbol Conditions Limit Unit
AVERAGE INPUT OFFSET VOLTAGE DRIFT TCVOS RS = 50 Ω 0.1 µV/OC
NULLED INPUT OFFSET VOLTAGE DRIFT TCVOSn RS = 50 Ω, RP = 20 kΩ 0.1 µV/°C
AVERAGE INPUT OFFSET CURRENT DRIFT TCIOS 0.5 pA/°C
SLEW RATE SR RL ≥ 2 kΩ 0.3 V/µs
BANDWIDTH BW AVCL + 1 0.6 MHz

–6– REV. B
 OP77
ABSOLUTE MAXIMUM RATINGS 1 BONDING DIAGRAM
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V 1. BALANCE
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V 2. INVERTING INPUT
3. NONINVERTING INPUT
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . Indefinite 4. V-
Storage Temperature Range 6. OUTPUT
7. V+
J and Z Packages . . . . . . . . . . . . . . . . . . . . –65°C to +150°C 8. BALANCE
Operating Temperature Range
OP77A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP77E, OPP77F (J, Z) . . . . . . . . . . . . . . . . –25°C to +85°C
Junction Temperature (Tj) . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec.) . . . . . . . . . . . . . 300°C
NOTES
1 DIE SIZE 0.093 ⴛ 0.057 inch, 5301 sq. mm
Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted. (2.36 ⴛ 1.45 mm, 3.42 sq. mm)
2
For supply voltages less than ± 22 V, the absolute maximum input voltage is
equal to the supply voltage. ORDERING GUIDE

Package Options Operating

Package Type ␪jAⴱ ␪jC Unit CERDIP* Temperature
TO-99 (J) 150 18 °C/W TO-99 8-Lead Range
8-Lead Hermetic DIP (Z) 148 16 °C/W
OP77AZ MIL
NOTE OP77EJ OP77EZ IND
ⴱ
␪jA is specified for worst-case mounting conditions, i.e., ␪jA is specified for
OP77FJ OP77FZ IND
device in socket for TO, CERDIP, P-DIP, and PLCC packages; ␪jA is specified
for device soldered to printed circuit board for SO package. ⴱ
Not for new designs; obsolete April 2002.

For Military processed devices, please refer to the Standard

Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp

SMD Part Number ADI Equivalent

5962-87738012A OP77BRCMDA
5962-8773802GA OP77AJMDA
5962-8773802PA OP77AZMDA

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the OP77 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

REV. B –7–
OP77-Typical Performance Characteristics
2 25 16

VS = ⴞ15V VS = ⴞ15V
TA = 25ⴗC
TA = 25ⴗC
(NULLED TO 0␮ @VOUT = 0V)

20 RL = 2k⍀

OPEN-LOOP GAIN – V/␮V

OPEN-LOOP GAIN – V/␮V
1 RL = 10k⍀ 12
INPUT VOLTAGE – ␮V

15
0 8

10

–1 4
5

–2 0 0
–10 –5 0 5 10 –55 –35 –15 5 25 45 65 85 105 125 0 ⴞ5 ⴞ10 ⴞ15 ⴞ20
OUTPUT VOLTAGE – V TEMPERATURE – ⴗC POWER SUPPLY VOLTAGE – V

TPC 1. Gain Linearity (Input TPC 2. Open-Loop Gain vs. TPC 3. Open-Loop Gain vs.
Voltage vs. Output Voltage) Temperature Power Supply Voltage

30 4 30
CHANGE IN INPUT OFFSET VOLTAGE – ␮V

J, Z PACKAGES
VS = ⴞ15V VS = ⴞ15V

ABSOLUTE CHANGE IN INPUT OFFSET

+0.3␮V/ⴗC
CHANGE IN OFFSET VOLTAGE – ␮V

3
20 TA = 25ⴗC 25
DEVICE IMMERSED IN
MEAN 2 70ⴗC OIL BATH (20 UNITS)
S.D.
10 20

VOLTAGE – ␮V
1

0 0 15

–1
–10 10 MAX
–2
–20 5 AVE
–0.3␮V/ⴗC –3
MIN

–30 –4 0
–55 –35 –15 5 25 45 65 85 105 125 0 0.5 1 1.5 2 2.5 3 3.5 0 10 20 30 40 50 60 70
TEMPERATURE – ⴗC TIME AFTER POWER SUPPLY TURN-ON – MINUTES TIME – SEC

TPC 4. Untrimmed Offset TPC 5. Warm-Up Drift TPC 6. Offset Voltage Change
Voltage vs. Temperature Due to Thermal Shock

100 160 0 150

VS = ⴞ15V
VS = ⴞ15V TA = 25ⴗC
140 TA = 25ⴗC 140
80 TA = 25ⴗC
CLOSED-LOOP GAIN – dB

120 45
OPEN-LOOP GAIN – dB

130
60
100
CMMR –dB

120
40 80 90
110
60
20
100
40 135
0
20 90

–20 0 180 80
10 100 1k 10k 10k 1M 10M 0.01 0.1 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

TPC 7. Closed-Loop Response for TPC 8. Open-Loop Gain/Phase TPC 9. CMRR vs. Frequency
Various Gain Configurations Response

–8– REV. B
 OP77
130 4 2.0
VS = ⴞ15V VS = ⴞ15V
TA = 25ⴗC
120

INPUT OFFSET CURRENT – nA

INPUT BIAS CURRENT – nA
3 1.5
110
PSRR – dB

100
2 1.0
90

80
1 0.5

70

60 0 0
0.1 1.0 10 100 1k 10k –50 0 50 100 –50 0 50 100
FREQUENCY – Hz TEMPERATURE – ⴗC TEMPERATURE – ⴗC

TPC 10. PSRR vs. Frequency TPC 11. Input Bias Current TPC 12. Input Offset Current
vs. Temperature vs. Temperature

10 1000 32
RS1 = RS2 = 200kV
VS = ⴞ15V
THERMAL NOISE OF SOURCE VS = ⴞ15V
28
INPUT NOISE VOLTAGE – nV/ Hz

TA = 25ⴗC

PEAK-TO-PEAK AMPLITUDE – V
RESISTORS INCLUDED TA = 25ⴗC
EXCLUDED 24
RMS NOISE – mV

100
20

1.0 16

RS = 0
12
10
8

VS = ⴞ15V 4
TA = 25ⴗC
0.1 1 0
100 1k 10k 100k 1 10 100 1k 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

TPC 13. Input Wideband Noise vs. TPC 14. Total Input Noise TPC 15. Maximum Output Swing
Bandwidth (0.1 Hz to Frequency Voltage vs. Frequency vs. Frequency
Indicated)

100 20 40
OUTPUT SHORT-CIRCUIT CURRENT – mA

TA = 25ⴗC VS = ⴞ15V
VS = ⴞ15V
TA = 25ⴗC
TA = 25ⴗC
POWER CONSUMPTION – mW

VIN = ⴞ10mV 35
MAXIUM OUTPUT – VOLTS

15 POSITIVE SWING

NEGATIVE SWING 30
10 10

25

5
20

0 0 15
0 10 20 30 40 100 1k 10k 0 1 2 3 4
TOTAL SUPPLY VOLTAGE, V+ TO V – V LOAD RESISTANCE TO GROUND – ⍀ TIME FROM OUTPUT BEING SHORTED –
MINUTES

TPC 16. Power Consumption vs. TPC 17. Maximum Output Voltage TPC 18. Output Short-Circuit
Power Supply vs. Load Resistance Current vs. Time

REV. B –9–
OP77
200k⍀

TYPICAL
50⍀
PRECISION OP AMP
10k⍀ 100k⍀
OP77 VO
VY
1M⍀
VO
VOS = VIN = 10V VX
4000 VX
–10V 0V +10V
Figure 1. Typical Offset Voltage Test Circuit 10⍀
RL

2.5M⍀
AVO ~ 650V/mV
V+ RL = 2k⍀
NOTES
100⍀ 2 7 3.3k⍀ 1. GAIN NOT CONSTANT. CAUSES NONLINEAR ERRORS.
6
100⍀ OP77 OUTPUT 2. AVO SPEC IS ONLY PART OF THE SOLUTION.
3
4 4.7␮F 3. CHECK THE OP AMP PERFORMANCE, ESPECIALLY AT TEMPERATURES.
V– ( 10Hz FILTER)

VO Figure 5. Open-Loop Gain Linearity

INPUT REFERRED NOISE =
25,000

Actual open-loop voltage gain can vary greatly at various output

Figure 2. Optional Offset Nulling Circuit
voltages. All automated testers use endpoint testing and therefore
20k⍀
only show the average gain. This causes errors in high closed-
V+ loop gain circuits. Since this is so difficult for manufacturers to
– 1 test, users should make their own evaluation. This simple test
2 8
7 6
INPUT +
3
OP77 OUTPUT circuit makes it easy. An ideal op amp would show a horizontal
4 scope trace.
V–

Figure 3. Typical Low-Frequency Noise Test Circuit VY

100k⍀
+18V

+
* 10␮F 10⍀
–10V 0V +10V
0.1␮F VX
2 7

3
OP77
6
4
10k⍀ 10k⍀

10⍀ 0.1␮F
AVO ~ 650V/mV
10␮F * + RL = 2k⍀
–18V
* 1 PER BOARD

Figure 4. Burn-In Circuit

Figure 6. Output Gain Linearity Trace

This is the output gain linearity trace for the new OP77. The
output trace is virtually horizontal at all points, assuring extremely
high gain accuracy. The average open-loop gain is truly impres-
sive—approximately 10,000,000.

–10– REV. B
 OP77
APPLICATIONS INFORMATION Bilateral Current Source

R3
R2
1k⍀
1M⍀
+15V

0.1␮F R1 2
VIN
100k⍀ 6
OP77 IOUT < 15mA
R2 3
R1 2 7 100k⍀
1k⍀ 6 R5
OP77E 10⍀
R3 3
1k⍀ 4 R4
0.1␮F 990⍀

R4 Figure 9. Basic Current Source

1M⍀

–15V
R3

+15V

Figure 7. Precision High-Gain Differential Amplifier

R1 2 2N2222
VIN
6
The high gain, gain linearity, CMRR, and low TCVos of the R2
OP77
3
OP77 make it possible to obtain performance not previously 2N2907
available in single-stage very high-gain amplifier applications. R5

R4 –15V
R1 R3 IOUT < 100mA
For best CMR, must equal . In this example,
R2 R4 IOUT = VIN = ( R1R3– R5)
GIVEN R3 = R4 ⴙ R5, R1 = R2
with a 10 mV differential signal, the maximum errors are as listed
in Table I. Figure 10. 100 mA Current Source

Table I. Maximum Errors These current sources will supply both positive and negative
current into a grounded load.
TYPE AMOUNT
 R4 
COMMON-MODE VOLTAGE 0.01%/V R5  + 1
 R2 
GAIN LINEARITY, WORST CASE 0.02% Note that ZO =
R5 + R 4 R3
TCVOS 0.003%/°C
TCI OS 0.008%/°C R2 R1
and that for ZO to be infinite,

RF

10pF

+15V
0.1␮F

RS
2 7
INPUT
6 100⍀
OP77 OUTPUT
3
4
0.1␮F CLOAD

–15V

Figure 8. Isolating Large Capacitive Loads

This circuit reduces maximum slew-rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output imped-
ance is reduced to insignificance by the high open-loop gain
of the OP77.

REV. B –11–
OP77
R5 + R 4 R3 In these circuits, OP77’s high gain, high CMRR, and low TCVOS
must = ensure high accuracy.
R2 R1
Precision Current Sinks R1

1.8k⍀
V+ 2mA

15V
RL
3 7
IO VIN
IO = 6
R1 OP77 EO = 10V
VIN 2
200⍀ VIN > OV
4 R2
OP77 IRF520 FULL SCALE OF 1V, 1N4579A D1 3.6k⍀
6.4V ⴞ5%
IO = 1A/V
ⴞ5ppm/ⴗC AVCL 1.6

R3
R1 6.4k⍀
1⍀
1W

Figure 13. High Stability Voltage Reference

Figure 11. Positive Current Sink
This simple bootstrapped voltage reference provides a precise 10 V
R1
virtually independent of changes in power supply voltage, ambi-
ent temperature and output loading. Correct Zener operating
current of exactly 2 mA is maintained by R1, a selected 5 ppm/°C
resistor, connected to the regulated output. Accuracy is prima-
200⍀ rily determined by three factors: the 5 ppm/°C temperature
OP77 IRF520
coefficient of D1, 1 ppm/°C ratio tracking of R2 and R3, and
VIN
IO VIN operational amplifier VOS errors.
IO =
R1 VOs errors, amplified by 1.6 (AVCL), appear at the output and
RL VIN > OV can be significant with most monolithic amplifiers. For example,
an ordinary amplifier with TCVOS of 5 µV/°C contributes 0.8 ppm/
V– °C of output error while the OP77, with TCVOS of 0.3 µV/°C,
contributes but 0.05 ppm/°C of output error, thus effectively
Figure 12. Positive Current Source eliminating TCVOS as an error consideration.
The high gain and low TCVOS assure accurate operation with
These simple high-current sinks require the load to float between
inputs from microvolts to volts. In this circuit, the signal always
the power supply and the sink.

1k⍀ 1k⍀

+15V
+15V
D1 0.1␮F
C1
0.1␮F 30pF 1N4148
2 7
2 7 6 VOUT
D2 OP77E
6 3 0 < VOUT < 10V
OP77E 4
3 2N4393
VIN 0.1␮F
4
R3
0.1␮F
2k⍀

–15V
–15V

Figure 14. Precision Absolute Value Amplifier

The high gain and low TCVOS assure accurate operation with appears as a common-mode signal to the op amps. The OP77E
inputs from microvolts to volts. In this circuit, the signal always CMRR of 1 ␮V/V assures errors of less than 2 ppm.

–12– REV. B
 OP77

15V
+
10␮F 2 2 2

REF-01 REF-01 REF-01

VO 6 VO 6 VO 6
OP77 VOUT
4 4 4 100⍀

100⍀

100⍀

0.1␮F

Figure 15. Low Noise Precision Reference

This circuit relies upon OP77’s low TCVOS and noise combined CH must be of polystyrene, Teflon*, or polyethylene to minimize
with very high CMRR to provide precision buffering of the dielectric absorption and leakage. The droop rate is determined
averaged REF01 voltage outputs. by the size of CH and the bias current of the AD820.
*Teflon is a registered trademark of the Dupont Company

1k⍀

15V
0.1␮F 1N4148 15V
0.1␮F
2 7
6
3 OP77
1k⍀ 2N930 2 7
VIN 6 VOUT
4 AD820
0.1␮F 1k⍀ 3
4 0.1␮F
CH

–15V
RESET –15V

Figure 16. Precision Positive Peak Detector

REV. B –13–
OP77
+15V
CC
0.1␮F
RF

100k⍀ 2
+15V
VIN RA RC
6
0.1␮F VO

TRIM 5 50k⍀
RS 2 7 D1
VTH REF-02
1k⍀ 1N4148
6
OP77 VOUT Rb1 OP77 VOUT
3 1.5k⍀
R1 3
VIN TEMP
4 0.1␮F
2k⍀ GND
0.1␮F
4 Rbp

–15V
–15V

Figure 17. Precision Threshold Detector/Amplifier Figure 18. Precision Temperature Sensor

Table II. Resistor Values

When VIN < VTH, amplifier output swings negative, reverse
biasing diode D1. VOUT = VTH if RL= ∞ when VIN > VTH, the TCVOUT SLOPE (S) 10 mV/°C 100 mV/°C 10 mV/°F
loop closes,
TEMPERATURE –55°C to –55°C to –67°F to
 R  RANGE +125°C +125°C +257°C
VOUT = VTH + (VIN – VTH ) 1 + F 
 RS  OUTPUT VOLTAGE –0.55 V to –5.5 V to –0.67 V to
CC is selected to smooth the response of the loop. RANGE +1.25 V +12.5V +2.57V
ZERO-SCALE 0 V @ 0°C 0 V @ 0°C 0 V @ 0⬚F
Ra (± 1% Resistor) 9.09 kΩ 15 kΩ 7.5 kΩ
Rb1 (± 1% Resistor) 1.5 kΩ 1.82 kΩ 1.21 kΩ
Rbp (Potentiometer) 200 Ω 500 Ω 200 Ω
Rc (± 1% Resistor) 5.11 kΩ 84.5 kΩ 8.25 kΩ

–14– REV. B
 OP77
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP 8-Lead Hermetic

(N-8) (Q-8)

0.005 (0.13) 0.055 (1.4)

0.430 (10.92) MIN MAX
0.348 (8.84)
8 5
8 5
0.280 (7.11) 0.310 (7.87)
0.240 (6.10) PIN 1 0.220 (5.59)
1 4 1 4

PIN 1 0.325 (8.25)

0.100 (2.54)
0.100 (2.54) 0.300 (7.62) BSC
BSC 0.405 (10.29) MAX 0.320 (8.13)
0.060 (1.52) 0.290 (7.37)
0.210 0.015 (0.38) 0.195 (4.95) 0.060 (1.52)
(5.33) 0.115 (2.93) 0.200 (5.08) 0.015 (0.38)
MAX MAX
0.130
0.160 (4.06) (3.30) 0.150
MIN 0.200 (5.08) (3.81)
0.115 (2.93)
0.015 (0.381) 0.125 (3.18) MIN
0.022 (0.558) 0.070 (1.77) SEATING 0.015 (0.38)
0.008 (0.204) SEATING
0.014 (0.356) 0.045 (1.15) PLANE 0.023 (0.58) 0.070 (1.78) PLANE 15 0.008 (0.20)
0.014 (0.36) 0.030 (0.76) 0

8-Lead PLCC 8-Lead Header Package

(P-20A) (H-8)

0.180 (4.57) REFERENCE PLANE

0.048 (1.21) 0.165 (4.19) 0.750 (19.05)
0.042 (1.07) 0.056 (1.42) 0.500 (12.70)
0.025 (0.63) 0.185 (4.70)
0.042 (1.07) 0.250 (6.35) MIN 0.100 (2.54) BSC
0.015 (0.38) 0.165 (4.19)
0.048 (1.21)
3 19 0.050 (1.27) MAX 0.160 (4.06)
0.042 (1.07) 0.021 (0.53)
4 PIN 1 18
0.013 (0.33) 0.110 (2.79)
IDENTIFIER 0.050 5
(1.27) 0.330 (8.38)
TOP VIEW 0.032 (0.81) 0.290 (7.37) 4 6
0.370 (9.40)
0.335 (8.51)
0.335 (8.51)
0.305 (7.75)

(PINS DOWN) BSC 0.045 (1.14)

0.026 (0.66) 0.200
8 14 0.027 (0.69)
(5.08) 3 7
0.020 9 13
BSC
(0.50) 0.040 (1.01) 2
0.356 (9.04) 8
R 0.025 (0.64)
0.350 (8.89) SQ 1
0.110 (2.79) 0.019 (0.48) 0.100
0.395 (10.02) (2.54)
SQ 0.085 (2.16) 0.016 (0.41)
0.385 (9.78) BSC 0.034 (0.86)
0.040 (1.02) MAX
0.021 (0.53) 0.027 (0.69)
0.045 (1.14) 0.016 (0.41)
0.010 (0.25) 45 BSC
BASE & SEATING PLANE

Revision History
Location Page
Data Sheet changed from REV. A to REV. B.
Remove 8-Lead SO PIN CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Remove OP77G column from WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Remove OP77G column from TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

REV. B –15–
–16–
PRINTED IN U.S.A. C00320–0–2/02(A)
 Analog Devices: OP77: Product Page: Package/Price Information

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Description
For detailed packaging information, please select the Data Sheets button.
Data Sheets
* The pricing listed here is provided only for budgetary purposes as recommended list price in U.S. Dollars
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Design Tools
Packages
Package Pin Temperature Price*
Model Status
Package/Price Information Description Count Range (1000-4999)
Purchase 5962-87738012A Production 20 ld LCC 20 MILITARY $42.03

All Design Resources 5962-8773802GA Production 8 ld Header 8 MILITARY $17.29

5962-8773802PA Production 8 ld CerDIP 8 MILITARY $16.15

Select a resource...
OP77AJ Obsolete 8 ld Header 8 MILITARY -

OP77AJ/883C Obsolete 8 ld Header 8 MILITARY -

OP77AZ Obsolete 8 ld CerDIP 8 MILITARY -

OP77AZ/883C Obsolete 8 ld CerDIP 8 MILITARY -

OP77BJ Obsolete 8 ld Header 8 MILITARY -

OP77BRC/883C Obsolete 8 ld PDIP 20 MILITARY -

OP77EJ Production 8 ld Header 8 INDUSTRIAL $7.60

OP77EP Obsolete 8 ld PDIP 8 INDUSTRIAL -

OP77EZ Production 8 ld CerDIP 8 INDUSTRIAL $5.10

OP77FJ Production 8 ld Header 8 INDUSTRIAL $4.79

OP77FP Obsolete 8 ld PDIP 8 INDUSTRIAL -

OP77FZ Production 8 ld CerDIP 8 INDUSTRIAL $2.98

OP77GBC Obsolete CHIPS OR DIE - TBD -

OP77GP Obsolete 8 ld PDIP 8 INDUSTRIAL -

OP77GS Obsolete 8 ld SOIC 8 INDUSTRIAL -

OP77GS-REEL Obsolete 8 ld SOIC - TBD -

OP77GS-REEL7 Obsolete 8 ld SOIC 8 TBD -

OP77HS Obsolete 8 ld SOIC 8 COMMERCIAL -

OP77HS-REEL Obsolete 8 ld SOIC 8 TBD -

OP77HS-REEL7 Obsolete 8 ld SOIC 8 TBD -

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OP77NBC Production CHIPS OR DIE - TBD $5.30

Pricing is not available for pre-release parts, please contact your local Sales Office or Authorized
Distributor for additional information.

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