University of Florida EEL 3701 Dr. Eric M.

Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 1/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
II. Designing
Tips
• Create a folder where you will store all of your Quartus A. Creating a BDF
projects. 1. If you have not already done so,
• Do NOT use spaces and special characters in Quartus create a new bdf by selecting the Figure 0: Button
file/project names. bdf button (see Figure 0) or by for new bdf
• Accept defaults when saving files. selecting “File”, “New”, “Block
• Use labels instead of crossing wires. Diagram/Schematic File”, and “OK”.
2. Remove the grid dots by selecting “View” and “Show
Example Problem Guidelines”.
3. Select “File” and “Save As”. Save your bdf as “lab1_ex”
Given the logic equation Y = A*/B + /C, implement this
in your lab1_ex” project director. If you used the directory
equation using a two input AND gate, a two input OR gate and
(folder name) that I suggested, then this should be the
two inverters under the Quartus environment. Upon completion
default name. The file will be given the bdf extension; bdf
of the schematic entry portion of the example, simulate the
stands for “block design file” and contains schematics,
circuit and print out copies of the circuit & simulation results.
symbols or block diagrams.
Draw a Logic Table and Voltage Table (in counting order)
for the inputs & output and you will later compare it with the B. Adding Text
simulation results. Assume A, B, C, and Y are active high 1. Select the “A” in the toolbar of your bdf window.
signals so your voltage table will look identical to your truth 2. Select a point near the top left in the window with the left
table but instead of 0’s there will be L’s and instead of 1’s there mouse key. Type your “Name:” followed by your first and
will be H’s. last name, and then hit the “Enter” key.
3. Type “Lab # Part #”, where # is replaced by that week’s
I. Creating a Project in Quartus lab number and the lab part number respectively and then
A. New Project Design Creation hit the “Enter” key.
1. Setup a local ‘lab1_ex’ directory on your PC to hold your 4. Type your “Section Number: ####” and then hit the
design & simulation files. “Enter” key.
2. Launch the Altera Quartus software under Windows. 5. Type “TA Name:”, followed by your TA’s first and last
3. Open the New Project Wizard by selecting the New Project name. Hit the “Enter” key.
Wizard icon or by selecting “File” and “New Project 6. Type “Description:” followed by an appropriate
Wizard ...”. Select “Next” (feel free to check the “Don’t description. In this case type the following equation, “Y =
show me this introduction again” box). A * /B + /C,” and then hit the “Enter” key. See Figure 1 for
4. Under “What is the working directory for this project”, use a sample of header for this course.
the “…” button to browse and select the directory you
created in step number 1.
5. Under “What is the name of this project”, name the project
lab1_ex. (This may already be done for you. This should
also make the top-level design entity name lab1_ex. If not,
again type in lab1_ex.) Select “Next”, “Next”, “Next”.
(Note that dashes should NOT be used in file names. The
simulator has a problem with dashes.)
6. Change the “Family” under “Device family” to MAX V. Figure 1: Sample bdf heading
Under Available Devices select “5M570ZT100C5”. Select
“Next”. 7. Hit the “Esc” (escape) key to end text additions.
7. In “EDA Tool Setting”, for “Simulation” chose 8. If your text is getting clipped off/cut off, this may be due
“ModelSim-Altera” and for “Format(s)” chose “VHDL”. to a resolution issue. This following link has instructions
8. Select “Next” and then “Finish”. on resolving this issues: Quartus Display Issues. If there is
9. Select the pull-down button “File” and “New | Device still a problem with parts being hidden in part of the screen,
Design Files | Block Diagram/Schematic File”. Press OK. just detach the design (bdf) file by selecting the “Window”
This should open a palette (called a bdf) where you will tab and then “Detach Window”.
design your circuit. C. Component Selection Process and Moving Components
B. Configuring Quartus Window 1. With your mouse pointing inside the bdf, double-click (or
1. Select “View” and “Utility Windows”. Make sure click the right mouse key and select “Insert” then
“Project Navigator”, “Messages”, and “Tasks” are “Symbol”). The “Symbol” dialog box will appear. This
selected. You do not need the “IP Catalog”. window lists the available Altera libraries.
2. Select “Tools” and “Customize.” Make sure “File”, 2. Select the > icon to expand the
“Standard” and “Applications” are selected. “/intelfpga_lite/17.1/quartus/libraries” folder.
University of Florida EEL 3701 Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 2/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
3. Select the > icon to expand the “primitives” folder and then 2. Place your pointer on the output of one of the Level-
expand the “logic” folder. Shifters and hold the left mouse button down. You should
4. Similarly example the “logic” folder and then select the see a cross-hairs or “+” appear at the output.
“and2” component by double clicking on it (or by selecting 3. Drag your pointer to the input of the AND gate. Every time
it with a single click, then selecting “OK”). you release the mouse key, the line (wire) ends. If your
5. Hit the left mouse key when the pointer is at the desired wire did not reach the AND gate, you can add to the wire
location in the bdf to insert the AND symbol into the design by putting your mouse over an end of the wire and again
file. selecting it with your left mouse button and dragging your
6. Double-click in the bdf window. Insert an “OR2” gate by mouse to another position.
typing or2 into the box under “Name:”. Hit the keyboard 4. To delete a wire or a portion of a wire, simply right click
“Enter” key or press “OK”. on the wire and select “Delete” or left click on the wire (it
7. Place the OR symbol into the bdf. should change color to indicate selection) and press the
8. Repeat step 6 to place two Level-Shifter (NOT) gates. This delete key.
time type not into the box and click on the box next to 5. If wires are connected to the component as you are moving
“Repeat-insert mode”. it, the wires will drag and stay connected to the component.
9. Click the pointer at the desired location in the bdf to insert This is referred to as “rubber banding” and is a feature of
the first NOT symbol into the design file. Now click on all major schematic entry design packages.
another desired location in the bdf to insert a second NOT 6. Add the rest of the wires needed to connect the logic
symbol. diagram. Add small input lines where the three inputs will
10. Hit the “Esc” (escape) key to end Repeat-insert mode. be placed and an output line where the output will be
11. Select the magnifying glass in the toolbar of your bdf placed. Your bdf should look similar to Figure 3.
window. Select a point in the window with the left mouse
button. Notice that the image gets larger with the center of
the enlargement at the point you selected. Now select a
point in the window with the right mouse button. Notice
that the image gets smaller with the center of the
enlargement at the point you selected.
12. Hit the “Esc” (escape) key to end magnifying options or
select the pointer symbol to return to selection mode.
13. Rearrange your devices in approximately the placement
you would like for the logic diagram you are trying to
construct. You can move a component by selecting it with
your mouse, and either holding down the left mouse button
and moving it to another location on your bdf or using your
up/down/left/right arrow keys. The window should look Figure 3: Bdf with wires
similar to Figure 2.
E. Adding Input & Output Ports
1. In the same manner that you placed a gate onto the bdf, add
three input pins from the “Symbol” libraries. Input pins
can be found under “primitives | pin | inputs” (or just type
input just as you typed not previously in the “Name:”
box). I suggest placing these inputs together, above your
logic diagram and just to the right of your name as shown
in Figure 4.
2. Double click on the first input pin name (on the left of the
input port symbol) and change it to ‘A’. Repeat these two
steps to create input ports ‘B’ & ‘C’.
Figure 2: Bdf with logic symbols

D. Adding/Deleting Wires
1. Save your design. You are now ready “wire up” your
circuit. It is a good idea to save your design often, just in
case something bad happens (like a Windows crash or a
power outage).
University of Florida EEL 3701 Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 3/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
3. In the same manner and in the same library that you found different number of warnings. You can ignore most
the input pins, add an output pin from the “Symbol” library. warnings. If you did something wrong, Quartus will not
I put this output pin under and to the right of the input pins. compile and will give you an error.
Change the pin name to ‘Y’ on the output port, as shown in
Note: Several common errors involve having floating
Figure 4.
(unconnected) inputs and outputs or short circuits (possible
locations where two inputs or two outputs are connected).
Another error is when the top-level entity undefined; if this
occurs click on “Files” on the Project Navigator utility window,
right click your bdf (in this case lab1_ex.bdf), and select “Set
as Top-Level Entity”).
Note: When using Quartus schematic entry (bdf) files as your
circuit diagram for constructing circuits on your breadboard,
always label the parts and pin numbers of the chip. If there are
multiples of the same part needed, e.g., if you need five 2-input
AND gates when the 74’08 only has four per chip, then label
the two 74’08’s differently, i.e., 08A and 08B. Each AND gate
on a single 74’08 can be labelled 08-1, 08-2, 08-3, and 08-4.
Figure 4: Bdf with inputs and outputs
G. Functional Compiling
To functionally compile your design takes significantly less
4. Now select the top wire near the left most point where you
time than the full compilation described above. When I just
would like to connect signal A. The wire should change
colors. Type “A.” An “A” should appear near the point tried it for this circuit, it took 12 seconds, whereas the full
you selected. compilation took 28 seconds.
1. To functionally compile your design, double click the
5. Do the same to place “B”, “C” and “Y” at the appropriate
“Analysis & Synthesis” in the Compilation window shown
points.
in Figure 6.
6. The “A” label will connect the input labeled “A” to this
2. Not that if perform a Functional Compiling, when you
wire. Similar connections are made by the labels on the
other inputs and output. The bdf should look similar to simulate, you can ONLY run a Functional Simulation.
Figure 4.
7. Save your design. You are now ready to proceed to
compile and simulate the circuit.
F. Compiling
1. See “Functional Compiling” below.
2. To compile your design, click on the blue isosceles triangle
button or double click on “Compile Design” in the task
utility window or select “Processing” and then “Start
Compilation”. Your task utility window should be similar
to the image in Figure 5.

Figure 6: Functional Compile

III. Simulating
A. Creating a VWF (Vector Waveform)
1. Select “File” and “New”. Under “Verification/Debugging
Files” select “University Program VWF”.
2. Save this file under the suggested (default) name,
“Waveform.vwf” by selecting “File | Save”.
Figure 5: Compile Complete
B. Adding signals
3. Notice that the Messages Utility Bar on the bottom of the 1. In the Waveform.vwf window, in the left side of the
Quartus window says “Quartus Prime Full Compilation window (under “Name”) double click with the left mouse
was successful. 0 errors, 13 warnings”. You may have a button or click the right mouse button. The “Insert Node
University of Florida EEL 3701 Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 4/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
or Bus” window will appear. Select “Node Finder”. Under “1” button on the toolbar (or select “Edit”, ”Value”,
“Filter” select “Pins: all” then select “List.” Hit the >> “Forcing High (1)”) to set this time as High.
button to copy all the nodes (inputs and outputs) to the 3. Using the same methods in the previous step, set the time
“Selected Nodes” list on the right. Select “OK” and then period of 0 ns to 50 ns to Low by using the “0” button.
“OK”. Your vwf should look like Figure 8.
2. You should now see the inputs and outputs in the vector
Special Note: Your simulation will match your voltage table
waveform file window. Save this file. The window should
(not your truth table). When you compare the outputs, you
look like Figure 7.
should verify it with the outputs of your voltage table and not
Special Note: The time scale is shown above is in increments your truth table. When you see a 0, it is LOW. When you see
of 10 ns (ns = nano seconds). This is too small for our parts. a 1, it is HIGH. Please do not get this confused.
Our parts have a propagation delay of between 10 and 20 ns,
4. Manually manipulate your signals to match the image in
i.e., the output of the gates does not change until approximately
Figure 9. Save this simulation design.
10-20 ns after the inputs change.

Figure 7: Vwf with inputs and outputs

5. The inputs have now been defined and “count” or

C. Changing Grid Size and End Time increment through the binary numbers 000 to 111 (ABC
1. Change the default grid size to 25 ns (or more) by the where A is the most significant bit and C is the least
following. Go to the “Edit” menu and select “Grid Size”. significant bit). We can now run the design simulation at
Then change the Time period to 25.0 ns. this point. Note: The Y output is comprised of ‘XXX’ in
2. Go to the “Edit” menu and select “Set End Time”. Change the waveform editor to show that the output is presently
the default time from 1.0 us (1 µs = 1000 ns) to 1.2 us undefined.
(1200 ns). NOTE: When you increase the end time,
Quartus simulation will pick signal values to fill up the
total time. Be sure to review your inputs to verify that the
simulation is doing what you want. NOTE: To avoid
possible simulation issues, ALWAYS INCREASE END
TIME. You may give it a new end time once you simulate
at least once, but you should always increase the end time
initially.
D. Manually Changing VWF
1. Use the magnifying glass to zoom in on the waveform Figure 9: Vwf with manual inputs
window until you can see 50 ns intervals as seen in the
image below. Note: There are better ways to input data then to enter each of
2. Using your mouse (make sure the pointer is selected), click the values you want by changing default inputs. See Section F
and drag your mouse cursor across 0 ns to 100 ns on input E. Functional and Timing Simulation
A to select the area. You should see that area highlighted 1. Select “Simulation” in waveform window and “Run
blue (as seen from 0ns to 50 ns in Figure 8). Now press the Functional Simulation”. You’ll notice a Simulation Flow
Progress window pop up then a new simulation window
will open. It will look similar to your vwf except that it is
read only. You cannot modify signals on this window.
2. Zoom in on the window. You should see something similar
to Figure 10.
3. If you haven’t created a logic and voltage table for the
equation you entered under Quartus, do so now and
Figure 8: Vwf with A set to high from 50 ns to 100 ns compare these results with those obtained from simulation.
Because the signals are assumed to be active high, the truth
and voltage tables will look identical (with 0 and 1 replaced
University of Florida EEL 3701 Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 5/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
with L and H, respectively). Your simulation results from “Group.” Group A, B, and C and name them “Inputs”.
Quartus should match your voltage table. Select the radix (base you want to use, i.e., binary,
hexadecimal, or octal). In this case you should stick to the
default: binary. Press “Ok”.
2. Click on the arrow next to Inputs to expand your group.
You should see something similar to Figure 12.

Figure 10: Output of Functional Simulation

• For active-low signals, I suggest that you name your

signals with a suffix of _L. For active-high signals, I
suggest no suffix (or you could use _H). For example,
if X is active-low and Z was active-high, use signal Figure 12: Grouping on vwf
names X_L and Z. 3. Click “Inputs” and press the “0” button to make all the
• When submitting screenshots for lab documents, take inputs low.
a screenshot of this window with the simulated 4. Click “Inputs” and press the C button in the toolbar (or
output. Use a tool like snip tool or paint to annotate Select “Edit”, “Value”, “Count Value …”). This will allow
the simulation. Use arrows and text to describe what you to count up from a start value (in this case from 000 to
is occurring and demonstrate that you received the 111). Leave the default “Start value” at 000 and the default
proper results. “Increment by” at 1. At “Count occur”, change it to 50 ns.
4. Close the simulation window and select “Simulation” and Press Ok.
“Run Timing Simulation”. You’ll again notice a 5. Zoom out on the window. Notice that “Inputs”
Simulation Flow Progress window pop up and a new automatically counts for the entire simulation. Press Save.
simulation window will pop up. 6. Perform a functional and timing simulation.
5. Zoom in on the window. You should see something similar 7. You can also use Clock value to generate a clock signal.
to Figure 11. The button looks like a stopwatch. You will use this later
on in the semester. You can change the period, offset, and
duty cycle.
IV. Programming
A. Using the Out of the Box CPLD Programmer
View the instructions on how to use the Out of the Box CPLD
Programmer. This programmer replaces the alternative part
that costs anywhere from $50 to $300 (from Terasic or Altera,
respectively). Programming with this CPLD programmer is
Figure 11: Output of Timing Simulation slower than the other two Terasic and Altera devices, and it does
limit the types of devices that it can program.
6. When comparing the results of the logic table with that of
the simulator, it should be apparent that they match but that The OOTB CPLD Programmer instructions has a link to a
there is a small delay between when the inputs change and required FTDI driver for USB on Windows computers (or those
when the output changes to the expected value. For setup to have Windows virtual machines). A link is also
example, if we look at the time segment from 25 to 50 ns, provided for those who want to try to run this with other
we see that the inputs C change at 25 ns, but that Y does operating systems (including Linux). Download, unzip, and
not change immediately. This delay is called the then execute the file to install the driver. See our website and
propagation delay of the device. This slight delay is due to either the Software/Docs page or the Labs page for the driver.
the physical gate delay of the gates in the programmable
In addition, a DLL file is provided on our website and either the
logic device (PLD) required to implement the circuit. In
Software/Docs page or the Labs page. As the instructions tell
other words, every gate in your circuit has a chunk of PLD
you, this file must be copied and placed in the appropriate folder
hardware that is associated with it and an associated
on your computer.
physical delay.
F. Grouping Signals and Using Count Value and Clock Value
1. You can group inputs by selecting several and then click
the right mouse button, select “Grouping” and then select
University of Florida EEL 3701 Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 6/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
B. Assigning pins using Pin Planner
1. To make sure you do NOT accidently assign pins to the
wrong location, use only the pins shown Figures 13 and 14.

Available CPLD Pins

29
30
33
34
35
36
38
40
41
42
43
44
47
48
49
50
74
75
76
77
78
81
82
83
84
85
86
87
89
91
92
96
Figure 13: CPLD PCB top layer with available CPLD pins
Figure 14: Available CPLD pins
University of Florida EEL 3701 Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 7/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
2. To program a device you need to give you device pins. destroyed if they are connected as outputs. To prevent this
Select “Assignments” and “Pin Planner”. Under location, from occurring, unused pins should be set as tri-stated.
type in a pin number for A, B, C, and Y (in this case type 2. In the “Assignment” menu select “Device”
in 96, 92, 91,a nd 89 respectively). Exit out of pin planner. 3. Select “Device and Pin Options…”

Figure 15: Pin Planner

4. Select the “Unused pins” tab and then select “As input tri-
3. Recompile and open your bdf. The result USED TO stated” Press “Ok”. Press “Ok”.
LOOK something like the below image, but now does not
D. Programming
seem to change. If you can figure out how to make it
1. Make sure the driver is installed. Go to this website if you
appear as below, please let me know!
have not installed the driver.
2. Unless your breadboard is completely empty of wires and
components, remove your CPLD board from your
breadboard. This will prevent possible shorts.
3. Using your USB-B cable, connect your board to your
computer. A green light should turn on.
4. Connect your USB-Blaster to your computer and to your
CPLD board.
5. On Quartus, select “Tools” and “Programmer”.
6. Select “Hardware Setup” and then select (double-click on)
USB-Blaster. (See Figure 17.) If it does not show up make
sure your USB-Baster is plugged into your computer and
Figure 16: Bdf with pin assignments your driver is installed. Then press “Close”. If you are on
a mac using a virtual machine, make sure your USB-blaster
is connected to your virtual machine. Look in your virtual
C. Tri-stating unused pins machine settings for something relating to USB
1. In the default configuration, Quartus will program unused Connection Preferences.
pins as outputs. The functions of these pins can be 7. Make sure your mode is “JTAG”.
University of Florida EEL 3701 Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering Revision 0 20-May-18
Page 8/8 Quartus Tutorial with Basic Graphical Gate Entry and Simulation
(Last verified for Quartus Prime Lite Edition 17.1)
V. Archiving Your Project
A. Archiving your project into a qar file
1. Archiving a project will save the relevant project files into
a single compressed file. In the "Project” menu, select
“Archive Project..."
2. Change the archive name, if necessary, and select
"Archive." The archive file will have the file name
extension qar, e.g., the file name might be “Lab6A.qar.”
VI. Miscellaneous
A “wire” component in Quartus will allow you to connect an
input to directly to an output. You can think of this as a Level
Shifter with no bubbles, i.e., it does change the activation level.

Figure 17: Programmer

8. Select “Add File” and go to the “output_files” directory.

Select lab1_ex.pof. Press “Open”.
9. Click the boxes under Program/Configure and Verify.
10. Press “Start”. Progress should read “100% Successful.” Figure 18: Wire component
The 2 orange lights should now turn on. If under Progress
it says “Failed”, make sure your USB-Blaster is not
plugged in backwards and make sure it is plugged into all
the pins. If that is not the issue, check your soldering.
11. Remove the USB-Blaster and USB-B cable. Insert your
CPLD into your breadboard. Do not plug in power until
you wire it up.
12. To avoid having to repeat step 8 every time you program,
you can save this configuration. Press “File” and “Save
As”. Name your file “lab1_ex”.
E. Exporting Pin Assignments
1. Sometimes when you make multiple projects, you want to
use the same pin assignments so you don’t need to rewire
the board. As long as you give the input and output pins
the same names, you can easily do this by exporting the pin
assignments from one project as a “.qsf” file and importing
it to another project.
2. To export assignments, select “Assignments” and “Export
Assignments”. You may change the location you wish to
save your qsf but do not change the name.
3. To import assignments, select “Assignments” and “Import
Assignments. Click the “…” and locate the “.qsf” file.
Press “Open”. Press “Ok”. If you have any additional pins
that was not in your original file, go to pin planner and give
those pins location. If there are pins that are not in the new
project, they will be ignored. Recompile.
F. Deleting Pin Assignments
To delete Pin Assignments, select “Assignments” and “Remove
Assignments”. Check “Pin, Location & Routing Assignments”
and Press “OK”. Recompile.