Chapter Three

 The inverter (NOT circuits ) performs the operation called inversion and
complementation. The inventor changes one logic level to the opposite level. In
terms of bits, it changes a 1 and a 0 and a 0 and a1.
 Standard logic symbols for the inverter are shown part a shows distinctive shape
symbols, part b shows the rectangular outline symbols.
 In this course distinctive shape symbols are used.
 The negation indicator is a “bubble” ( ) that indicates inversion or
complementation when it appears on the input or output of any logic
element, as shown in Figure bellow for the inverter.

 Generally, inputs are on the left of a logic symbol and the output is on the
right. When appearing on the input, the bubble means that a 0 is the active
or asserted input state, and the input is called an active-LOW input.
 When appearing on the output, the bubble means that a 0 is the active or
asserted output state, and the output is called an active LOW output.
 The absence of a bubble on the input or output means that a 1 is the active
or asserted state, and in this case, the input or output is called active-HIGH.
 When a HIGH level is applied to an inverter input, a LOW level will appear on its
output. When a LOW level is applied to its input, a HIGH will appear on its output.
 This operation is summarized in the Table bellow , which shows the output for each
possible input in terms of levels and corresponding bits. A table such as this is
called a truth table.

Inverter Operation
 When the input is LOW, the output is HIGH; when the input is HIGH, the output is
LOW, thereby producing an inverted output pulse. In the picture below t1 and t2
indicate the corresponding points on the input and output pulse waveforms.
 Timing diagram is basically a graph that accurately displays the
relationship of two or more waveforms with respect to each other on a time
basis.
 For example, the relationship of the output pulse to the input pulse in the
following figure can be shown with a simple timing diagram by aligning the
two pulses so that the occurrence of the pulse edges appear in the proper
time relationship.
 A timing diagram shows how two or more waveforms relate in time.

 The rising edge of the input pulse and the falling edge of the output pulse
occur at the same time(ideally). Similarly, the rising edge of the input pulse
and the falling edge of the output pulse occur at the same time(ideally).
 In Boolean algebra, which is the mathematics of logic circuits. A variable is
generally designated by one or two letters although there can be more.
 Letters near the beginning of the alphabet usually designate inputs, while letters
near the end of the alphabet usually designate outputs. The complement of a
variable is designated by a bar over the letter.
 A variable can take on a value of either 1 or 0. If a given variable is 1, its
complement is 0 and vice versa. The operation of an inverter (NOT circuit) can be
expressed as follows: If the input variable is called A and the output variable is
called X, then

 This expression states that the output is the complement of the input, so if A = 0,
then X = 1, and if A = 1, then X = 0. Figure illustrates this. The complemented
variable A can be read as “A bar” or “not A.”
 The AND gate is one of the basic gates that can be combined to form
any logic function. An AND gate can have two or more inputs and
performs what is known as logical multiplication.
 The term gate is used to describe a circuit that performs a basic logic
operation. The AND gate is composed of two or more inputs and a
single output, as indicated by the standard logic.

 Inputs are on the left, and the output is on the right in each symbol.
Gates with two inputs are shown; however, an AND gate can have any
number of inputs greater than one.
Operation of an AND Gate
 An AND gate produces a HIGH output only when all of the inputs are
HIGH. When any of the inputs is LOW, the output is LOW.
 Therefore, the basic purpose of an AND gate is to determine when
certain conditions are simultaneously true, as indicated by HIGH
levels on all of its inputs, and to produce a HIGH on its output to
indicate that all these conditions are true.
 For a 2-input AND gate, output X is HIGH only when inputs A and B
are HIGH; X is LOW when either A or B is LOW, or when both A and B
are LOW.
AND Gate Truth Table
The truth table can be expanded to any number of inputs. Although
the terms HIGH and LOW tend to give a “physical” sense to the input
and output states, the truth table is shown with 1s and 0s; a HIGH is
equivalent to a 1 and a LOW is equivalent to a 0 in positive logic.
For any AND gate, regardless of the number of inputs, the output is
HIGH only when all inputs are HIGH. The total number of possible
combinations of binary inputs to a gate is determined by the following
formula: N =2 n
AND Gate Operation with Waveform Inputs
 In most applications, the inputs to a gate are not stationary levels but are voltage
waveforms that change frequently between HIGH and LOW logic levels.
 inputs A and B are both HIGH (1) during the time interval, t1 , making output X
HIGH (1) during this interval. During time interval t2 , input A is LOW (0) and input
B is HIGH (1), so the output is LOW (0). During time interval t3 , both inputs are
HIGH (1) again, and therefore the output is HIGH (1).
AND Gate Operation with Waveform Inputs
 During time interval t4 , input A is HIGH (1) and input B is LOW
(0), resulting in a LOW (0) output. Finally, during time interval t5 ,
input A is LOW (0), input B is LOW (0), and the output is therefore
LOW (0).

 As you know, a diagram of input and output waveforms showing

time relationships is called a timing diagram.

 Remember, when analyzing the waveform operation of logic

gates, it is important to pay careful attention to the time
relationships of all the inputs with respect to each other and to
the output.
Logic Expressions for an AND Gate
The logical AND function of two variables is represented
mathematically either by placing a dot between the two
variables, as , or by simply writing the adjacent letters
without the dot, as AB. We will normally use the latter
notation.
 Boolean multiplication follows the same basic rules
governing binary multiplication, Boolean multiplication is
the same as the AND function.

X = AB
Logic Expressions for an AND Gate
The operation of a 2-input AND gate can be expressed in
equation form as follows: If one input variable is A, if the
other input variable is B, and if the output variable is X, then
the Boolean expression is
X = AB
 The OR gate is another of the basic gates from which all
logic functions are constructed. An OR gate can have two or
more inputs and performs what is known as logical addition.
X = AB
 An OR gate has two or more inputs and one output, as
indicated by the standard logic symbols , where OR gates
with two inputs are illustrated.
 An OR gate can have any number of inputs greater than one.
 Operation of an OR Gate An OR gate produces a HIGH on the output
when any of the inputs is HIGH. The output is LOW only when all of the
inputs are LOW.
 Therefore, an OR gate determines when one or more of its inputs are
HIGH and produces a HIGH on its output to indicate this condition.
 For a 2-input OR gate, output X is HIGH when either input A or input B
is HIGH, or when both A and B are HIGH; X is LOW only when both A
and B are LOW.
OR Gate Truth Table
 The operation of a 2-input OR gate is described in Table.
This truth table can be expanded for any number of inputs;
but regardless of the number of inputs, the output is HIGH
when one or more of the inputs are HIGH.
OR Gate Operation with Waveform Inputs
The operation of a 2-input OR gate is described in Table. This truth
table can be expanded for any number of inputs; but regardless of the
number of inputs, the output is HIGH when one or more of the inputs are
HIGH.
 For example, in Figure 3–20, inputs A and B are both HIGH (1) during time interval t1
, making output X HIGH (1). During time interval t2 , input A is LOW (0), but because
input B is HIGH (1), the output is HIGH (1). Both inputs are LOW (0) during time
interval t3 , so there is a LOW (0) output during this time. During time interval t4 , the
output is HIGH (1) because input A is HIGH (1).
Logic Expressions for an OR Gate
 The logical OR function of two variables is represented
mathematically by a + between the two variables, for
example, A + B.
 The plus sign is read as “OR.” Addition in Boolean algebra
involves variables whose values are either binary 1 or
binary 0. The basic rules for Boolean addition are as follows:
Boolean addition is the same as the OR function.
 Notice that Boolean addition differs from binary addition in
the case where two 1s are added. There is no carry in
Boolean addition.
 The operation of a 2-input OR gate can be expressed as
follows: If one input variable is A, if the other input variable
is B, and if the output variable is X, then the Boolean
expression is : X = A + B
Boolean addition is the same as the OR function.
 This evaluation shows that the output X of an OR gate is a 1
(HIGH) when any one or more of the inputs are 1 (HIGH). A
similar analysis can be extended to OR gates with any
number of input variables.
 The term NAND is a contraction of NOT-AND and implies
an AND function with a complemented (inverted) output.
 The standard logic symbol for a 2-input NAND gate and its
equivalency to an AND gate followed by an inverter are
shown in Figure, where the symbol K means equivalent to.

Operation of a NAND Gate

 A NAND gate produces a LOW output only when all the inputs are
HIGH. When any of the inputs is LOW, the output will be HIGH.
 For the specific case of a 2-input NAND gate, as shown in Figure with
the inputs labeled A and B and the output labeled X, the operation can
be stated as follows:
 For a 2-input NAND gate, output X is LOW only when inputs
A and B are HIGH; X is HIGH when either A or B is LOW, or
when both A and B are LOW.
 This operation is opposite that of the AND in terms of the
output level.
 In a NAND gate, the LOW level (0) is the active or asserted
output level, as indicated by the bubble on the output.
Figure illustrates the operation of a 2-input NAND gate for
all four input combinations, and Table above is the truth
table summarizing the logical operation of the 2-input
NAND gate.
NAND Gate Operation with Waveform Inputs
 Now let’s look at the pulse waveform operation of a NAND gate.
Remember from the truth table that the only time a LOW output occurs
is when all of the inputs are HIGH.
Negative-OR Equivalent Operation of a NAND Gate
 For a 2-input NAND gate performing a negative-OR operation, output X is HIGH
when either input A or input B is LOW, or when both A and B are LOW.
 When a NAND gate is used to detect one or more LOWs on its inputs rather than all
HIGHs, it is performing the negative-OR operation and is represented by the
standard logic symbol shown in Figure
Logic Expressions for a NAND Gate
 The Boolean expression for the output of a 2-input NAND gate is X = AB This expression
says that the two input variables, A and B, are first ANDed and then complemented, as
indicated by the bar over the AND expression. This is a description in equation form of the
operation of a NAND gate with two inputs.
 The NAND expression can be extended to more than two input variables by including
additional letters to represent the other variables.
 The NOR gate, like the NAND gate, is a useful logic element because it can also be
used as a universal gate; that is, NOR gates can be used in combination to perform
the AND, OR, and inverter operations.
 The term NOR is a contraction of NOT-OR and implies an OR function with an
inverted (complemented) output. The standard logic symbol for a 2-input NOR gate
and its equivalent OR gate followed by an inverter are shown in Figure
Operation of a NOR Gate
 For a 2-input NOR gate, output X is LOW when either input A or input B is HIGH, or
when both A and B are HIGH; X is HIGH only when both A and B are LOW.
NOR Gate Operation with Waveform Inputs
 Again, as with the other types of gates, we will simply follow the truth table
operation to determine the output waveforms in the proper time relationship to the
inputs.
Negative-AND Equivalent Operation of the NOR Gate
 For a 2-input NOR gate performing a negative-AND operation, output
X is HIGH only when both inputs A and B are LOW.
 When a NOR gate is used to detect all LOWs on its inputs rather than
one or more HIGHs, it is performing the negative-AND operation and
is represented by the standard symbol in Figure
Logic Expressions for a NOR Gate
The Boolean expression for the output of a 2-input NOR gate can be
written as:

This equation says that the two input variables are first ORed and then
complemented, as indicated by the bar over the OR expression.
Evaluating this expression, you get the results shown in Table
 Logic Expressions for a NOR Gate
 Standard symbols for an exclusive-OR (XOR for short) gate are shown in Figure 3–
42. The XOR gate has only two inputs.

 For an exclusive-OR gate, output X is HIGH when input A is LOW and input B is
HIGH, or when input A is HIGH and input B is LOW; X is LOW when A and B are both
HIGH or both LOW.
Logic Expressions for a NOR Gate
 The four possible input combinations and the resulting outputs for an XOR gate are
illustrated in Figure
 The HIGH level is the active or asserted output level and occurs only when the
inputs are at opposite levels. The operation of an XOR gate is summarized in the
truth table shown in Table
The Exclusive-NOR Gate
 For an exclusive-NOR gate, output X is LOW when input A is LOW and input B is
HIGH, or when A is HIGH and B is LOW; X is HIGH when A and B are both HIGH or
both LOW.
The Exclusive-NOR Gate
 The four possible input combinations and the resulting outputs for an XNOR gate
are shown in Figure . The operation of an XNOR gate is summarized in Table 3–12.
Notice that the output is HIGH when the same level is on both inputs.
The Exclusive-NOR Gate
Operation with Waveform Inputs
 Figure 3–47 for an XOR gate. You can see that the input waveforms A and B are at
opposite levels during time intervals t2 and t4 . Therefore, the output X is HIGH
during these two times. Since both inputs are at the same level, either both HIGH or
both LOW, during time intervals t1 and t3 , the output is LOW during those times as
shown in the timing diagram.