VD3404 HARDWARE MODELING

USING VHDL
(Theory cum Practical Course)

Name of the Student :

…………………...………
Register Number :….…………………………
…….
………………………………
Year / Semester / Section :.

Branch :
………………………………
.

Department of Electronics Engineering

(VLSI Design Technology)
 Register No:

BONAFIDE CERTIFICATE

Certified that this is the bonafide record of work done by

Mr./Ms.……………………………………………………… of …… semester

B.E. ..……………………………………..…………………………………… in

the …………………………………………………………………..Laboratory

during the academic year ……............................

Staff in-Charge Head of the Department

Submitted for the End semester Practical Examination held on …………………………

Internal Examiner External Examiner

Date: …………… Date: ……………...

VISION OF THE INSTITUTION:

To be an eminent center for Academia, Industry and Research by imparting

knowledge, relevant practices and inculcating human values to address global
challenges through novelty and sustainability.

MISSION OF THE INSTITUTION:

IM1: To create next generation leaders by effective teaching learning

methodologies and instill scientific spark in them to meet the global
challenges.
IM2: To transform lives through deployment of emerging technology, novelty
and sustainability.
IM3: To inculcate human values and ethical principles to cater to the societal
needs.
IM4: To contribute towards the research ecosystem by providing a suitable,
effective platform for interaction between industry, academia and R & D
establishments.
IM5: To nurture incubation centers enabling structured entrepreneurship and
start-ups.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Vision of the Department:

To Excel in the emerging areas of Electronics and Communication

Engineering by imparting knowledge, relevant practices and inculcating human
values to transform the students as potential resources to cater the industrial and
societal development through sustainable technology growth.

Mission of the Department:

DM1: To provide strong fundamentals and technical skills through effective

teaching learning Methodologies.
DM2: To transform lives of the students by fostering ethical values, creativity
and innovation to become Entrepreneurs and establish Start-ups.
DM3: To habituate the students to focus on sustainable solutions to improve
the quality of life and welfare of the society.
DM4: To provide an ambience for research through collaborations with
industry and academia.
DM5: To inculcate learning of emerging technologies for pursuing higher
studies leading to lifelong learning.
 Program Educational Objectives:

Graduates will be able to

PEO1: Contribute to the industry as an Engineer through sound knowledge acquired in
core engineering to develop new processes and implement the solutions for
industrial problems.
PEO2: Establish an organization / industry as an entrepreneur with professionalism,
leadership quality, teamwork, and ethical values to meet the societal needs.
PEO3: Create a better future by pursuing higher education / research and develop the
sustainable products / solutions to meet the demand.

Program Outcomes:

1. Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs
with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge
and research methods including design of experiments, analysis and interpretation of
data, and synthesis of theinformation to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
 6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant tothe professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with
the engineering community and with society at large, such as, being able to comprehend
and write effective reports and design documentation, make effective presentations, and
give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.

State the Program Specific Outcomes:

PSO1: To analyze, design and develop quality solutions in Communication Engineering by

adapting the emerging technologies.
PSO2 : To innovate ideas and solutions for real time problems in industrial and domestic
Automation using Embedded & IOT tools.
 Course Code HARDWARE MODELING USING VHDL L T P C
EC2V11 LABORATORY 0 0 2 1

OBJECTIVES:

The student should be able:

• To know introduction to VHDL, its structure, data types and operators, logic synthesis.
• To Understand syntax and statement of Behavioral Modeling using VHDL language
• To illustrate Gate level modelling, Dataflow level modeling, in VHDL
• To introduce Advanced Topics in VHDL using Packages and libraries
• To understand the concept of Hardware Modelling using VHDL

List of Experiments:

1. Circuit implementation using VHDL (Dataflow, Gate level and Behavioral)

2. VHDL implementation of System Tasks and Functions
3. Design of ADDERS - Ripple carry adder – carry save adder – carry select/skip
adder Implementation in VHDL gate-level or behavioural modelling – synthesis report and
analysis
4. Realization of VLSI Multiplier (Braun and booth multiplier, Wallace Tree multiplier)
Implementation in VHDL gate-level or behavioural modelling-synthesis report and
analysis.
5. Realisation of 1K x 8 RAM & ROM- 4K x 16 RAM & ROM – Realisation of 4 bit and high
order bit ALU – Implementation in VHDL behavioural modelling – synthesis report with
analysis.
6. Design and Simulation of Real Time Clock using Behavioral VHDL

Total Period: 30

OUTCOMES:

At the end of the course, the student should be able to:

CO1: Understand the basics of Hardware Description Languages, Program structure and basic
language elements of VHDL
CO2: Understand various statements and delay models of behavior modelling Using VHDL
CO3: Understand the gate level and structural level modelling using VHDL
CO4: Understand an advanced technique in VHDL
CO5: Summarize various optimization methods, circuit design of Datapath and memory system
 HARDWARE MODELING USING VHDL LABORATORY

Course Objectives:

➢ To know introduction to VHDL, its structure, data types and operators, logic synthesis.
➢ To Understand syntax and statement of Behavioral Modeling using VHDL language
➢ To illustrate Gate level modelling, Dataflow level modeling, in VHDL
➢ To introduce Advanced Topics in VHDL using Packages and libraries
➢ To understand the concept of Hardware Modelling using VHDL

Course Outcomes:

CO No. Course Outcomes Blooms

Understand the basics of Hardware Description Languages, Program
C301.1 K3
structure and basic language elements of VHDL
Understand various statements and delay models of behavior modelling
C301.2 K3
Using VHDL
C301.3 Understand the gate level and structural level modelling using VHDL K3

C301.4 Understand an advanced technique in VHDL K3

Summarize various optimization methods, circuit design of Datapath and
C301.5 K3
memory system

CO-PO mapping Matrix:

CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

C301.1 3 2 2 3 1 1 1 1

C301.2 3 2 2 1 3 1 1 1 1

C301.3 3 2 2 3 1 1 1 1

C301.4 3 2 2 3 1 1 1 1

C301.5 3 2 2 3 1 1 1 1
 INDEX

EXPERIMENT
PAGE CO PO MAPPING MAR
NAME OF THE EXPERIMENT SIGN
NO. DATE NO. KS
PO1, PO2, PO3, PO4,
Circuit implementation using VHDL PO5, PO9, PO10,
1 (Dataflow, Gate level and Behavioral) PO11, PO12, PSO1,
PSO2

VHDL Implementation of System Tasks PO1, PO2, PO3, PO4,

2 PO5, PO9, PO10, PO11,
and Functions
PO12, PSO1, PSO2

3 Design of Adders
PO1, PO2, PO3, PO4,
16-Bit Ripple Carry Adder PO5, PO9, PO10,
3a
PO11, PO12, PSO1,
PSO2
PO1, PO2, PO3, PO4,
3b 16-Bit Carry Save Adder PO5, PO9, PO10, PO11,
PO12, PSO1, PSO2
16-Bit Carry Select Adder PO1, PO2, PO3, PO4,
3c PO5, PO9, PO10, PO11,
PO12, PSO1, PSO2
PO1, PO2, PO3, PO4,
3d 16-Bit Carry Skip Adder PO5, PO9, PO10, PO11,
PO12, PSO1, PSO2
PO1, PO2, PO3, PO4,
4 Realization of VLSI Multiplier PO5, PO9, PO10, PO11,
PO12, PSO1, PSO2
PO1, PO2, PO3, PO4,
4-Bit BRAUN Multiplier
4a PO5, PO9, PO10, PO11,
PO12, PSO1, PSO2

PO1, PO2, PO3, PO4,

4-Bit Booth Multiplier PO5, PO9, PO10,
4b
PO11, PO12, PSO1,
PSO2
PO1, PO2, PO3, PO4,
4-Bit Wallace Multiplier PO5, PO9, PO10,
4c
PO11, PO12, PSO1,
PSO2
Realization of 1K x 8 RAM & ROM- 4K
x 16 RAM & ROM – Realization of 4 bit PO1, PO2, PO3, PO4,
5 and high order bit ALU – Implementation PO5, PO9, PO10, PO11,
in VHDL behavioural modelling – PO12, PSO1, PSO2
synthesis report with analysis

Design and Simulation of Real Time PO1, PO2, PO3, PO4,

6 PO5, PO9, PO10, PO11,
Clock using Behavioral VHDL
PO12, PSO1, PSO2

CONTENT BEYOND THE SYLLABUS

FPGA Implementation of PO1, PO2, PO3, PO4,

7 PO5, PO9, PO10, PO11,
Combinational Circuits
PO12, PSO1, PSO2
 FPGA Implementation of Combinational PO1, PO2, PO3, PO4,
7a PO5, PO9, PO10, PO11,
Circuits 1
PO12, PSO1, PSO2

FPGA Implementation of Combinational PO1, PO2, PO3, PO4,

7b PO5, PO9, PO10, PO11,
Circuits 2
PO12, PSO1, PSO2

FPGA Implementation of Sequential PO1, PO2, PO3, PO4,

8 PO5, PO9, PO10, PO11,
Circuits
PO12, PSO1, PSO2

PO1, PO2, PO3, PO4,

FPGA Implementation of Sequential PO5, PO9, PO10,
8a
Circuits 1 PO11, PO12, PSO1,
PSO2

PO1, PO2, PO3, PO4,

FPGA Implementation of Sequential PO5, PO9, PO10,
8b
Circuits 2 PO11, PO12, PSO1,
PSO2

PO1, PO2, PO3, PO4,

Implementation of Digital Logic PO5, PO9, PO10,
9
Design PO11, PO12, PSO1,
PSO2

PO1, PO2, PO3, PO4,

FPGA Implementation of Combinational PO5, PO9, PO10,
9a
Circuits & Sequential Circuits PO11, PO12, PSO1,
PSO2

PO1, PO2, PO3, PO4,

FPGA Implementation of Combinational PO5, PO9, PO10,
9a
Circuits & Sequential Circuits PO11, PO12, PSO1,
PSO2
 8:1 MULTIPLEXER

BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 1 Circuit implementation using VHDL
8:1 MULTIPLEXER
DATE:

AIM
To develop the source code for 8:1 Multiplexer using VHDL and obtain its Simulation,
Synthesis using Behavioral, Structural and Dataflow Modelling.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

PROCEDURE
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM

VHDL SOURCE CODE (BEHAVIOURAL MODEL):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX8to1 is
Port (
sel : in STD_LOGIC_VECTOR(2 downto 0);
inputs : in STD_LOGIC_VECTOR(7 downto 0);
y : out STD_LOGIC
);
end MUX8to1;
architecture Behavioral of MUX8to1 is
begin
y <= inputs(0) when sel = "000" else
inputs(1) when sel = "001" else
inputs(2) when sel = "010" else
inputs(3) when sel = "011" else
inputs(4) when sel = "100" else
inputs(5) when sel = "101" else
 DATAFLOW MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

 inputs(6) when sel = "110" else
inputs(7) when sel = "111" else
'0';
end Behavioral;

VHDL SOURCE CODE (DATAFLOW MODEL):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_8to1 is
Port ( inputs : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC);
end mux_8to1;

architecture Dataflow of mux_8to1 is

begin
y <= (inputs(0) and (not sel(2)) and (not sel(1)) and (not sel(0))) or
(inputs(1) and (not sel(2)) and (not sel(1)) and sel(0)) or
(inputs(2) and (not sel(2)) and sel(1) and (not sel(0))) or
(inputs(3) and (not sel(2)) and sel(1) and sel(0)) or
(inputs(4) and sel(2) and (not sel(1)) and (not sel(0))) or
(inputs(5) and sel(2) and (not sel(1)) and sel(0)) or
(inputs(6) and sel(2) and sel(1) and (not sel(0))) or
(inputs(7) and sel(2) and sel(1) and sel(0));
end Dataflow;

VHDL SOURCE CODE (STRUCTURAL MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_8to1 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end mux_8to1;
 architecture gate_level of mux_8to1 is
signal A, B, C, D, E, F : STD_LOGIC;
begin
A <= (not S(2)) and (not S(1)) and (not S(0)) and I(0);
B <= (not S(2)) and (not S(1)) and S(0) and I(1);
C <= (not S(2)) and S(1) and (not S(0)) and I(2);
D <= (not S(2)) and S(1) and S(0) and I(3);
E <= S(2) and (not S(1)) and (not S(0)) and I(4);
F <= S(2) and (not S(1)) and S(0) and I(5);

G <= S(2) and S(1) and (not S(0)) and I(6);

H <= S(2) and S(1) and S(0) and I(7);

Y <= A or B or C or D or E or F or G or H;
end gate_level;

TEST BENCH(VHDL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity mux_8to1_tb is
end mux_8to1_tb;

architecture testbench of mux_8to1_tb is

component MUX8to1
Port (
inputs : in STD_LOGIC_VECTOR(7 downto 0);
sel : in STD_LOGIC_VECTOR(2 downto 0);
y : out STD_LOGIC
);
end component;

signal inputs : STD_LOGIC_VECTOR(7 downto 0) := "00000000";

signal sel : STD_LOGIC_VECTOR(2 downto 0) := "000";

signal y : STD_LOGIC;

begin
uut: MUX8to1 port map (
inputs => inputs,
sel => sel,
y => y
);
stim_proc: process
begin

inputs <= "11001010";

sel <= "000";
wait for 10 ns;

sel <= "001";

wait for 10 ns;

sel <= "010";

wait for 10 ns;

sel <= "011";

wait for 10 ns;

sel <= "100";

wait for 10 ns;

sel <= "101";

wait for 10 ns;

sel <= "110";

wait for 10 ns;

sel <= "111";

wait for 10 ns;

sel <= "000";

wait for 10 ns;

wait;
end process;
end testbench;

RESULT
Thus the outputs of Multiplexers are verified by synthesizing and simulating VHDL
code. By completing this experiment, students will gain a deeper understanding of Multiplexer.
Problems encountered in the designing of Multiplexer are identified in the study (PO2) are
analyzed with Xilinx Vivado tool (PO5) and results are verified (PO3) through simulation
(PO4).
EXP NO: 2 SYSTEM TASKS AND FUNCTIONS
DATE:

AIM
To develop the source code for a VHDL program for implementation of System Tasks
and Functions.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM

VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Entity Declaration
entity SystemTasksFunctions is
Port (
clk : in std_logic;
reset : in std_logic;
input_a : in std_logic_vector(7 downto 0);
input_b : in std_logic_vector(7 downto 0);
result_out: out std_logic_vector(7 downto 0)
);
end SystemTasksFunctions;

architecture Behavioral of SystemTasksFunctions is

signal internal_result : std_logic_vector(7 downto 0);
 begin
sum := std_logic_vector(unsigned(a) + unsigned(b));
return sum;
end function;

-- Procedure to multiply two vectors

procedure multiply_vectors(a, b : std_logic_vector(7 downto 0); signal product : out std_logic_vector(7
downto 0)) is
begin
product <= std_logic_vector(unsigned(a) * unsigned(b));
end procedure;

begin

-- Process block for sequential logic

process(clk, reset)
begin
if reset = '1' then
internal_result <= (others => '0');
elsif rising_edge(clk) then
-- Call the add function
internal_result <= add_vectors(input_a, input_b);
-- Call the multiply procedure
multiply_vectors(input_a, input_b, internal_result);
end if;
end process;

-- Output assignment
result_out <= internal_result;

end Behavioral;

TEST BENCH(VHDL)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Entity Declaration for Testbench
entity SystemTasksFunctions_tb is
end SystemTasksFunctions_tb;

-- Architecture Body for Testbench

architecture Behavioral of SystemTasksFunctions_tb is

-- Signal declarations for inputs and outputs

signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal input_a : std_logic_vector(7 downto 0);
signal input_b : std_logic_vector(7 downto 0);
signal result_out: std_logic_vector(7 downto 0);

-- Component declaration for the Unit Under Test (UUT)

component SystemTasksFunctions
Port (
clk : in std_logic;
reset : in std_logic;
input_a : in std_logic_vector(7 downto 0);
input_b : in std_logic_vector(7 downto 0);
result_out: out std_logic_vector(7 downto 0)
);
end component;

begin

-- Instantiate the UUT

UUT: SystemTasksFunctions
Port map (
clk => clk,
reset => reset,
input_a => input_a,
input_b => input_b,
result_out=> result_out
);
clk_process : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stimulus_process : process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';

input_a <= "00000001"; -- 1

input_b <= "00000010"; -- 2
wait for 20 ns;

input_a <= "00000101"; -- 5

input_b <= "00000011"; -- 3
wait for 20 ns;
input_a <= "00001000"; -- 8
input_b <= "00000100"; -- 4
wait for 20 ns;

-- Test case 5: Apply another set of values

input_a <= "00001100"; -- 12
input_b <= "00001001"; -- 9
wait for 20 ns;
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing System Tasks and Functions are verified
by synthesizing and simulating VHDL code. By completing this experiment, students will gain
a deeper understanding of System Tasks and Functions. Problems encountered in the designing
of System Tasks and Functions are identified in the study (PO2) are analyzed with Xilinx
Vivado tool (PO5) and results are verified (PO3) through simulation (PO4).
 RIPPLE CARRY ADDER

BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 3a
DESIGN OF ADDERS
RIPPLE CARRY ADDER
DATE:

AIM
To develop the source code for different types of 16 Bit Ripple Carry Adder using VHDL and
obtains its Simulation, Synthesis using Behavioral, Structural and Dataflow Modelling.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

PROCEDURE
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE (BEHAVIOURAL MODEL)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RippleCarryAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC
);
end RippleCarryAdder16bit;
 DATAFLOW MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

architecture Behavioral of RippleCarryAdder16bit is
begin
process(A, B, Cin)
variable carry: STD_LOGIC;
variable temp_sum: STD_LOGIC_VECTOR(15 downto 0);
begin
carry := Cin;
for i in 0 to 15 loop
temp_sum(i) := A(i) xor B(i) xor carry;
carry := (A(i) and B(i)) or (A(i) and carry) or (B(i) and carry);
end loop;
Sum <= temp_sum;
Cout <= carry;
end process;
end Behavioral;

VHDL SOURCE CODE (DATAFLOW MODEL):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RippleCarryAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Cin : in STD_LOGIC; -- Carry-in
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC
);
end RippleCarryAdder16bit;

architecture Dataflow of RippleCarryAdder16bit is

signal Carry: STD_LOGIC_VECTOR(15 downto 0);
begin
Sum(0) <= A(0) xor B(0) xor Cin;
Carry(0) <= (A(0) and B(0)) or (A(0) and Cin) or (B(0) and Cin);
 gen: for i in 1 to 15 generate
Sum(i) <= A(i) xor B(i) xor Carry(i-1);
Carry(i) <= (A(i) and B(i)) or (A(i) and Carry(i-1)) or (B(i) and Carry(i-1));
end generate;
Cout <= Carry(15);
end Dataflow;

VHDL SOURCE CODE (STRUCTURAL MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdder is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end FullAdder;
architecture Structural of FullAdder is
begin
Sum <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RippleCarryAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC
);
end RippleCarryAdder16bit;
architecture Structural of RippleCarryAdder16bit is
signal Carry: STD_LOGIC_VECTOR(15 downto 0);

component FullAdder
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end component;

begin

FA0: FullAdder Port map (

A => A(0),
B => B(0),
Cin => Cin,
Sum => Sum(0),
Cout => Carry(0)
);

FA1: FullAdder Port map (

A => A(1),
B => B(1),
Cin => Carry(0),
Sum => Sum(1),
Cout => Carry(1)
);

FA2: FullAdder Port map (

A => A(2),
B => B(2),
Cin => Carry(1),
Sum => Sum(2),
Cout => Carry(2)
);
.
 .
.
.
FA15: FullAdder Port map (
A => A(15),
B => B(15),
Cin => Carry(14),
Sum => Sum(15),
Cout => Cout
);

end Structural;

TEST BENCH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb_RippleCarryAdder16bit is
end tb_RippleCarryAdder16bit;

architecture sim of tb_RippleCarryAdder16bit is

component RippleCarryAdder16bit
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC
);
end component;

signal A : STD_LOGIC_VECTOR(15 downto 0);

signal B : STD_LOGIC_VECTOR(15 downto 0);
signal Cin : STD_LOGIC;
signal Sum : STD_LOGIC_VECTOR(15 downto 0);
signal Cout : STD_LOGIC;

begin
uut: RippleCarryAdder16bit
Port map (
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);
 stim_proc: process
begin
-- Initialize inputs
A <= (others => '0');
B <= (others => '0');

Cin <= '0';

wait for 100 ps;

A <= "0000000000000001";
B <= "0000000000000010";
Cin <= '0';
wait for 100 ps;

A <= "1111000000000111";
B <= "1110000000000011";
Cin <= '0';
wait for 100 ps;

A <= "1111111111111111";
B <= "0000000000000001";
Cin <= '0';
wait for 100 ps;

A <= "1010101010101010";
B <= "0101010101010101";
Cin <= '1';
wait for 100 ps;

wait;
end process;
end sim;

RESULT
Thus the outputs of a program implementing 16-bit Ripple Carry Adder are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 16-bit Ripple Carry Adder. Problems encountered in the designing of
16-bit Ripple Carry Adder are identified in the study (PO2) are analyzed with Xilinx Vivado
tool (PO5) and results are verified (PO3) through simulation (PO4).
 CARRY SAVE ADDER
BEHAVIOURAL MODEL
Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 3b CARRY SAVE ADDER
DATE:

AIM
To develop the source code for different types of 16 Bit Carry Save Adder using VHDL and
obtains its Simulation, Synthesis using Behavioral, Structural and Dataflow Modelling.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

PROCEDURE
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM

VHDL SOURCE CODE (BEHAVIOURAL MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CarrySaveAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input A
B : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input B
C : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input C
Sum : out STD_LOGIC_VECTOR(15 downto 0); -- Intermediate sum output
Carry : out STD_LOGIC_VECTOR(15 downto 0) -- Carry output
);
end CarrySaveAdder16bit;

architecture Behavioral of CarrySaveAdder16bit is

begin
process(A, B, C)
begin
-- Sum is calculated as the bitwise XOR of A, B, and C
Sum <= A xor B xor C;
 DATAFLOW MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

 -- Carry is calculated as (A and B) or (B and C) or (C and A)
Carry <= (A and B) or (B and C) or (C and A);
end process;
end Behavioral;

VHDL SOURCE CODE (DATAFLOW MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CarrySaveAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input A
B : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input B
C : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input C
Sum : out STD_LOGIC_VECTOR(15 downto 0); -- Intermediate sum output
Carry : out STD_LOGIC_VECTOR(15 downto 0) -- Carry output
);
end CarrySaveAdder16bit;

architecture Dataflow of CarrySaveAdder16bit is

begin
Sum <= A xor B xor C;
Carry <= (A and B) or (B and C) or (C and A);
end Dataflow

VHDL SOURCE CODE (STRUCTURAL MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end FullAdder;
architecture Structural of FullAdder is
begin
Sum <= A xor B xor Cin;
Cout <= (A and B) or (B and Cin) or (Cin and A);
end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CarrySaveAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
C : in STD_LOGIC_VECTOR(15 downto 0);
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Carry : out STD_LOGIC_VECTOR(15 downto 0)
);
end CarrySaveAdder16bit;

architecture Structural of CarrySaveAdder16bit is

signal Carry_internal : STD_LOGIC_VECTOR(15 downto 0);
component FullAdder
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end component;

begin
FA0: FullAdder Port map (
A => A(0),
B => B(0),
Cin => C(0),
Sum => Sum(0),
Cout => Carry_internal(0)
);
 FA1: FullAdder Port map (
A => A(1),
B => B(1),
Cin => C(1),
Sum => Sum(1),
Cout => Carry_internal(1)
);

FA2: FullAdder Port map (

A => A(2),
B => B(2),
Cin => C(2),
Sum => Sum(2),
Cout => Carry_internal(2)
);
.
.
.
FA15: FullAdder Port map (
A => A(15),
B => B(15),
Cin => C(15),
Sum => Sum(15),
Cout => Carry
);
end Structural;
TEST BENCH :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Adder16bit is
end Adder16bit;

architecture sim of Adder16bit is

component CarrySaveAdder16bit
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
C : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Carry : out STD_LOGIC
);
end component;

signal A : STD_LOGIC_VECTOR(15 downto 0);

signal B : STD_LOGIC_VECTOR(15 downto 0);
signal C : STD_LOGIC;
signal Sum : STD_LOGIC_VECTOR(15 downto 0);
signal carry : STD_LOGIC;

begin
uut: CarrySaveAdder16bit
Port map (
A => A,
B => B,
C => C,
Sum => Sum,
carry => carry
);

stim_proc: process
begin
-- Initialize inputs
A <= (others => '0');
B <= (others => '0');
C <= '0';

wait for 100 ps;

A <= "0000000000000001";
B <= "0000000000000010";
C <= '0';
wait for 100 ps;
A <= "1111000000000111";
 B <= "1110000000000011";
C <= '0';
wait for 100 ps;

A <= "1111111111111111";
B <= "0000000000000001";
C <= '0';
wait for 100 ps;

A <= "1010101010101010";
B <= "0101010101010101";
C <= '1';
wait for 100 ps;

wait;
end process;
end sim;

RESULT
Thus the outputs of a program implementing 16-bit Carry Save Adder are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 16-bit Carry Save Adder Problems encountered in the designing of 16-
bit Carry Save Adder are identified in the study (PO2) are analyzed with Xilinx Vivado tool
(PO5) and results are verified (PO3) through simulation (PO4).
 CARRY SELECT ADDER
BEHAVIOURAL MODEL
Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 3c CARRY SELECT ADDER
DATE:

AIM
To develop the source code for different types of 16 Bit Carry Select Adder using VHDL and
obtains its Simulation, Synthesis using Behavioral, Structural and Dataflow Modelling.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

PROCEDURE
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE (BEHAVIOURAL MODEL)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity carry_select_adder_16bit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC);
end carry_select_adder_16bit;

architecture Behavioral of carry_select_adder_16bit is

signal S0, S1 : STD_LOGIC_VECTOR(15 downto 0);

signal C0, C1 : STD_LOGIC_VECTOR(3 downto 0);

begin
-- 4-bit Ripple Carry Adder for least significant bits
S0(3 downto 0) <= A(3 downto 0) + B(3 downto 0) + Cin;
 DATAFLOW MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

 C0(0) <= (A(3) and B(3)) or (A(3) and Cin) or (B(3) and Cin);
-- Carry Select Adder blocks (4-bit each)
gen_csa: for i in 1 to 3 generate
-- Adder with Carry-in = 0
S0((4*i)+3 downto 4*i) <= A((4*i)+3 downto 4*i) + B((4*i)+3 downto 4*i);
C0(i) <= (A((4*i)+3) and B((4*i)+3)) or
(A((4*i)+3) and C0(i-1)) or
(B((4*i)+3) and C0(i-1));

-- Adder with Carry-in = 1

S1((4*i)+3 downto 4*i) <= A((4*i)+3 downto 4*i) + B((4*i)+3 downto 4*i) + '1';
C1(i) <= (A((4*i)+3) and B((4*i)+3)) or
(A((4*i)+3) and C1(i-1)) or
(B((4*i)+3) and C1(i-1));
end generate gen_csa;

-- Final sum and carry-out selection

Sum(3 downto 0) <= S0(3 downto 0);
Sum(15 downto 4) <= S0(15 downto 4) when C0(0) = '0' else S1(15 downto 4);
Cout <= C0(3) when C0(0) = '0' else C1(3);

end Behavioral;

VHDL SOURCE CODE (DATAFLOW MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity carry_select_adder_16bit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC);
end carry_select_adder_16bit;

architecture Dataflow of carry_select_adder_16bit is

signal S0, S1 : STD_LOGIC_VECTOR(15 downto 0);
 signal C0, C1 : STD_LOGIC_VECTOR(3 downto 0);
begin
S0(3 downto 0) <= A(3 downto 0) + B(3 downto 0) + Cin;
C0(0) <= (A(3) and B(3)) or (A(3) and Cin) or (B(3) and Cin);

gen_csa: for i in 1 to 3 generate

S0((4*i)+3 downto 4*i) <= A((4*i)+3 downto 4*i) + B((4*i)+3 downto 4*i);
C0(i) <= (A((4*i)+3) and B((4*i)+3)) or
(A((4*i)+3) and C0(i-1)) or
(B((4*i)+3) and C0(i-1));
S1((4*i)+3 downto 4*i) <= A((4*i)+3 downto 4*i) + B((4*i)+3 downto 4*i) + '1';
C1(i) <= (A((4*i)+3) and B((4*i)+3)) or
(A((4*i)+3) and C1(i-1)) or
(B((4*i)+3) and C1(i-1));
end generate gen_csa;
Sum(3 downto 0) <= S0(3 downto 0);
Sum(15 downto 4) <= S0(15 downto 4) when C0(0) = '0' else S1(15 downto 4);
Cout <= C0(3) when C0(0) = '0' else C1(3);
end Dataflow;

VHDL SOURCE CODE (STRUCTURAL MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdder is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end FullAdder;

architecture Structural of FullAdder is

begin
Sum <= A xor B xor Cin;
 Cout <= (A and B) or (B and Cin) or (Cin and A);
end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RippleCarryAdder8bit is
Port (
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(7 downto 0);
Cout : out STD_LOGIC
);
end RippleCarryAdder8bit;

architecture Structural of RippleCarryAdder8bit is

signal carry : STD_LOGIC_VECTOR(8 downto 0); -- Intermediate carries

component FullAdder
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end component;

begin
carry(0) <= Cin;

FA0: FullAdder Port map (

A => A(0),
B => B(0),
Cin => carry(0),
Sum => Sum(0),
Cout => carry(1)
);
 FA1: FullAdder Port map (
A => A(1),
B => B(1),
Cin => carry(1),
Sum => Sum(1),
Cout => carry(2)
);

-- Continue similarly for FA2 to FA6

FA7: FullAdder Port map (

A => A(7),
B => B(7),
Cin => carry(7),
Sum => Sum(7),
Cout => carry(8)
);

Cout <= carry(8);

end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CarrySelectAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input A
B : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input B
Cin : in STD_LOGIC; -- Carry input
Sum : out STD_LOGIC_VECTOR(15 downto 0); -- Sum output
Cout : out STD_LOGIC -- Carry output
);
end CarrySelectAdder16bit;

architecture Structural of CarrySelectAdder16bit is

signal Sum0, Sum1 : STD_LOGIC_VECTOR(15 downto 0);
signal Cout0, Cout1 : STD_LOGIC;
signal muxSum, muxCout : STD_LOGIC_VECTOR(15 downto 0);
 component RippleCarryAdder8bit
Port (
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(7 downto 0);
Cout : out STD_LOGIC
);
end component;

component MUX2to1
Port (
A0 : in STD_LOGIC_VECTOR(15 downto 0);
A1 : in STD_LOGIC_VECTOR(15 downto 0);
Sel : in STD_LOGIC;
MuxOut : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;

begin
-- Lower 8-bit adder with carry-in 0
RCA_low0: RippleCarryAdder8bit Port map (
A => A(7 downto 0),
B => B(7 downto 0),
Cin => '0',
Sum => Sum0(7 downto 0),
Cout => Cout0
);

-- Lower 8-bit adder with carry-in 1

RCA_low1: RippleCarryAdder8bit Port map (
A => A(7 downto 0),
B => B(7 downto 0),
Cin => '1',
Sum => Sum1(7 downto 0),
Cout => Cout1
);
 RCA_high0: RippleCarryAdder8bit Port map (
A => A(15 downto 8),
B => B(15 downto 8),
Cin => Cout0,
Sum => Sum0(15 downto 8),
Cout => Cout
);

RCA_high1: RippleCarryAdder8bit Port map (

A => A(15 downto 8),
B => B(15 downto 8),
Cin => Cout1,
Sum => Sum1(15 downto 8),
Cout => Cout
);

-- Multiplexers to select the correct sum and carry based on Cin

MUX_sum: MUX2to1 Port map (
A0 => Sum0,
A1 => Sum1,
Sel => Cin,
MuxOut => Sum
);

MUX_carry: MUX2to1 Port map (

A0 => Cout0,
A1 => Cout1,
Sel => Cin,
MuxOut => Cout
);

end Structural;

TEST BENCH :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tb_CarrySelectAdder16bit is
-- Testbench has no ports
end tb_CarrySelectAdder16bit;

architecture sim of tb_CarrySelectAdder16bit is

-- Component Declaration for the Unit Under Test (UUT)
component CarrySelectAdder16bit
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC
);
end component;

-- Signals to connect to the UUT

signal A : STD_LOGIC_VECTOR(15 downto 0);
signal B : STD_LOGIC_VECTOR(15 downto 0);
signal Cin : STD_LOGIC;
signal Sum : STD_LOGIC_VECTOR(15 downto 0);
signal Cout : STD_LOGIC;

begin
-- Instantiate the Unit Under Test (UUT)
uut: CarrySelectAdder16bit
Port map (
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);

stim_proc: process
begin
-- Test 1: All inputs are zero
A <= (others => '0');
B <= (others => '0');
 Cin <= '0';
wait for 10 ns;

-- Test 2: Simple addition with no carry-in

A <= "0000000000000011"; -- 3
B <= "0000000000000101"; -- 5
Cin <= '0';
wait for 10 ns;

-- Test 3: Simple addition with carry-in

A <= "0000000000000111"; -- 7
B <= "0000000000001001"; -- 9
Cin <= '1';
wait for 10 ns;

-- Test 4: All ones (maximum value)

A <= (others => '1'); -- 65535
B <= (others => '1'); -- 65535
Cin <= '0';
wait for 10 ns;
wait;
end process;
end sim;

RESULT
Thus the outputs of a program implementing 16-bit Carry Select Adder are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 16-bit Carry Select Adder Problems encountered in the designing of
16-bit Carry Select Adder are identified in the study (PO2) are analyzed with Xilinx Vivado
tool (PO5) and results are verified (PO3) through simulation (PO4).
 CARRY SKIP ADDER
BEHAVIOURAL MODEL
Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 3d CARRY SKIP ADDER
DATE:

AIM
To develop the source code for different types of 16 Bit Carry Skip Adder using VHDL and
obtains its Simulation, Synthesis using Behavioral, Structural and Dataflow Modelling.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

PROCEDURE
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM

VHDL SOURCE CODE (BEHAVIOURAL MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity carry_skip_adder is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC
);
end carry_skip_adder;

architecture Behavioral of carry_skip_adder is

signal P : STD_LOGIC_VECTOR(15 downto 0);
signal G : STD_LOGIC_VECTOR(15 downto 0);
signal C : STD_LOGIC_VECTOR(16 downto 0);
begin
C(0) <= Cin;
 DATAFLOW MODEL

Simulation Result

Synthesized Design RTL Analysis

LUT Design
 gen_pro: for i in 0 to 15 generate
P(i) <= A(i) xor B(i);
G(i) <= A(i) and B(i);
end generate;
sum_calc: for i in 0 to 15 generate
Sum(i) <= P(i) xor C(i);
C(i+1) <= G(i) or (P(i) and C(i));
end generate;
Cout <= C(16);
end Behavioral;

VHDL SOURCE CODE (DATAFLOW MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CarrySkipAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input A
B : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input B
Cin : in STD_LOGIC; -- Carry input
Sum : out STD_LOGIC_VECTOR(15 downto 0); -- Sum output
Cout : out STD_LOGIC -- Carry output
);
end CarrySkipAdder16bit;

architecture Dataflow of CarrySkipAdder16bit is

-- Define internal signals
signal P, G : STD_LOGIC_VECTOR(15 downto 0); -- Propagate and Generate signals
signal C : STD_LOGIC_VECTOR(16 downto 0); -- Carry signals

-- Define block size for carry-skip (e.g., 4 bits)

constant BLOCK_SIZE : integer := 4;

begin
-- Propagate and Generate signals
P <= A xor B;
G <= A and B;
 -- Calculate carry signals using dataflow modeling
C(0) <= Cin;
C(1) <= C(0) or G(0);
C(2) <= (C(1) and P(1)) or G(1);
C(3) <= (C(2) and P(2)) or G(2);
C(4) <= (C(3) and P(3)) or G(3);
C(5) <= (C(4) and P(4)) or G(4);
C(6) <= (C(5) and P(5)) or G(5);
C(7) <= (C(6) and P(6)) or G(6);
C(8) <= (C(7) and P(7)) or G(7);
C(9) <= (C(8) and P(8)) or G(8);
C(10) <= (C(9) and P(9)) or G(9);
C(11) <= (C(10) and P(10)) or G(10);
C(12) <= (C(11) and P(11)) or G(11);
C(13) <= (C(12) and P(12)) or G(12);
C(14) <= (C(13) and P(13)) or G(13);
C(15) <= (C(14) and P(14)) or G(14);
C(16) <= (C(15) and P(15)) or G(15);

-- Sum and Carry-out

Sum <= P xor C(15 downto 0);
Cout <= C(16);

end Dataflow;

VHDL SOURCE CODE (STRUCTURAL MODEL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdder is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end FullAdder;
architecture Structural of FullAdder is
begin
Sum <= A xor B xor Cin;
Cout <= (A and B) or (B and Cin) or (Cin and A);
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CarrySkipAdder16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input A
B : in STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input B
Cin : in STD_LOGIC; -- Carry input
Sum : out STD_LOGIC_VECTOR(15 downto 0); -- Sum output
Cout : out STD_LOGIC -- Carry output
);
end CarrySkipAdder16bit;

architecture Structural of CarrySkipAdder16bit is

-- Define internal signals for carry
signal carry : STD_LOGIC_VECTOR(16 downto 0);

-- Component declaration for Full Adder

component FullAdder
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC
);
end component;

begin
-- Instantiate Full Adders
FA0: FullAdder port map (A(0), B(0), Cin, Sum(0), carry(1));
FA1: FullAdder port map (A(1), B(1), carry(1), Sum(1), carry(2));
FA2: FullAdder port map (A(2), B(2), carry(2), Sum(2), carry(3));
FA3: FullAdder port map (A(3), B(3), carry(3), Sum(3), carry(4));
 FA4: FullAdder port map (A(4), B(4), carry(4), Sum(4), carry(5));
FA5: FullAdder port map (A(5), B(5), carry(5), Sum(5), carry(6));
FA6: FullAdder port map (A(6), B(6), carry(6), Sum(6), carry(7));
FA7: FullAdder port map (A(7), B(7), carry(7), Sum(7), carry(8));
FA8: FullAdder port map (A(8), B(8), carry(8), Sum(8), carry(9));
FA9: FullAdder port map (A(9), B(9), carry(9), Sum(9), carry(10));
FA10: FullAdder port map (A(10), B(10), carry(10), Sum(10), carry(11));
FA11: FullAdder port map (A(11), B(11), carry(11), Sum(11), carry(12));
FA12: FullAdder port map (A(12), B(12), carry(12), Sum(12), carry(13));
FA13: FullAdder port map (A(13), B(13), carry(13), Sum(13), carry(14));
FA14: FullAdder port map (A(14), B(14), carry(14), Sum(14), carry(15));
FA15: FullAdder port map (A(15), B(15), carry(15), Sum(15), Cout);

-- Carry-Skip Logic
carry(0) <= Cin;
carry(1) <= carry(0) or (A(0) and B(0));
carry(2) <= carry(1) or (A(1) and B(1));
carry(3) <= carry(2) or (A(2) and B(2));
carry(4) <= carry(3) or (A(3) and B(3));
carry(5) <= carry(4) or (A(4) and B(4));
carry(6) <= carry(5) or (A(5) and B(5));
carry(7) <= carry(6) or (A(6) and B(6));
carry(8) <= carry(7) or (A(7) and B(7));
carry(9) <= carry(8) or (A(8) and B(8));
carry(10) <= carry(9) or (A(9) and B(9));
carry(11) <= carry(10) or (A(10) and B(10));
carry(12) <= carry(11) or (A(11) and B(11));
carry(13) <= carry(12) or (A(12) and B(12));
carry(14) <= carry(13) or (A(13) and B(13));
carry(15) <= carry(14) or (A(14) and B(14));
Cout <= carry(15);

end Structural;

TEST BENCH(VHDL)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity carry_skip_adder_tb is
end carry_skip_adder_tb;
architecture Behavioral of carry_skip_adder_tb is

component carry_skip_adder
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC
);
end component;

signal A : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');

signal B : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal Cin : STD_LOGIC := '0';
signal Sum : STD_LOGIC_VECTOR(15 downto 0);
signal Cout : STD_LOGIC;

begin

uut: carry_skip_adder
Port map (
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);

stim_proc: process
begin

A <= "0000000000000001";
B <= "0000000000000001";
Cin <= '0';
wait for 100 ps;

A <= "1111111111111111";
B <= "0000000000000001";
Cin <= '0';
wait for 100 ps;

A <= "1111111111111111";
B <= "0000000000000001";
Cin <= '1';
wait for 100 ps;

A <= "1010101010101010";
B <= "0101010101010101";
Cin <= '0';
wait for 100 ps;
 A <= "1000000000000000";
B <= "1000000000000000";
Cin <= '1';
wait for 100 ps;

A <= "0001001000110100";
B <= "0100001100100001";
Cin <= '0';
wait for 100 ps;

wait;
end process;

end Behavioral;

RESULT
Thus the outputs of a program implementing 16-bit Carry Skip Adder are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 16-bit Carry Skip Adder Problems encountered in the designing of 16-
bit Carry Skip Adder are identified in the study (PO2) are analyzed with Xilinx Vivado tool
(PO5) and results are verified (PO3) through simulation (PO4).
 BRAUN MULTIPLIER
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 4a DESIGN OF MULTIPLIERS
BRAUN MULTIPLIER
DATE:

AIM
To develop the source code for 4-bit Braun multiplier by using VHDL and obtain the simulation,
synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM

VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BraunMultiplier4bit is
Port (
A : in STD_LOGIC_VECTOR (3 downto 0); -- 4-bit input A
B : in STD_LOGIC_VECTOR (3 downto 0); -- 4-bit input B
Product : out STD_LOGIC_VECTOR (7 downto 0) -- 8-bit product output
);
end BraunMultiplier4bit;

architecture Behavioral of BraunMultiplier4bit is

signal P0, P1, P2, P3 : STD_LOGIC_VECTOR (7 downto 0);
signal S1, S2, S3 : STD_LOGIC_VECTOR (7 downto 0);
signal C1, C2 : STD_LOGIC_VECTOR (7 downto 0);
begin
 P0 <= (A(0) & "0000000") when B(0) = '1' else "00000000";
P1 <= ("0" & A(1) & "000000") when B(1) = '1' else "00000000";
P2 <= ("00" & A(2) & "00000") when B(2) = '1' else "00000000";
P3 <= ("000" & A(3) & "0000") when B(3) = '1' else "00000000";

S1 <= P0 + P1;
S2 <= S1 + P2;
S3 <= S2 + P3;

Product <= S3; -- Final product

end Behavioral;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BraunMultiplier4bit_tb is
end BraunMultiplier4bit_tb;

architecture Behavioral of BraunMultiplier4bit_tb is

component BraunMultiplier4bit
Port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Product : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;

signal A : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');

signal B : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal Product : STD_LOGIC_VECTOR(7 downto 0);

begin
UUT: BraunMultiplier4bit
port map (
 A => A,
B => B,
Product => Product
);

-- Test process
process
begin
-- Test Case 1
A <= "0011"; -- A = 3
B <= "0010"; -- B = 2
wait for 10 ns;

-- Test Case 2
A <= "0101"; -- A = 5
B <= "0011"; -- B = 3
wait for 10 ns;

-- Test Case 3
A <= "1111"; -- A = 15
B <= "1111"; -- B = 15
wait for 10 ns;

-- Test Case 4
A <= "1001"; -- A = 9
B <= "0110"; -- B = 6
wait for 10 ns;
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 4-bit Braun Multiplier are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 4-bit Braun Multiplier Problems encountered in the designing of 4-bit
Braun Multiplier are identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5)
and results are verified (PO3) through simulation (PO4).
 BOOTH MULTIPLIER
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 4b BOOTH MULTIPLIER
DATE:

AIM
To develop the source code for 4-bit Booth multiplier by using VHDL and obtain the simulation,
synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM

VHDL SOURCE CODE

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;

ENTITY BoothMultiplier4bit IS
PORT(A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Product : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END BoothMultiplier4bit;

ARCHITECTURE behavior OF BoothMultiplier4bit IS

BEGIN
PROCESS(A, B)
CONSTANT X_ZEROS : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT Y_ZEROS : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');

VABIABLE q, s, p : STD_LOGIC_VECTOR(7 DOWNTO 0);

VABIABLE var : STD_LOGIC_VECTOR(3 DOWNTO 0);
 BEGIN
q := (OTHERS => '0');
s := (OTHERS => '0');
p := (OTHERS => '0');

IF (A /= X_ZEROS AND B /= Y_ZEROS) THEN

q(8 DOWNTO 5) := A;
q(9) := A(3);
var := (NOT A) + 1;
s(8 DOWNTO 5) := var;
s(9) := NOT(A(3));
p(4 DOWNTO 1) := B;

FOR i IN 1 TO 4 LOOP
IF (p(1 DOWNTO 0) = "01") THEN
p := p + q;
ELSIF (p(1 DOWNTO 0) = "10") THEN
p := p + s;
END IF;
p(8 DOWNTO 0) := p(9 DOWNTO 1);
END LOOP;
END IF;
Product <= p(8 DOWNTO 1);
END PROCESS;
END behavior;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BoothMultiplier4bit_tb is
end BoothMultiplier4bit_tb;

architecture Behavioral of BoothMultiplier4bit_tb is

 -- Component declaration for the Booth Multiplier
component BoothMultiplier4bit
Port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Product : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;

-- Signals to connect to the multiplier

signal A : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal B : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal Product : STD_LOGIC_VECTOR(7 downto 0);

begin
-- Instantiate the Booth Multiplier
UUT: BoothMultiplier4bit
port map (
A => A,
B => B,
Product => Product
);

-- Test process
process
begin
-- Test Case 1: 3 * 2 = 6
A <= "0011"; -- A = 3
B <= "0010"; -- B = 2
wait for 20 ns;

-- Test Case 2: -3 * 2 = -6
A <= "1101"; -- A = -3 (2's complement)
B <= "0010"; -- B = 2
wait for 20 ns;
 -- Test Case 3: -3 * -2 = 6
A <= "1101"; -- A = -3
B <= "1110"; -- B = -2
wait for 20 ns;

-- Test Case 4: 7 * -1 = -7
A <= "0111"; -- A = 7
B <= "1111"; -- B = -1
wait for 20 ns;

-- Finish simulation
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 4-bit Booth Multiplier are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 4-bit Booth Multiplier Problems encountered in the designing of 4-bit
Booth Multiplier are identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5)
and results are verified (PO3) through simulation (PO4).
 BOOTH MULTIPLIER
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 4c WALLACE MULTIPLIER
DATE:

AIM
To develop the source code for 4-bit Wallace multiplier by using VHDL and obtain the simulation,
synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity WallaceTreeMultiplier4bit is
Port (
A : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit multiplicand
B : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit multiplier
Product : out STD_LOGIC_VECTOR(7 downto 0) -- 8-bit product output
);
end WallaceTreeMultiplier4bit;

architecture Behavioral of WallaceTreeMultiplier4bit is

signal partial_products: STD_LOGIC_VECTOR(15 downto 0); -- To store all the partial products
signal sum1, sum2, carry1, carry2: STD_LOGIC_VECTOR(7 downto 0);
begin
-- Generate the partial products
partial_products(3 downto 0) <= A(0) & A(0) & A(0) & A(0) when B(0) = '1' else "0000";
 partial_products(7 downto 4) <= A(1) & A(1) & A(1) & A(1) when B(1) = '1' else "0000";
partial_products(11 downto 8) <= A(2) & A(2) & A(2) & A(2) when B(2) = '1' else "0000";
partial_products(15 downto 12) <= A(3) & A(3) & A(3) & A(3) when B(3) = '1' else "0000";

-- First level of reduction (4-bit adders)

sum1 <= partial_products(3 downto 0) + partial_products(7 downto 4);
carry1 <= (partial_products(3 downto 0) and partial_products(7 downto 4)) or (partial_products(7 downto
4) and sum1(3 downto 0)) or (sum1(3 downto 0) and partial_products(3 downto 0));

sum2 <= partial_products(11 downto 8) + partial_products(15 downto 12);

carry2 <= (partial_products(11 downto 8) and partial_products(15 downto 12)) or (partial_products(15
downto 12) and sum2(3 downto 0)) or (sum2(3 downto 0) and partial_products(11 downto 8));

-- Final addition of reduced results

Product <= sum1 + carry1 + sum2 + carry2;
end Behavioral;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity WallaceTreeMultiplier4bit_tb is
end WallaceTreeMultiplier4bit_tb;

architecture Behavioral of WallaceTreeMultiplier4bit_tb is

-- Component declaration for the Wallace Tree Multiplier
component WallaceTreeMultiplier4bit
Port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Product : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;

-- Signals to connect to the multiplier

signal A : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal B : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal Product : STD_LOGIC_VECTOR(7 downto 0);

begin
-- Instantiate the Wallace Tree Multiplier
UUT: WallaceTreeMultiplier4bit
port map (
A => A,
B => B,
Product => Product
);
 -- Test process
process
begin
-- Test Case 1: 3 * 2 = 6
A <= "0011"; -- A = 3
B <= "0010"; -- B = 2
wait for 20 ns;

-- Test Case 2: 5 * 4 = 20
A <= "0101"; -- A = 5
B <= "0100"; -- B = 4
wait for 20 ns;

-- Test Case 3: 7 * 7 = 49
A <= "0111"; -- A = 7
B <= "0111"; -- B = 7
wait for 20 ns;

-- Test Case 4: 8 * 3 = 24
A <= "1000"; -- A = 8
B <= "0011"; -- B = 3
wait for 20 ns;

-- Test Case 5: 15 * 15 = 225

A <= "1111"; -- A = 15
B <= "1111"; -- B = 15
wait for 20 ns;

-- Finish simulation
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 4-bit Wallace Multiplier are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 4-bit Wallace Multiplier Problems encountered in the designing of 4-
bit Wallace Multiplier are identified in the study (PO2) are analyzed with Xilinx Vivado tool
(PO5) and results are verified (PO3) through simulation (PO4).
 4-BIT ALU
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 5 4-BIT ALU
DATE:

AIM
To develop the source code for 4-bit Arithmetic Logic Unit (ALU) by using VHDL and obtain the
simulation, synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
Port (
A : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit input A
B : in STD_LOGIC_VECTOR(3 downto 0); -- 4-bit input B
Op : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit operation code
Result : out STD_LOGIC_VECTOR(3 downto 0) -- 4-bit result
);
end ALU;

architecture Behavioral of ALU is

begin
process(A, B, Op)
begin
case Op is
when "00" => -- Addition
Result <= A + B;
 when "01" => -- Subtraction
Result <= A - B;
when "10" => -- Complement of A
Result <= NOT A;
when others => -- Default case, return zero
Result <= "0000";
end case;
end process;
end Behavioral;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU_tb is
end ALU_tb;

architecture Behavioral of ALU_tb is

-- Component declaration
component ALU
Port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Op : in STD_LOGIC_VECTOR(1 downto 0);
Result : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;

-- Signals to connect to the ALU

signal A : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal B : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal Op : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal Result : STD_LOGIC_VECTOR(3 downto 0);

begin
-- Instantiate the ALU component
uut: ALU
Port map (
A => A,
B => B,
Op => Op,
Result => Result
);

-- Stimulus process to apply test vectors

stimulus: process
begin
-- Test 1: A = 5 (0101), B = 3 (0011), Op = 00 (Addition)
 A <= "0101";
B <= "0011";
Op <= "00"; -- Add A and B
wait for 100 ps;

-- Test 2: A = 8 (1000), B = 2 (0010), Op = 01 (Subtraction)

A <= "1000";
B <= "0010";
Op <= "01"; -- Subtract B from A
wait for 100 ps;

-- Test 3: A = 7 (0111), Op = 10 (Complement of A)

A <= "0111";
Op <= "10"; -- Complement A
wait for 100 ps;

-- Test 4: Default case (should return 0000)

A <= "0001";
B <= "0011";
Op <= "11"; -- Undefined operation
wait for 100 ps;

-- Stop simulation
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 4-bit Arithmetic Logic Unit (ALU) are
verified by synthesizing and simulating VHDL code. By completing this experiment, students
will gain a deeper understanding of 4-bit Arithmetic Logic Unit (ALU) Problems encountered
in the designing of 4-bit Arithmetic Logic Unit (ALU) are identified in the study (PO2) are
analyzed with Xilinx Vivado tool (PO5) and results are verified (PO3) through simulation
(PO4).
 DESIGN OF REAL TIME CLOCK
BEHAVIOURAL MODEL

Simulation Result

Synthesized Design RTL Analysis

LUT Design
EXP NO: 6 DESIGN OF REAL TIME CLOCK
DATE:

AIM
To develop the source code for Real Time Clock by using VHDL and obtain the simulation,
synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RealTimeClock is
Port (
clk : in STD_LOGIC; -- Clock input
reset : in STD_LOGIC; -- Asynchronous reset
hours : out STD_LOGIC_VECTOR(4 downto 0); -- 5-bit hours (0-23)
minutes : out STD_LOGIC_VECTOR(5 downto 0); -- 6-bit minutes (0-59)
seconds : out STD_LOGIC_VECTOR(5 downto 0) -- 6-bit seconds (0-59)
);
end RealTimeClock;

architecture Behavioral of RealTimeClock is

signal sec_count : STD_LOGIC_VECTOR(5 downto 0) := "000000";
signal min_count : STD_LOGIC_VECTOR(5 downto 0) := "000000";
signal hour_count : STD_LOGIC_VECTOR(4 downto 0) := "00000";
begin
process(clk, reset)
begin
if reset = '1' then
sec_count <= "000000";
min_count <= "000000";
hour_count <= "00000";
elsif rising_edge(clk) then
 -- Increment seconds
if sec_count = "111011" then -- 59 in binary
sec_count <= "000000";
-- Increment minutes
if min_count = "111011" then -- 59 in binary
min_count <= "000000";
-- Increment hours
if hour_count = "10111" then -- 23 in binary
hour_count <= "00000";
else
hour_count <= hour_count + 1;
end if;
else
min_count <= min_count + 1;
end if;
else
sec_count <= sec_count + 1;
end if;
end if;
end process;

-- Assigning to outputs
seconds <= sec_count;
minutes <= min_count;
hours <= hour_count;
end Behavioral;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RealTimeClock_tb is
end RealTimeClock_tb;

architecture Behavioral of RealTimeClock_tb is

-- Component Declaration for the RealTimeClock
component RealTimeClock
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
hours : out STD_LOGIC_VECTOR(4 downto 0);
minutes : out STD_LOGIC_VECTOR(5 downto 0);
seconds : out STD_LOGIC_VECTOR(5 downto 0)
);
end component;
 signal clk : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal hours : STD_LOGIC_VECTOR(4 downto 0);
signal minutes : STD_LOGIC_VECTOR(5 downto 0);
signal seconds : STD_LOGIC_VECTOR(5 downto 0);

begin
-- Instantiate the RealTimeClock
UUT: RealTimeClock
port map (
clk => clk,
reset => reset,
hours => hours,
minutes => minutes,
seconds => seconds
);

-- Clock generation
clk_process : process
begin
while true loop
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end loop;
end process;
process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait for 1 us;
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 4-bit Wallace Multiplier are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 4-bit Wallace Multiplier Problems encountered in the designing of 4-
bit Wallace Multiplier are identified in the study (PO2) are analyzed with Xilinx Vivado tool
(PO5) and results are verified (PO3) through simulation (PO4).
 FPGA IMPLEMENTATION - 8:3 ENCODER
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 7a FPGA IMPLEMENTATION - 8:3 ENCODER
DATE:

AIM
To develop the source code for 8:3 Encoder by using VHDL and obtain the simulation, synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Encoder8to3 is
Port (
data_in : in STD_LOGIC_VECTOR(7 downto 0); -- 8-bit input
data_out : out STD_LOGIC_VECTOR(2 downto 0); -- 3-bit output
valid : out STD_LOGIC -- Output valid signal
);
end Encoder8to3;

architecture Behavioral of Encoder8to3 is

begin
process(data_in)
begin
case data_in is
when "00000001" => data_out <= "000"; valid <= '1';
when "00000010" => data_out <= "001"; valid <= '1';
when "00000100" => data_out <= "010"; valid <= '1';
when "00001000" => data_out <= "011"; valid <= '1';
when "00010000" => data_out <= "100"; valid <= '1';
when "00100000" => data_out <= "101"; valid <= '1';
when "01000000" => data_out <= "110"; valid <= '1';
when "10000000" => data_out <= "111"; valid <= '1';
when others => data_out <= "000"; valid <= '0';
end case;
end process;
end Behavioral;
TEST BENCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_Encoder8to3 is
end tb_Encoder8to3;

architecture Behavioral of tb_Encoder8to3 is

component Encoder8to3
Port (
data_in : in STD_LOGIC_VECTOR(7 downto 0); -- 8-bit input
data_out : out STD_LOGIC_VECTOR(2 downto 0); -- 3-bit output
valid : out STD_LOGIC -- Output valid signal
);
end component;

signal data_in : STD_LOGIC_VECTOR(7 downto 0) := "00000000";

signal data_out : STD_LOGIC_VECTOR(2 downto 0);
signal valid : STD_LOGIC;

begin

uut: Encoder8to3
Port map (
data_in => data_in,
data_out => data_out,
valid => valid
);

stim_proc: process
begin

data_in <= "00000001";

wait for 100 ps;

data_in <= "00000010";

wait for 100 ps;

data_in <= "00000100";

wait for 100 ps;

data_in <= "00001000";

wait for 100 ps;
 data_in <= "00010000";
wait for 100 ps;

data_in <= "00100000";

wait for 100 ps;

data_in <= "01000000";

wait for 100 ps;

data_in <= "10000000";

wait for 100 ps;

wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 8:3 Encoder are verified by synthesizing
and simulating VHDL code. By completing this experiment, students will gain a deeper
understanding of 8:3 Encoder Problems encountered in the designing of 8:3 Encoder are
identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5) and results are verified
(PO3) through simulation (PO4).
 FPGA IMPLEMENTATION - 3:8 DECODER
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 7b FPGA IMPLEMENTATION - 3:8 DECODER
DATE:

AIM
To develop the source code for 3:8 Decoder by using VHDL and obtain the simulation, synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_3to8 is
Port (
input : in STD_LOGIC_VECTOR (2 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0)
);
end decoder_3to8;

architecture Behavioral of decoder_3to8 is

begin
process(input)
begin
output <= (others => '0'); -- Default output to all 0s
case input is
when "000" => output <= "00000001";
when "001" => output <= "00000010";
when "010" => output <= "00000100";
when "011" => output <= "00001000";
when "100" => output <= "00010000";
when "101" => output <= "00100000";
when "110" => output <= "01000000";
when "111" => output <= "10000000";
when others => output <= (others => '0');
end case;

end process;
end Behavioral;
 TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_decoder_3to8 is
end tb_decoder_3to8;

architecture Behavioral of tb_decoder_3to8 is

signal input : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal output : STD_LOGIC_VECTOR (7 downto 0);

-- Instantiate the Unit Under Test (UUT)

component decoder_3to8
Port (
input : in STD_LOGIC_VECTOR (2 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;

begin
-- Instantiate the UUT
uut: decoder_3to8
port map (
input => input,
output => output
);

-- Stimulus process
stim_proc: process
begin
-- Apply each input value and wait for 10 ns
input <= "000"; wait for 100 ps;
input <= "001"; wait for 100 ps;
input <= "010"; wait for 100 ps;
input <= "011"; wait for 100 ps;
input <= "100"; wait for 100 ps;
input <= "101"; wait for 100 ps;
input <= "110"; wait for 100 ps;
input <= "111"; wait for 100 ps;

-- End simulation
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 3:8 Decoder are verified by synthesizing
and simulating VHDL code. By completing this experiment, students will gain a deeper
understanding of 3:8 Decoder Problems encountered in the designing of 3:8 Decoder are
identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5) and results are verified
(PO3) through simulation (PO4).
 FPGA IMPLEMENTATION - D FLIP FLOP
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 8a FPGA IMPLEMENTATION – D FLIP FLOP
DATE:

AIM
To develop the source code for D Flip Flop by using VHDL and obtain the simulation, synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_flip_flop is
Port (
clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC
);
end d_flip_flop;

architecture Behavioral of d_flip_flop is

begin
process(clk,D)
begin
if rising_edge(clk) then
Q <= D;
end if;
end process;
end Behavioral;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_d_flip_flop is
end tb_d_flip_flop;
 architecture Behavioral of tb_d_flip_flop is
signal clk : STD_LOGIC := '0';
signal D : STD_LOGIC := '0';
signal Q : STD_LOGIC;

component d_flip_flop
Port (
clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;

begin
uut: d_flip_flop
port map (
clk => clk,
D => D,
Q => Q
);
clk_process :process
begin
clk <= '1';
wait for 100 ps;
clk <= '0';
wait for 100 ps;
end process;
stim_proc: process
begin
D <= '1'; wait for 80 ps;
D <= '0'; wait for 80 ps;
D <= '1'; wait for 80 ps;
D <= '0'; wait for 80 ps;
D <= '1'; wait for 80 ps;
D <= '0'; wait for 80 ps;
D <= '1'; wait for 80 ps;
D <= '0'; wait for 80 ps;
wait;
end process;
end Behavioral

RESULT
Thus the outputs of a program implementing D Flip Flop are verified by synthesizing
and simulating VHDL code. By completing this experiment, students will gain a deeper
understanding of D Flip Flop Problems encountered in the designing of D Flip Flop are
identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5) and results are verified
(PO3) through simulation (PO4).
 4-BIT COUNTER
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis

Synthesized Design LUT Design

EXP NO: 8b FPGA IMPLEMENTATION – 4-BIT COUNTER
DATE:

AIM
To develop the source code for 4-Bit Counter by using VHDL and obtain the simulation, synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_4bit is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0)
);
end counter_4bit;

architecture Behavioral of counter_4bit is

signal count : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
process(clk, rst)
begin
if rst = '1' then
count <= "0000";
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

q <= count;
end Behavioral;
TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_counter_4bit is
end tb_counter_4bit;

architecture Behavioral of tb_counter_4bit is

signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC := '0';
signal q : STD_LOGIC_VECTOR(3 downto 0);

-- Instantiate the Unit Under Test (UUT)

component counter_4bit
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

begin
-- Instantiate the UUT
uut: counter_4bit
port map (
clk => clk,
rst => rst,
q => q
);

-- Clock process
clk_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- Apply reset
rst <= '1';
wait for 20 ns;
rst <= '0';
wait for 100 ns;

-- Apply reset again

rst <= '1';
wait for 20 ns;
rst <= '0';
 wait for 100 ns;

-- End simulation
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 4-Bit Counter are verified by synthesizing
and simulating VHDL code. By completing this experiment, students will gain a deeper
understanding of 4-Bit Counter Problems encountered in the designing of 4-Bit Counter are
identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5) and results are verified
(PO3) through simulation (PO4).
FPGA IMPLEMENTATION – 2-BIT COMPARATOR
BEHAVIOURAL MODEL

Simulation Result

RTL Analysis
EXP NO: 9a FPGA IMPLEMENTATION – 2-BIT COMPARATOR
DATE:

AIM
To develop the source code for 2-Bit Comparator by using VHDL and obtain the simulation,
synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator_2bit is
Port (
A : in STD_LOGIC_VECTOR (1 downto 0);
B : in STD_LOGIC_VECTOR (1 downto 0);
A_eq_B: out STD_LOGIC;
A_gt_B: out STD_LOGIC;
A_lt_B: out STD_LOGIC
);
end comparator_2bit;

architecture Gate_Level of comparator_2bit is

signal A0_and_B0_not, A1_and_B1_not, A0_not_and_B0, A1_not_and_B1: STD_LOGIC;
begin
-- A_eq_B = (A1 == B1) and (A0 == B0)
A_eq_B <= (not(A(1) xor B(1))) and (not(A(0) xor B(0)));

-- A_gt_B = A1 & ~B1 | (A1 == B1) & A0 & ~B0

A1_and_B1_not <= A(1) and not(B(1));
A0_and_B0_not <= A(0) and not(B(0));
A_gt_B <= A1_and_B1_not or ((not(A(1) xor B(1))) and A0_and_B0_not);

-- A_lt_B = B1 & ~A1 | (A1 == B1) & B0 & ~A0

A1_not_and_B1 <= not(A(1)) and B(1);
A0_not_and_B0 <= not(A(0)) and B(0);
A_lt_B <= A1_not_and_B1 or ((not(A(1) xor B(1))) and A0_not_and_B0);
Synthesized Design LUT Design
end Gate_Level;

TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_comparator_2bit is
end tb_comparator_2bit;

architecture Behavioral of tb_comparator_2bit is

signal A : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal B : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal A_eq_B: STD_LOGIC;
signal A_gt_B: STD_LOGIC;
signal A_lt_B: STD_LOGIC;

-- Instantiate the Unit Under Test (UUT)

component comparator_2bit
Port (
A : in STD_LOGIC_VECTOR (1 downto 0);
B : in STD_LOGIC_VECTOR (1 downto 0);
A_eq_B: out STD_LOGIC;
A_gt_B: out STD_LOGIC;
A_lt_B: out STD_LOGIC
);
end component;

begin
-- Instantiate the UUT
uut: comparator_2bit
port map (
A => A,
B => B,
A_eq_B=> A_eq_B,
A_gt_B=> A_gt_B,
A_lt_B=> A_lt_B
);

-- Stimulus process
stim_proc: process
begin
-- Test case 1: A = 00, B = 00
A <= "00"; B <= "00"; wait for 20 ns;

-- Test case 2: A = 01, B = 00

A <= "01"; B <= "00"; wait for 20 ns;

-- Test case 3: A = 00, B = 01

A <= "00"; B <= "01"; wait for 20 ns;
 -- Test case 4: A = 11, B = 10
A <= "11"; B <= "10"; wait for 20 ns;

-- Test case 5: A = 10, B = 11

A <= "10"; B <= "11"; wait for 20 ns;

-- Test case 6: A = 11, B = 11

A <= "11"; B <= "11"; wait for 20 ns;

-- End simulation
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing 2-Bit Comparator are verified by
synthesizing and simulating VHDL code. By completing this experiment, students will gain a
deeper understanding of 2-Bit Comparator Problems encountered in the designing of 2-Bit
Comparator are identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5) and
results are verified (PO3) through simulation (PO4).
 SHIFT REGISTER

Simulation Result

RTL Analysis
EXP NO: 9b FPGA IMPLEMENTATION – SHIFT REGISTER
DATE:

AIM
To develop the source code for Shift Register by using VHDL and obtain the simulation, synthesis.

SOFTWARE REQUIREMENT
Xilinx Vivado 2023.1.1 Software

ALGORITHM
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VHDL.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

PROGRAM
VHDL SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_register is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
d_in : in STD_LOGIC;
q_out : out STD_LOGIC_VECTOR (3 downto 0)
);
end shift_register;

architecture Gate_Level of shift_register is

signal q : STD_LOGIC_VECTOR(3 downto 0);
begin
-- D flip-flop with reset (using gates)
process(clk, rst)
begin
if rst = '1' then
q <= "0000";
elsif rising_edge(clk) then
q(3) <= q(2);
q(2) <= q(1);
q(1) <= q(0);
q(0) <= d_in;
end if;
end process;
q_out <= q;
end Gate_Level;
Synthesized Design

LUT Design
TEST BENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_shift_register is
end tb_shift_register;

architecture Behavioral of tb_shift_register is

signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC := '0';
signal d_in : STD_LOGIC := '0';
signal q_out : STD_LOGIC_VECTOR(3 downto 0);

-- Instantiate the Unit Under Test (UUT)

component shift_register
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
d_in : in STD_LOGIC;
q_out : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

begin
-- Instantiate the UUT
uut: shift_register
port map (
clk => clk,
rst => rst,
d_in => d_in,
q_out => q_out
);

-- Clock process
clk_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- Apply reset
rst <= '1';
wait for 20 ns;
rst <= '0';
wait for 20 ns;

-- Apply inputs to shift into the register

 d_in <= '1'; wait for 20 ns;
d_in <= '0'; wait for 20 ns;
d_in <= '1'; wait for 20 ns;
d_in <= '1'; wait for 20 ns;
d_in <= '0'; wait for 20 ns;

-- Reset again
rst <= '1';
wait for 20 ns;
rst <= '0';

-- End simulation
wait;
end process;
end Behavioral;

RESULT
Thus the outputs of a program implementing Shift Register are verified by synthesizing
and simulating VHDL code. By completing this experiment, students will gain a deeper
understanding of Shift Register Problems encountered in the designing of Shift Register are
identified in the study (PO2) are analyzed with Xilinx Vivado tool (PO5) and results are verified
(PO3) through simulation (PO4).