Understanding Minimum Pulse Width

 Pulse Width is the duration of time for which the

clock will stay stable in a particular state

In a digital design, clocks must have a minimum pulse
width for proper operation of the design
 It is defined for both high and low levels of the clock
The pulse width is measured from the point where the amplitude
is 50% of the final value

Minimum Minimum
pulse width pulse width
high low
VDD

VDD/2 Pulse width Pulse width

high low

Ph: 080-40788574 www.rv-vlsi.com 51

E-mail: [email protected] RV-VLSI Confidential
Understanding No-change Timing
 No-change timing checks are required to check the timing requirement on
certain pins of level sensitive elements such as latches.
 A no-change timing check, checks whether a constrained signal stays
stable around a level-sensitive related signal
 Example: Enable signal of a latch should stay stable for a certain
duration of time around active clock level

Constrained signal

Related signal

Ph: 080-40788574 www.rv-vlsi.com 52

E-mail: [email protected] RV-VLSI Confidential
Timing Arcs
 A segment or component of a timing path that may contribute to the
delay in signal propagation along the path is represented by a timing
arc. A timing arc specifies a timing relationship between pins of logic
elements
IN1

A Y A Y
IN2 D Q D Q OUT
B
FF1 A1
B2
FF2

CLK

 Each arrow on the schematic represents a timing arc

 BY of AND gate A1 is a timing arc that defines the delay from pin B to pin Y
of AND gate
 Pin Y of A1 to pin A of B2 is also a timing arc that defines the delay of the net
connecting the pins Y of A1 and A of B2
Ph: 080-40788574 www.rv-vlsi.com 53
E-mail: [email protected] RV-VLSI Confidential
Timing Arcs (cont.)
 Any timing information which influences the timing of a path
is provided to STA tool through a timing arc.
 This information is used by STA tool for traversing through a
timing path and computing delays.
 There are two types of Timing arcs
 Delay arc
 cell delay arc
 net delay arc
 Constraint arc
 Each cell can have multiple delay or constraint arcs

Ph: 080-40788574 www.rv-vlsi.com 54

E-mail: [email protected] RV-VLSI Confidential
Understanding Cell Delay Arcs
 Cell delay arcs represent the propagation delay
between an input and output pin of a cell. For
example,
 Propagation delay, from A → Y for a buffer
 CLK → Q delay for a flip-flop
IN1

A Y A Y
IN2 D Q D Q OUT
B
FF1 A1
B2
FF2

CLK

Ph: 080-40788574 www.rv-vlsi.com 55

E-mail: [email protected] RV-VLSI Confidential
Cell Delay Arcs for a NOT Gate

Pin Related pin Timing arc Related pin specifies the

pin from which
Y Rise time tR
timing is calculated.
Fall time tF
A Propagation delay low to high tPLH
A Propagation delay high to low tPHL

A NOT gate has four timing arcs associated with it

Ph: 080-40788574 www.rv-vlsi.com 56

E-mail: [email protected] RV-VLSI Confidential
Delay Arcs for a NOT Gate (cont.)

 Each of these timing arcs are represented as separate

delay tables in the Liberty file as shown
tR at Y tF at Y
Slew Load at Y Slew Load at Y
at A at A
1pF 2pF 1pF 2pF
10ps 10ps 20ps 10ps 11ps 21ps
20ps 20ps 30ps 20ps 22ps 32ps

tPLH at Y tPHL at Y
Slew Load at Y Slew Load at Y
at A at A
1pF 2pF 1pF 2pF
10ps 40ps 50ps 10ps 42ps 53ps
20ps 50ps 60ps 20ps 51ps 61ps
Ph: 080-40788574 www.rv-vlsi.com 57
E-mail: [email protected] RV-VLSI Confidential
Delay Arcs for a 2 Input NAND Gate

 Timing arcs for a 2 input NAND gate are shown

below
Pin Related pin Timing arc
Y Rise time tR
Fall time tF
A Propagation delay low to high tPLH
A Propagation delay high to low tPHL
B Propagation delay low to high tPLH
B Propagation delay high to low tPHL

A two input NAND gate has six timing arcs associated with it

Ph: 080-40788574 www.rv-vlsi.com 58

E-mail: [email protected] RV-VLSI Confidential
Delay Arcs for a Flip-flop
 Delay arcs for a flip-flop
Pin Related Timing arc
D Q
pin
Q Rise time tR
Fall time tF D Flip-flop
CK
CK Propagation delay low to high tPLH
Propagation delay high to low tPHL

Note: There is no timing

arc between D and Q pins
of a flip-flop!!!

Ph: 080-40788574 www.rv-vlsi.com 59

E-mail: [email protected] RV-VLSI Confidential
Understanding Net delay Arcs

 Net delay arcs represent the delay due to a net.

 The net delay arc represents delay from OUT to IN2

Ph: 080-40788574 www.rv-vlsi.com

E-mail: [email protected] RV-VLSI Confidential
Understanding Constraint Arcs
 Constraint arcs are associated with sequential cells
only
 It is defined for an input pin or between input pins
 Setup and Hold arcs are examples of constraint arcs defined
between input pins of a flip-flop
 Minimum pulse width arc is an example of constraint arc
defined on a input pin of a flip-flop

D Q
Setup or
Hold
D Flip-flop
timing
arc CK

Ph: 080-40788574 www.rv-vlsi.com 61

E-mail: [email protected] RV-VLSI Confidential
Delay and Constraint Arcs for a Flip-flop
 Below table lists all the arcs for a flip-flop
Pin Related pin Timing arc
D Q
CK Minimum pulse width high tWH
Minimum pulse width low tWL
D Flip-flop
D CK Setup when D is rising CK
Setup when D is falling
Hold when D is rising
Hold when D is falling
Q Rise time tR Constraint arc CK → D
Delay arc CK → Q
Fall time tF

CK Propagation delay low to high tPLH

Propagation delay high to low tPHL

For the flip-flop shown there are ten timing arcs

Ph: 080-40788574 www.rv-vlsi.com 62
E-mail: [email protected] RV-VLSI Confidential
Understanding Timing Arcs
IN1

A Y A Y
IN2 D Q D Q OUT
B
FF1 A1
B2
FF2

CLK

Cell delay arc

Net delay arc

Constraint arc

Ph: 080-40788574 www.rv-vlsi.com 63

E-mail: [email protected] RV-VLSI Confidential
Understanding Timing Paths
 In a digital design the data moves from the input-to-
output ports through series of sequential and/or
combinational elements.
 Data moves from one sequential element to the next in a
lockstep at every clock edge.
 For the design to work as expected, we need to ensure that the data
from each of the sequential element reaches the next element within
a given time i.e., within a clock period or else it will result in data
being overwritten.
 In the case of combinational logic, data from the input ports
should reach the output ports in a specified time defined by
the timing constraints.
 STA analyzes these timing requirements in parallel or
concurrently by identifying paths
Ph: 080-40788574 www.rv-vlsi.com 64
E-mail: [email protected] RV-VLSI Confidential
Understanding Timing Paths (cont.)
 A timing path exists between two points in a design if
timing arcs exist between them. STA tools classify timing
paths into four types:
 From one flip-flop to another flip-flop (register-to-register
path)
 From an input port to an output port
 From an input port to a flip-flop
 From a flip-flop to an output port
 Each path has certain valid start and end points which
STA tools use to analyze timing on the paths
 Valid start points are: Input ports, Clock pin of sequential cell
 Valid end points are: Output ports, Data pin of sequential cell
Example of ports and pins are shown in the next slide
Ph: 080-40788574 www.rv-vlsi.com 65
E-mail: [email protected] RV-VLSI Confidential
 Understanding Timing Paths (cont.)
Input
Types of timing paths in a Digital Design
port Pin
Combo Combo
logic logic

Output
port

Combo
logic

 4 types of timing paths are

 Path1: register-to-register (reg-to-reg)
 Path2: input-port-to-register (input-to-reg)
 Path3: register-to-output-port (reg-to-output)
 Path4: input-port-to-output-port (input-to-output)
Ph: 080-40788574 www.rv-vlsi.com 66
E-mail: [email protected] RV-VLSI Confidential
 Terminologies Related to Timing Paths
Delay of each gate =
100ps

Constraint:
Maximum delay from
Input-port-to-output-port
 Critical path must be less than 400ps

 A timing path that fails to meet the timing constraint by largest

margin in a design is called critical path. If all timing paths are
meeting the constraints, then the path that is closest to failing is
called critical path.
 Critical path determines the maximum frequency of operation of a
design
 For the circuit shown, delay A  Y = 500ps, B  Y = 400ps and C  Y =
100ps. As A  Y delay is the Critical Path for the circuit as it failing by
largest margin of 400-500 = -100ps.
Ph: 080-40788574 www.rv-vlsi.com
E-mail: [email protected] RV-VLSI Confidential
 Terminologies Related to Timing Paths
(cont.)
 Arrival time
 The time elapsed for a signal to arrive at a certain point is known as arrival time.
 For the circuit shown, Arrival Time at the output pin of I1 is 100ps and Arrival
time for pin Y is 500ps, given pin A as startpoint.
 Required time
 The latest time by which a signal should arrive at a certain point is known as
required time.
 For the circuit shown, Required time at pin Y is 400ps
 Slack
 The difference between the Required time and the Arrival time is called slack.
 For the circuit shown, slack at pin Y = Required time – Arrival time = 400 –
500 = -100ps
 A positive slack indicates timing met, while a negative slack indicates timing violated by the
amount of the slack.

Ph: 080-40788574 www.rv-vlsi.com 68

E-mail: [email protected] RV-VLSI Confidential
 Terminologies Related to Timing Paths (cont.)
 FF1 is launching the data that will be captured by FF2. Hence, FF1 is called
the Launching flip-flop and FF2 is called the Capturing flip-flop.
 Launch clock
 Clock connected to a launching flip-flop is called launch clock
 Capture clock
 Clock connected to a capturing flip-flop is called capture clock
CLK1 is the Launch clock and
The flip-flops share a common clock
CLK2 is the Capture clock in
CLK1. Hence, CLK1 is both Launch
this example.
and Capture clock in this example.

D FF1 FF2 D FF1 FF2

CLK1

CLK1 CLK2

Ph: 080-40788574 www.rv-vlsi.com 69

E-mail: [email protected] RV-VLSI Confidential
 Terminologies Related to Timing Paths (cont.)
 Clock path or Capture path
 Clock path is the path starting from common point of clock network
(between launch and capture sequential cells) to the clock pin of
capturing sequential cell.
 Data path or Launch path
 Data path is the path starting from common point of clock network
(between launch and capture sequential cells) to the data pin of
capturing sequential cell.

Design
FF1 FF2
Data path

DIN D Q A Y D Q
B1
CK CK
CLK B2
Clock path
Ph: 080-40788574 www.rv-vlsi.com 70
E-mail: [email protected] RV-VLSI Confidential
 Terminologies Related to Timing Paths (cont.)
 Virtual clock.

BLK1 BLK2 BLK3

B1 B2 B3
Y D Q D Q OUT A Y D Q
D Q A A Y
A Y IN
FF3 B1 FF_o
FF_i FF2

clk1 clkL clkC

clk2

Design

clk1 must be synchronous with clkL and

clk2 must be synchronous with clkC.
Input delay at port IN = [CK  Q delay of FF_i] + [A  Y delay of B1]
Output delay at port OUT = [A  Y delay of B3] + [Setup time of FF_o]
Ph: 080-40788574 www.rv-vlsi.com 71
E-mail: [email protected] RV-VLSI Confidential
Summary
 In this session, you have learnt:
 The Timing Concepts needed to perform Static
Timing Analysis
 The concepts used in STA such as, type of Delays,
Timing Arcs and Timing Paths
 The terminologies related to timing paths and their
usage

Ph: 080-40788574 www.rv-vlsi.com 72

E-mail: [email protected] RV-VLSI Confidential
Assessments

Ph: 080-40788574 www.rv-vlsi.com 73

E-mail: [email protected] RV-VLSI Confidential
E-learning Practice labs

Ph: 080-40788574 www.rv-vlsi.com 74

E-mail: [email protected] RV-VLSI Confidential
3.0 Estimating path delays for
combinational and sequential paths

75
Topic Objectives
 After the completion of this topic you will be
able to
 Perform the timing analysis of combinational and
sequential paths and estimate the path delays.
 Describe path groups
 List inputs and outputs for a typical STA flow and
describe their role in STA

Ph: 080-40788574 www.rv-vlsi.com 76

E-mail: [email protected] RV-VLSI Confidential
 3.1 Delay Calculation for
Combinational Circuits – NOT gate
 The cell delay is not constant and depends on
A → Y Delay table
many factors
Slew Load at Y
Slew of the
at A
signal at A
1pF 2pF
10ps 40ps 50ps
inv1x 20ps 50ps 60ps
Load at Assume tPLH = tPHL
pin Y
 From the delay table, it is clear that the cell
delay of this inverter is between 40ps and 60ps
for input slew range of 10ps to 20ps and output
load range of 1pF to 2pF
Ph: 080-40788574 www.rv-vlsi.com 77
E-mail: [email protected] RV-VLSI Confidential
Delay Calculation – NOT gate (cont.)
 For scenarios within the range (for example, input slew of
15ps), STA uses interpolation to estimate the delay
 For scenarios out of the range (for example, input slew of
25ps), STA uses extrapolation (not accurate and must be
avoided).

Ph: 080-40788574 www.rv-vlsi.com 78

E-mail: [email protected] RV-VLSI Confidential
 Hot-spot: Calculating Gate Delay using
Interpolation
 Can you find out what would be the
corresponding delay for 2pF load?
20ps  Pop-up Answer: 55ps

15ps
Slew
→

10ps

40ps 45ps 50ps 60ps

Delay →

Use this content for hot-spot in previous slide

Note to e-learning vendor: Use a scale of

20 equal divisions between 40ps and 60ps
(x-axis).
Use 10 equal divisions between 10ps and
20ps (y-axis)
Ph: 080-40788574 www.rv-vlsi.com 79
E-mail: [email protected] RV-VLSI Confidential
 Hot-spot: Calculating Gate Delay using
Extrapolation

25ps

20ps
Slew →

10ps

40ps 50ps 55ps 60ps

Delay →

Note to e-learning vendor: Use a scale of

20 equal divisions between 40ps and 60ps
(x-axis).
Use 10 equal divisions between 10ps and
20ps (y-axis)
Ph: 080-40788574 www.rv-vlsi.com 80
E-mail: [email protected] RV-VLSI Confidential
Slew Calculation – NOT gate
Slew of the Slew Table
Slew for Yat Y
Load
signal at A
at A
1pF 2pF
10ps 10ps 20ps
inv1x 20ps 20ps 30ps
Load at Assume tR = tF
pin Y Capacitance at pin A = 1pF

Ph: 080-40788574 www.rv-vlsi.com 81

E-mail: [email protected] RV-VLSI Confidential
Estimating Path Delay for Combinational Circuits
Delay table
Slew Load at Y
at A
inv1x inv1x
1pF 2pF
10ps 40ps 50ps
Specifications Input pin capacitance
20ps 50ps 60ps
Slew at IN = 10ps (I1 and I2) = 1pF
Load at OUT (C1) = 2pF
 Estimating the path delay between IN and OUT
 To find the delay between IN and OUT, we need to add the propagation
delays of I1 and I2

Ph: 080-40788574 www.rv-vlsi.com 82

E-mail: [email protected] RV-VLSI Confidential
Estimating Path Delay for Combinational
Circuits (cont.)
• To determine the propagation delay of I1 we need to
know
• Slew at IN or A of I1 - is 10ps as per specification
• Load at Y of I1 – is the pin capacitance at pin A of I2 = 1pF as
given in the specification
• Cell delay of I1 –can be determined by parsing the delay table of
the Inverter
• To determine the propagation delay of I2 we need to
know
• Slew at A of I2 – derive this from the slew table of the NOT gate,
• Load at Y or OUT of I2 is 2pF as per the specification
• Cell delay of I2 can be determined by parsing the delay table of
the Inverter

Ph: 080-40788574 www.rv-vlsi.com 83

E-mail: [email protected] RV-VLSI Confidential
Estimating Path Delay for Combinational
Circuits (cont.)
 For NOT gate I1, input slew is 10ps, and output load is input cap of I2
which is 1pF
 Step 1 (find the cell delay of I1): From the delay table, delay at
node INT or output of I1 = 40ps.
 Step 2 (find the slew at Y of I1): From the slew table, slew at
node INT = 10ps
 For I2, input slew at A of I2 (interconnect parasitics are not
considered here) is 10ps and load at Y is 2pF
 Step 3 (find the cell delay of I2): From the delay table, delay at
node OUT = 50ps
 Step 4 (find the slew at Y of I2): From the slew table, slew at
node OUT = 20ps
 Step 5: Overall delay from IN to OUT is = 40 + 50 = 90ps

Ph: 080-40788574 www.rv-vlsi.com 84

E-mail: [email protected] RV-VLSI Confidential
3.2 Delay Calculation for
Sequential Circuits

Ph: 080-40788574 www.rv-vlsi.com 85

E-mail: [email protected] RV-VLSI Confidential
 Steps for Analyzing a Timing Path having
sequential cells
 Step 1: Determine the timing path type and identify the startpoint and endpoint for
the path
 Valid start points are: Input ports of blocks, Clock pins of sequential cells
 Valid end points are: Output ports of blocks, Data pin of sequential cells
 Step 2: Determine the timing analysis setup or hold
 Setup analysis for pre-layout STA, both Setup and Hold analysis for post-
layout STA etc.
 Step 3: List the cells and their corresponding timing arcs in the launch path
 Step 4: Add delays corresponding to each of the timing arcs in the launch path
that contribute to Arrival Time (AT) to form an expression
 Refer to slides in section "Understanding Delay Calculation"
 Step 5: List the cells and their corresponding timing arcs in the capture path
 Step 6: Add delays corresponding to each of the timing arcs in the capture path
that contribute to Required Time (RT) to form an expression
 Step 7: Compute AT and RT by substituting timing arc delays from Liberty file in
AT and RT expressions and determine slack
Ph: 080-40788574 www.rv-vlsi.com 86
E-mail: [email protected] RV-VLSI Confidential
Case Study: Analysis of reg-to-reg Path for
Setup Time
 Compute the setup slack for the circuit Setup analysis is
FF1 Endpoint FF2 always done for
Startpoint
the capturing
D Q A Y D flip-flop, FF2 in
B1 Q
this case
CK CK
CLK

Valid start points are: Input ports of blocks, Clock pins of sequential cells
Valid end points are: Output ports of blocks, Data pin of sequential cells

 Step 1: Determine the timing path type and identify the startpoint and
endpoint for the path
 The timing path is of type reg-to-reg path
 Startpoint: FF1/CK (Clock pin of sequential cell)
Endpoint: FF2/D (Data pin of sequential cell)

Ph: 080-40788574 www.rv-vlsi.com 87

E-mail: [email protected] RV-VLSI Confidential
Analysis of reg-to-reg Path for
Setup Time (cont.)
FF1 FF2

D Q A Y D
B1 Q
CK CK
CLK

 Step 2: Determine the type of analysis needed (setup, hold etc.)

 From the problem statement, type of analysis is: Setup
analysis

Ph: 080-40788574 www.rv-vlsi.com 88

E-mail: [email protected] RV-VLSI Confidential
 Analysis of reg-to-reg Path for
Setup Time (cont.)
FF1 Launch path FF2

D Q A Y D
B1 Q
CK CK
CLK
A Y
C1

 Step 3: List the cells and corresponding timing arcs in the launch
path
 (CK → Q) of FF1
 (A → Y) of B1
 Step 4: Add all the timing arcs in the launch path that contribute to Arrival
Time (AT) to form a expression
 Arrival time (AT) = (CK → Q) of FF1 + (A → Y) of B1

Ph: 080-40788574 www.rv-vlsi.com 89

E-mail: [email protected] RV-VLSI Confidential
Analysis of reg-to-reg Path for
Setup Time (cont.)
Below waveform shows launch path delays marked on the clock waveform

CK → Q delay A → Y delay
of FF1 of B1

Clock Period

FF1 initiates
data transfer
from D to Q

Ph: 080-40788574 www.rv-vlsi.com 90

E-mail: [email protected] RV-VLSI Confidential
Analysis of reg-to-reg Path for
Setup Time (cont.)
FF1 FF2

D Q A Y D
B1 Q
CK CK
CLK

Capture path

 Step 5: List the cells and corresponding timing arcs in the capture path
 Setup of FF2
 Step 6: Compute Required Time (RT) using timing arc delays from Step 5
 Required time (RT) = CLK Period – Setup time of FF2
 Note that FF2 captures the data from FF1 in next clock cycle

Ph: 080-40788574 www.rv-vlsi.com 91

E-mail: [email protected] RV-VLSI Confidential
Analysis of reg-to-reg Path for
Setup Time (cont.)
Waveform shows delays from launch path, data path and setup slack
marked on the clock
CK → Q delay A → Y delay setup time
of FF1 of B1 of FF2

setup
slack

Clock Period
FF1 initiates
FF2 can capture data if data is
data transfer
available before this time point
from D to Q
 Step 7: Compute AT and RT by substituting timing arc delays from Liberty
file in AT and RT expressions and determine slack as RT-AT
 Setup slack = Required time (RT) - Arrival time (AT)
 Setup slack = [ [Period of CLK – Setup time of FF2] - (CK → Q) of
FF1 + (A → Y) of B1]
 If setup slack is positive setup is met or setup time is met
Ph: 080-40788574 www.rv-vlsi.com 92
E-mail: [email protected] RV-VLSI Confidential
Calculating Setup Slack in reg-to-reg path:
An Example
Combo
delay
CK → Q = 1ns
D FF1 Q 3ns D FF2 Q Setup time = 0.5ns
Din
CK → Q setup time CLK Period = 6ns

CK CK

CLK Launch at t = 0 capture at t = CLK period

Setup
time

CLK → Q Combo
0 delay Slack 6ns

Arrival time (AT) = (CLK → Q delay) + (Combo delay) = 1 + 3 = 4ns

Required time (RT) = (Clock period) – (Setup time FF2) = 6 – 0.5 = 5.5ns
Slack = RT - AT = 5.5 – 4 = 1.5ns
Combinational logic is also referred as Combo Logic.
Ph: 080-40788574 www.rv-vlsi.com 93
E-mail: [email protected] RV-VLSI Confidential
Timing diagram for Setup Time

Combinational Combinational
Delay Delay

Setup time Setup time Setup time

for FF1 for FF2 for FF3
CLK

Ph: 080-40788574 www.rv-vlsi.com 94

E-mail: [email protected] RV-VLSI Confidential
Case Study: Analysis of reg-to-reg Path for
Hold Time
 At any rising edge of the clock, both FF1 and FF2 will capture
data at their respective D pins and transfer it to their Q pin
 Hold time violation occurs if the flip-flop FF2 gets new data from
FF1, before latching the existing data that is present at its input
from previous clock cycle.
 For the data to be successfully latched, the flip-flop FF2 takes a
finite amount of time. Hence, if the data at its input is overwritten,
data is lost.

D0
FF1 FF2 Hold analysis is
D1 always done for
D Q A Y D Q the capturing
B1
flip-flop, FF2 in
CK CK this case
CLK
Ph: 080-40788574 www.rv-vlsi.com 95
E-mail: [email protected] RV-VLSI Confidential
Case Study: Analysis of reg-to-reg Path for
Hold Time (cont.)
 From the waveform, at the rising clock edge 0ns, FF1 is
processing data D1 present at its input and FF2 is processing
data D0. Flip-flop FF2, should not get data D1 before it has
processed D0, the time it needs to process D0 is its hold time
 Hence to meet hold time requirement for FF2,
 Arrival time (AT) - Required time (RT)= Hold slack > 0
 AT = (CK → Q delay of FF1) + (A → Y delay of B1)
 RT = Hold time of FF2

Ph: 080-40788574 www.rv-vlsi.com 96

E-mail: [email protected] RV-VLSI Confidential
Case Study: Analysis of reg-to-reg Path for
Hold Time (cont.)
hold time
of FF2 hold slack

CK → Q delay A → Y delay
of FF1 of B1

Clock Period
0ns

FF1 initiates transfer of data bit D1

FF2 initiates transfer of data bit D0

Ph: 080-40788574 www.rv-vlsi.com 97

E-mail: [email protected] RV-VLSI Confidential
Calculating Hold Slack in reg-to-reg path:
An Example

CLK → Q = 1ns
FF1 3ns FF2
D Hold time = 0.5ns
CLK → Q hold time CLK Period = 6ns

CLK

Hold Slack
time
CLK → Q Combo
0 delay 6ns

Arrival time (AT) = (CLK → Q delay) + (Combo delay) = 1 + 3 = 4ns

Required time (RT) = (Hold time FF2) = 0.5
Slack = AT - RT = 4 – 0.5 = 3.5ns
Combinational Logic is also referred as combo logic.
Ph: 080-40788574 www.rv-vlsi.com 98
E-mail: [email protected] RV-VLSI Confidential
Understanding Metastability
 When the set-up or hold time of a flip-flop is
violated, the flip-flop enters into a state called
Metastable state. In this state, it’s output
oscillates between high and low for an unknown
duration of time before settling into a final state
 Engineers spend a major chunk of their time to
meet set-up and hold time requirements and
overcome metastability in the design!

Ph: 080-40788574 www.rv-vlsi.com 99

E-mail: [email protected] RV-VLSI Confidential
Understanding Input and Output delay
BLK1
B1 B2
D Q A Y D Q
A Y IN
FF_i FF2
CK CK

clkE clkL BLK2

Design
CLK

 Input delay
 Setup slack = RT – AT
= [Clock period - (setup time of FF2)]- [(CK → Q delay of FF_i) + (A →
Y delay of B1) + (A → Y delay of B2)]
(CK → Q delay of FF_i) + (A → Y delay of B1) constitute the Input
delay.
Ph: 080-40788574 www.rv-vlsi.com 100
E-mail: [email protected] RV-VLSI Confidential