CHAPTER 17 MEMORY CIRCUITS

Chapter Outline
17.1 Latches and Flip-Flops
17.2 Semiconductor Memories: Types and Architectures
17.3 Random-Access Memory (RAM) Cells
17.4 Sense-Amplifier and Address Decoders
17.5 Read-Only Memory (ROM)

NTUEE Electronics III 17-1

 17.1 Latches and Filp-Flops

Logic Classifications
 Combinational circuits: output depends only on present value of input
 Sequential circuits: output depends not only on present input values but also on previous values
 Static sequential circuits: use positive feedback to provide two stable states (bistable)
 Dynamic sequential circuits: use the storage of charge on a capacitor
Latch
 Exhibits two stable operating points and one unstable operating point
 The latch needs to be triggered to change stage
 The latch together with the triggering circuitry forms a flip-flop.

NTUEE Electronics III 17-2

The SR Flip-Flop
 The latch is triggered by input S and R
 S =1 and R = 0  Q = 1
 S =0 and R = 1  Q = 0
 S =0 and R = 0  Q unchanged
 S =1 and R = 1  Q undefined (not allowed)

CMOS Implementation of SR Flip-Flop

 The flip-flop is set by S and R when the clock f is high
 Q5, Q6 should be able to pull the output node at least below the threshold of inverter (Q3, Q4)
 The period of the set signal should be long enough to cause regeneration to take over
 The state is latched when the clock f is low
 No static power dissipation (no conducting path between VDD and ground except during switching)

NTUEE Electronics III 17-3

D Flip-Flop Circuits
 Simple implementation of the D flip-flop:
   1 and   0 : the loop is open and Q is determined by D
   0 and   1 : the loop is closed and the flip-flop is in latch mode
 Two-phase non-overlapping clock is required for D flip-flop operation
 Major drawback: the output simply follows the signal on the D input line during f

 Master-slave D flip-flop:

NTUEE Electronics III 17-4

 17.2 Semiconductor Memories

Memory Types
 Random-access memory (RAM): access time is independent of physical location of the stored info
 Sequential memories: data are available only in the same sequence in which the data were stored
 Read/write memory: permits data to be stored and retrieved at comparable speeds
 Read-only memory (ROM): only permits reading operation
Memory-Chip Organization
 The bits on a memory chip are either individually
addressable (64M1) or addressable in groups(16M4)
 Increase in word line and bit line lengths slows down
their transient response due to larger R and C
 Memory chip is partitioned into a number of blocks
to improve the transient response
Memory-Chip Timing
 Memory access time: the time between the initiation
of a read operation and the data at the output
 Memory cycle time: the minimum time allowed
between two consecutive memory operations.
 Access time and cycle time are in the range of a few
to few hundred nanoseconds

NTUEE Electronics III 17-5

 17.3 Random-Access Memory (RAM) Cells

RAM Cells
 It is imperative to reduce the cell size for a large number of bits on a chip
 The power dissipation should be minimized for RAM cells
 There are two basic types of MOS RAMs:
 Static (SRAM): utilize static latches as the storage cells ( ~ 6 transistors/cell)
 Dynamic (DRAM): store binary data on capacitors and require periodic refreshing (~ 1T+1C/cell)
 Both static and dynamic RAMs are volatile
Static Memory Cell
 A typical static memory cell comprises a latch (2 cross-coupled inverters) and 2 access transistors
 The access transistors are turned on when the word line is selected
 The complementary bit lines are connected to the latch when the cell is selected

NTUEE Electronics III 17-6

Read Operation of SRAM
 The complementary bit lines are precharged to an intermediate voltage in the range VDD/2 to VDD
 The bit lines are connected to the latches through access transistors when the cell is selected
 A differential voltage develops between complementary bit lines
 Voltage change at vQ and vQ has to be sufficiently small not to change the latch state during read
 The read operation in an SRAM is nondestructive
 Read delay is determined by the rise time of word line and time needed to develop the required
voltage at bit lines
 The dynamic operation can be approximated by treating Q1 and Q5 as rON1 and rON5
 The larger (W/L)5, the faster the voltage at the bit line develops
 The smaller (W/L)5, the smaller voltage change for vQ and vQ
 The access transistors are usually made two to three times wider than QN of the inverters

NTUEE Electronics III 17-7

Design Constraint for Read Operation
 The worst case scenario is to choose a precharge value of VDD
 Q5 operates in saturation region and Q1 operates in triode region:
1 W  W   1 
I5   nCox   (VDD  Vtn  VQ ) 2  I1  nCox   (VDD  Vtn )VQ  VQ2 
2  L 5  L 1  2 
 To keep Q3 off for nondestructive read, the design constraint is
 
 
 1  (W / L)5 1
VQ  (VDD  Vtn )1    Vtn   2
1
 (W / L) 5  (W / L )  Vtn 
 1 
1
1  
 (W / L)1  V  V
 DD tn 

 The voltage change in vQ is relatively small

 The B line is discharged by I5 at the beginning:
V  I 5 t / C B
 The time needed to develop a voltage difference V is
t  CB V / I 5
 The B line will be finally discharged to 0 in steady state
 Sense amplifiers usually used to speed up the read operation

NTUEE Electronics III 17-8

Write Operation of SRAM
 Before the operation, the complementary bit-lines are respectively set to VDD and ground
 The cell is selected by word line and the cell is connected to bit lines thru access transistors
 At least one of the inverter inputs has to be significantly changed beyond its threshold voltage
 The regenerative feedback starts and the flip-flop changes state
 Q5 is in saturation and the current for charging capacitor equals to I5  I1
 The charging component of write delay is much smaller than the corresponding component
during read operation because only small capacitance CQ needs to be charged
 The delay time in write operation is dominated by the word-line delay

NTUEE Electronics III 17-9

Design Constraint for Write Operation
 Assume the write operation is done by pulling vQ down to Vtn
 Regenerative feedback starts as Q1 turns off
 Q4 operates in saturation region and Q6 operates in triode region:
1 W  W   1 
I5   nCox   (VDD  | Vtn |) 2  I 6   nCox   (VDD  Vtn )VQ  VQ2 
2  L 4  L 1  2 

 The design constraint is specified by

(W / L) 4  p   Vtn  
2
  p (W / L) 4 
VQ  (VDD  Vtn )1    Vtn   1  1   
  n (W / L)6  (W / L)6  n   VDD  Vtn  
   

Design Procedure of the SRAM Cell

 The aspect ratios of the PMOS and NMOS devices in the latch are determined
 Choose the aspect ratio of the access transistors carefully
 Read operation specifies the upper limit of the device size
 Write operation specifies the lower limit of the device size

NTUEE Electronics III 17-10

Dynamic RAM Cell
 One-transistor cell: one transistor and one capacitor per cell
 Only one bit line is use in DRAMs
 When the cell is storing a 1, the capacitor is charged to VDDVt
 When the cell is storing a 0, the capacitor is discharged to 0V
 Refresh operation must be performed every 5 to 10 ms
Read Operation
 The bit lines are precharged to VDD/2
 The word line is raised to VDD and all the access transistors in the selected row are conductive
 A small voltage difference will be detected in the bit lines
 The read operation is destructive
VDD V 
CSVCS  CB  (C B  CS ) DD  V 
2  2 
CS  V  C  V 
V  VCS  DD   S VCS  DD  for C B  CS
CB  CS  2  CB  2 

Write Operation
 The write operation is similar to the read operation except that the data bit to be written
 Data bit to be written is set to VDD or ground and CS will be charged or discharged to VDDVt or 0V
 All other cells in the selected row are refreshed

NTUEE Electronics III 17-11

 17.4 Sense Amplifiers and Address Decoders

Operation of Sense Amplifier

 A sense amplifier is formed by a latch with two cross-
coupled CMOS inverters
 Q5 and Q6 connect the sense amplifier to VDD and ground
when data-sensing action is required
 Precharge and equalization circuit is controlled by fp
prior to a read operation. While Q8 and Q9 precharge the
bit lines to VDD/2, transistor Q7 helps speed up this process
by equalizing the voltages on the two lines
 Complete read operation:
 The precharge and equalization circuit is activated by
fp and complementary bit lines are set to VDD/2
 Word line goes up and the cell is connected to bit lines
 The sense amplifier turned on by fs as an adequate
difference voltage signal is developed between the bit
lines by the storage cell
 The data stored in the cell is refreshed as the sense
amplifier pulls the bit lines to VDD and ground

NTUEE Electronics III 17-12

Dynamic Operation of Sense Amplifier
 When the sense amplifier is activated, both inverters are biased in transition region (VIN = VDD/2)
 With input signal vi, the output signal (gmp + gmn)vi is fed back to the input (positive feedback)
 Bit line voltage rises/decays exponentially with a time constant of CB/Gm for small-signal operation
 As the voltage deviates from VDD/2, the it tends to saturate at VDD or ground (large-signal operation)

VDD
Read-1 operation: vB   V (1)e (Gm / CB )t
2
V
Read-0 operation: vB  DD  V (0)e (Gm / CB )t
2

NTUEE Electronics III 17-13

An Alternative Sense Amplifier
 A differential amplifier with a current mirror as the active load
 The charging/discharging current is defined by the bias current I
 The voltage difference developed by the sense amplifier: V = I t/C
 The voltage required for complete current switching: V = 2 VOV

Alternative Precharging Arrangement

 Vprecharge = VDD for PMOS switches
 Vprecharge = VDD–Vt for diode-connected NMOS

NTUEE Electronics III 17-14

Differential Operation in Dynamic RAMs
 Each bit line is split into two identical halves
 Each half-line is connected to half the cells in the column and an additional dummy cell
 The dummy cell serves as the other half of a differential DRAM cell to cancel the error voltage on
bit lines due to clock feedthrough
 During precharge phase, two dummy cells are precharged to VDD/2
 Differential signal V(1) or V(0) is detected by the sense amplifier when it is enabled

NTUEE Electronics III 17-15

Row-Address Decoder
 The decoder can be realized by NOR functions provided by the matrix structure  NOR decoder
 The word lines are precharged to VDD during precharge
 All the unselected word lines will be discharged
 No static power dissipation due to dynamic operation

W0  A0 A1 A2  A0  A1  A2

W1  A0 A1 A2  A0  A1  A2

W2  A0 A1 A2  A0  A1  A2

W3  A0 A1 A2  A0  A1  A2

W4  A0 A1 A2  A0  A1  A2

W5  A0 A1 A2  A0  A1  A2

W6  A0 A1 A2  A0  A1  A2

W7  A0 A1 A2  A0  A1  A2

NTUEE Electronics III 17-16

Column-Address Decoder
 Column-address decoder is to connect one of the 2N bit lines to the data I/O line of the chip
 It exhibits the same function as a multiplexer
 Pass-transistor logic decoder:
 A NOR decoder + pass-transistor multiplexer
 Tree decoder:
 Utilize smaller number of transistors
 Speed decreases due to a relatively large number of series transistors in the signal path

NTUEE Electronics III 17-17

Pulse-Generation Circuits
 The ring oscillator:
 Generates periodic output waveforms
 Odd number of stages in the loop
 The oscillation frequency is 1/2NtP

 A one-shot or monostable multivibrator circuit

 A single output pulse with a predetermined
width is provided when triggered
 The width is determined by NtP

NTUEE Electronics III 17-18

 17.5 Read-Only Memory (ROM)

MOS ROM
 Non-volatile memory operation
 The circuit can be in a static or a dynamic form
 The data stored in the ROMs is determined at the time of fabrication

NTUEE Electronics III 17-19

Mask-Programmable ROMs
 Mask programmable ROMs can avoid having custom design each ROM from scratch
 MOSFETs are included at all bit locations but only the gates of those transistors where 0’s are to
be stored are connected to the word lines

disconnected

connected

NTUEE Electronics III 17-20

Programmable ROM (PROM)
 The data can be programmed by the user, but only once
 A typical PROM uses polysilicon fuses to connect the emitter of each BJT to the digital line

fuse

NTUEE Electronics III 17-21

Erasable Programmable ROM (EPROM)
 The data can be erased and reprogrammed as many times by the uses
 A floating-gate transistor can be used for EPROM at all bit locations as memory cells
 Programming process:
 Apply high voltage to the select gate and between the source and the drain
 Hot electrons are injected into the floating gate and become trapped
 After the programming process, the programmed transistors exhibit high threshold voltage
 The process of charging is self-limiting as the charge accumulation increases
 Erasure process:
 Illuminate the cell with UV light for a specified duration
 UV light provides the trapped electrons sufficient energy to transported back to the substrate

NTUEE Electronics III 17-22

Electrically Erasable Programmable ROM (EEPROM)
 EEPROMs are organized as arrays of floating-gate transistors
 Can be programmed or erased in-circuit
 No UV light needed in erase process

Programming via hot electron injection Erasing via tunneling

NTUEE Electronics III 17-23