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Important Synthesis Rules

This document provides guidelines for synthesizing logic to improve design performance and produce a cleaner design. Key points include: 1. Keep clock logic like gating and resets in one block for clean clock constraints. 2. Top block should only connect modules, not contain combinational logic. 3. Name modules same as files and avoid multiple modules per file to avoid synthesis confusion. 4. Code finite state machines with enumerated state names and separate state registers from combinational next-state logic.

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27 views

Important Synthesis Rules

This document provides guidelines for synthesizing logic to improve design performance and produce a cleaner design. Key points include: 1. Keep clock logic like gating and resets in one block for clean clock constraints. 2. Top block should only connect modules, not contain combinational logic. 3. Name modules same as files and avoid multiple modules per file to avoid synthesis confusion. 4. Code finite state machines with enumerated state names and separate state registers from combinational next-state logic.

Uploaded by

gautamarora
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Synthesis Guidelines Document Must read before you synthesize

Following are given some guidelines which if followed might improve the performance of the synthesized logic, and produce a cleaner design that is suited for automating the synthesis process. 1. Clock logic including clock gating and reset generation should be kept in one block to be synthesized once and not touched again. This helps in a clean specification of the clock constraints. Another advantage is that the modules that are being driven by the clock logic can be constrained using the ideal clock specifications. 2. No glue logic at the top: The top block is to be used only for connecting modules together. It should not contain any combinational glue logic. This removes the time consuming top-level compile, which can now be simply stitched together without undergoing additional synthesis. 3. Module name should be same as the file name and one should avoid describing morethat one module or entity in a single file. This avoids any confusion while compiling the files and during the synthesis. 4. While coding finite state machines, the state names should be described using the enumerated types. The combinational logic for computing the next state should be in its own process, separate from the state registers. Implement the next-state combinational logic with a case statement. This helps in optimizing the logic much better and results in a cleaner design.

Incomplete sensitivity lists must be avoided as this might result in simulation

Synthesis Guidelines Document Must read before you synthesize

5. Memory elements, latches and flip-flops: A latch is inferred when an incomplete if statement with a missing else part is specified. A flip-flop, or a register, is inferred
when an edge sensitive statement is specified in the always statement for Verilog and process statement for VHDL. A latch is more troublesome than a latch as it makes static timing analysis on designs containing latches. So designers try to avoid latches and prefer flipflops more to latches. 6. Multiplexer Inference: A case statement is used for implementing multiplexers. To prevent latch inferences in case statements the default part of the case statement should always be specified. On the other hand an if statement is used for writing priority encoders. Multiple if statements with multiple branches result in the creation of a priority encoder structure. Ex: always @ (A, B, C) begin if A= 0 then D = B; end if; if A= 1 then D = C; end if; end

The above example infers a priority encoder with the first if statement given the precedence. The same code can be written using a case statement to implement a multiplexer as follows. always @ (A, B, C) begin

Synthesis Guidelines Document Must read before you synthesize

case (A) is when 0 => D = B; when others => D = C; end case; end The same code can be written using if statement along with elsif statements to cover all possible branches. Three state buffers: A tri-state buffer is inferred whenever a high impedance (Z) is assigned to an output. Tri-state logic is generally not always recommended because it reduces testability and is difficult to optimize since it cannot be buffered. Signals versus Variables in VHDL: Signal assignments are order independent, i.e. the order in which they are placed within the process statement does not have any effect on the order in which they are executed as all the signal assignments are done at the end of the process. The variable assignments on the other hand are order dependent. The signal

Synthesis Guidelines Document Must read before you synthesize

assignments are generally used within the sequential processes and variable assignments are used within the combinational processes.

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