mp chapterwise imp questions
mp chapterwise imp questions
AbD A BX+SI+5
MODULE 3: VIemory nd reripherais interfacing
3.1 Memory Interfacing - RAM and ROM Decoding Techniques Partial and Absolute
3.2 8255-PPI-Block diagram, CWR, operating modes, interfacing with 8086.
3.3 8257-DMAC-Block diagram, DMA operations and transfer modes.
3,4 Programmable Interrupt Controller 8259-Block Diagram, Interfacing the 8259 in single and cascaded
mode.
QUESTIONS
1. Interface three 8259 with 8086 in minimum mode and explain its functionality in fully nested mode. OR
Explain Interfacing of 8259 with 8086 in minimum mode.
Write short note on 8259- PIC. OR Draw and explain block diagram of 8259 PIC.
3 Explain the 8257 DMA controller with the help of neat diagram and explain its Control Register Format.
4. Explain DMA data transfer modes in brief. OR Explain different data transfer modes of 8257 DMA
controller. OR Interface DMA controller 8237 with 8086 microprocessor. Explain different data transfer
modes of 8237 DMA controller.
5. Explain Mode 2 of 8255 with a neat block diagam.Showthe CWR initialization.
6 Draw and explain the block diagram of 8255.lso, xplain different operating modes of 8255
7. Explain with block diagram working of 8255 PP)
8. Design 8086 microprocessor based system workingin minimum mode with the followjng specifications.
8086 microprocessor working at 8MHz.
II) 16 KB EPROM using 8 Kdevic
9. Design 8086 based system for following requirements:
a. Clock frequenc 5MHx
b. 512 KB RAM sing32 KR X8
c. 256 KB ROM uing 3 KB>
10. Design 8086 based syste with Tollowing specificatio
i) 8086 is working in minimum mode at 10MHz.
i) 8 KB EPROM using 2 KB hips
i) 16 KBSRAM using 8 KB chips:
11. Pesign 80B6 microprocessor-bàsed system wih following specifications
a) Mioprocessor2086 working at \0MHz in miimum mode
(b)2KBEPROM Using8 KB chip.
(c) 16 KBSRAM using KB chips
Explain the design along with memory address map.
12. Design 8086icroprocessor-based on following Specifications:
(a) MP 8086 working at 10MHz minimum mode.
(b) 64 KB ROM using 16KB Devices
O 32KB RAM using 16Ke chips
13. Design 8086 microprocessar-based system with following specifications
(a) Microprocessor 8086 working at 8MHz in minimum mode
(b) 32 KB EPROM using 16 KB chips
(c) 16 KB SRAM using 8 KB chips
Explain the design along with memory address map.
14. Design 8086 based system with following specifications.
(1) 8086 working at 8MHz at minimum mode
(2) 256 KB RAM using 64 KBX8 device
(3) 128 KB EPROM using IC 27128.
15. Design 8086 based system with following specifications.
(1)8086 working at 8MHz at minimum mode
(2) 64 KB RAM using 32 KB x 8 device
(3) 64KB EPROM using IC 27128.
16. Design 8086 based minimum mode system for following requirements:
I. 256 KB of RAM using 64 KB × 8-bit device
II. 128 KB of RAM using 64 KB X 8-bit device
III. Three 8-bit parallel ports using 8255
IV. Support for 8 interrupts
17. Design 8086 based system with following specification
(a) 8086 in minimum mode working at 8MHz
(b) 32 KB EPROM using 16 KB devices.
(c) 64 KB SRAM using 32 KB devices.
18. Explain the need of DRAM controller for interfacing DRAM with 8086.
OR Draw and explain interfacing of DRAM controller with 8086.
MODULE 4: Intel 80386DX Processor
4.1 Architecture of 80386 microprocessor
4.2 80386 registers-General purpose Registers, EFLAGS and Control registers
4.3 Real mode, Protected mode, virtual 8086 mode
4.4 80386 memory management in Protected Mode Descriptors and sclcctors, descriptor tables, the
memory paging mcchanism
QUESTIONS
1. Differentiate between real Mode, Virtual Mode and Protected Mode of 80386 Processor. OR
Difference between real mode and protected mode
2. Write short note on virtual 86 mode of 80386DX OR Explain V86 mode of 80386 DX.
3. Explain the mode of operation of 80386 microprocessor.
4. Explain flag register of 80386DX OR Explain the EFLAG REGISTERof 80386 Processor.OR Drav
and explain EFLAG register format of 80386 DX,
5. Write short note on control register of 803860X
6. Explain the segment descriptor of 80386 processor. OR Draw a segment descriptor table, the
memory paging mechanism.
7. Explain protection mechanism of 80386 with dlagram.
8. Explain descriptors and paging nechanism in protected mode of 80386? OR Explain, with
neat diagram, address translation mechagism implenmented on 80386 D. ORWrite short
note on page translation mechanism on 80386 DX.
9. Explain 80386 processor descriptor and its content.
MODULE 5: Pentium Processor
5.1 Pentium Architccture
5,2 Superscalar Operation,
5.3 Integer &Floating-Point Pipclinc Stages,
5,4 Branch Prediction Logic,
5,5 Cache Organization and
5.6 MESI protocol
QUESTIONS
1. Draw and Explain Floating point pipeline for Pentium processor.
2. Explain, in brief pipeline stage on Pentium processor.
3. Explain integer pipeline of Pentium processor?
4. Explain how the flushing of pipeline problem isminiized In Pentiumarchitecture.
5. Enlist the instruction pairing rules for Uandpipeline in Pentium.
6. Write instruction issue algorithm used in Pentiom.
7. Explain the Branch Prediction Mechanism of Pentium Processor.
8. Explain in brief cache organization of Pentiumprocessor OR Explain, with heat diagram, cache
memory organization is supported by Pentiumprocessor
9. Explain Data Cache architecture for Pentium Processor
10. Explain MESI protocol
11. Write down features of Pentium prOcessar
12. Draw and Explain architeture bf Pentium prgcessor OR Drawand explajn block diagram of Pentium
procesSor.
MODULE 6: Pentium 4
6.1 Comparative study of 8086, 80386, Pentium I, Pentium ll and Pentium IlI
6.2 Pentium 4: Nct burst micro architccturc.
6.3 Instruction translation look aside buffer and branch prediction
6.4 Hypcr thrcading technology and its usc in Pentium 4
QUESTIONS
1. Explain Pentium 4 Net burst micro architecture and write a note on hyperthreading
2. Explain hyper threading technology and its use in Pentium 4
3. Compare 80386, Pentium 1, Pentium 2 and Pentium 3 Processor.
4. Compare Pentium 2, Pentium 3 and Pentium 4 processors.
5. Compare Pentium, Pentium ll and Pentium IlJprocessors.
6. Compare 8086, 80386 and Pentium.
7. Explain Superscalar and Branch Prediction for Pentium Processor.