This article has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

This is the author's version which has not been fully edit
content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2024.3463534

ATOM: An Automatic Topology Synthesis

Framework for Operational Amplifiers
Jinyi Shen, Fan Yang∗ , Member, IEEE, Li Shang, Member, IEEE, Changhao Yan, Member, IEEE,
Zhaori Bi, Member, IEEE, Dian Zhou, Senior Member, IEEE, and Xuan Zeng∗ , Senior Member, IEEE
Abstract—Bayesian optimization is more efficient in auto- a sacrifice of opamp performance potential. Moreover, these
matically synthesizing operational amplifier (opamp) topologies methods based on evolutionary algorithms [5, 6], graph con-
compared to conventional methods. However, the design space struction processes [7] or reinforcement learning [8, 9] exhibit
for behavior-level opamp topologies involves numerous connec-
tions that are difficult to comprehend, and evaluating each relatively low efficiency and require evaluation of numerous
topology incurs substantial computational costs. To tackle these topologies, incurring substantial computational costs.
challenges, this brief introduces ATOM, an automatic opamp To address these challenges, opamp topology synthesis
topology synthesis framework. We construct a concise design methods based on Bayesian optimization (BO) are presented
space for behavior-level opamp topologies, consisting of topologies in [10–12]. The behavior-level topology design space circum-
that designers can easily understand. We propose an opamp
topology optimization method that incorporates freeze-thaw vents the complexities associated with transistor-level connec-
Bayesian optimization. This method efficiently explores the design tion rules and provides enhanced coverage of opamp com-
space and expedites the evaluation process. Experimental studies pensation structures. The utilization of BO enables sample-
demonstrate that ATOM outperforms state-of-the-art topology efficient exploration of the topology design space. However,
synthesis methods in terms of success rate and optimization the opamp design space includes compensation structures that
results while reducing the number of required simulations by
up to 8.15 times. The source code for ATOM is available at are unfamiliar to circuit designers, thus limiting the practical
https://github.com/Jinyi-Shen/ATOM. utility of the synthesized topologies. Additionally, evaluating
each visited topology through detailed sizing imposes a sub-
Index Terms—Design Automation, Topology Synthesis, Opera-
tional Amplifier, Bayesian Optimization, Freeze-thaw Technique stantial computational burden.
This brief presents ATOM, an automatic topology synthesis
I. I NTRODUCTION framework for opamps. ATOM enhances the synthesis capabil-
ity of our prior BO-based topology synthesis method [12] by
The operational amplifier (opamp) is a common building incorporating a designer-comprehensible design space, more
block for various analog circuits. Since the design specifica- comprehensive stability constraints, an improved graph rep-
tions of opamps differ across applications, the circuit topology resentation tailored to the design space, and a more efficient
needs to be tailored accordingly. Topology customization has optimization algorithm. We propose a concise topology design
long been carried out by experienced analog designers based space by decomposing opamp compensation structures into
on a limited collection of topology templates. This manual functional modules and leveraging manual design experience
design process is time-consuming and design quality is limited to determine the allowed module types. We introduce a novel
by the availability of topology templates as well as the graph representation for the topologies within our design space
expertise of analog designers. In order to discover new opamp and utilize a graph variational autoencoder to learn continuous
topologies and shorten the design cycle, there is a great need topological representations that are suitable for optimization.
for automatic topology synthesis of opamps. We propose an opamp topology optimization method based on
Existing opamp topology synthesis methods can be clas- freeze-thaw BO, enabling sample-efficient exploration of the
sified into two categories: topology selection and topology topology design space while facilitating simulation-efficient
generation. Topology selection methods [1–4] rely on heuristic topology evaluation. Experimental studies demonstrate that
rules [1] or data-driven machine learning models [2–4] to se- ATOM achieves a higher success rate, significantly better
lect topologies from a pre-defined topology library. However, optimization results, and substantially improved optimization
these methods are limited by a narrow range of compensation efficiency when compared to state-of-the-art methods.
structures and require substantial effort for rule development,
model training, or library construction. Topology generation
methods [5–9] generate topologies based on predefined rules II. P RELIMINARIES
and building blocks. However, the topology design space for A. Problem Formulation
multi-stage opamps is vast. These methods reduce the design Topology synthesis is defined as a constrained optimization
space by either limiting the number of opamp stages [5, 6] problem in this study. The objective is to identify an opamp
or simplifying the compensation structures [7–9], resulting in topology that maximizes the figure of merit (FOM) while
This research is supported partly by National Key R&D Program of
adhering to all performance constraints. This problem can be
China 2020YFA0711900, 2020YFA0711901, partly by National Natural Sci- mathematically expressed as
ence Foundation of China (NSFC) research projects 62141407, 62474050,
92373207, 62090025, 62304052, 62474051. maximize f (t, x∗ )
t∈T
*Corresponding authors: Fan Yang and Xuan Zeng. Email: {yangfan,
s.t. x∗ = arg max {f (t, x) : ci (t, x) < 0} , (1)
xzeng}@fudan.edu.cn x∈St
Jinyi Shen, Fan Yang, Changhao Yan, Zhaori Bi and Xuan Zeng are with
State Key Laboratory of Integrated Chips and Systems, Microelectronics where f is the FOM, ci denotes the i-th performance con-
Department, Fudan University, Shanghai, China.
Li Shang is with School of Computer Science, Fudan University, Shanghai, straint, and t is an opamp topology in the design space T .
China. The vector x encompasses adjustable continuous opamp circuit
Dian Zhou is with State Key Laboratory of Integrated Chips and Systems, parameters, including the transconductance of amplification
Microelectronics Department, Fudan University, Shanghai, China, and the
Department of Electrical Engineering, University of Texas at Dallas, USA. stages, and the values of resistors and capacitors. Parameter
Dian Zhou is the emeritus professor at the University of Texas at Dallas. range St is set for the parameters of t to ensure the practicality.

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 This article has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This is the author's version which has not been fully edit
content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2024.3463534

B. Variational Autoencoder for Directed Acyclic Graphs opamp’s frequency response, and this behavioral-level simpli-
The directed acyclic graph (DAG) variational autoencoder fication captures the primary behavior of the opamps. Com-
(DVAE) [13] is a powerful generative model comprising pared with transistor-level topology optimization approach,
two neural networks: an encoder network parameterized by behavior-level topology optimization offers the advantages of
ϕ that transforms a DAG g into a low-dimensional latent reduced computational complexity and faster exploration of
representation z and a decoder network parameterized by θ design alternatives while maintaining the necessary precision.
that reconstructs g from z. The encoder and decoder are Though transient specifications cannot be measured directly at
denoted as qϕ (z|g) and pθ (g|z), respectively. They are trained the behavioral level, they can be addressed during behavior-
together by maximizing the evidence lower bound L: level topology optimization by estimating their values using
component parameters and the currents of amplification stages.
L(ϕ, θ) = Ez∼qϕ (z|g) log [pθ (g|z)] − KL [qϕ (z|g)||p (z)] , (2) In this brief, we use three-stage opamps as an example
to demonstrate the topology synthesis capability of ATOM.
where Ez means the expectation computed with respect to This choice is due to the high gain requirements in various
z, and KL[·||·] refers to the Kullback-Leibler divergence that applications, as well as the high design complexity and large
measures the similarity between two probability distributions. topology design space of three-stage opamps. Following [14],
The prior p (z) is typically a Gaussian distribution. we categorize three-stage opamps into two types: opamps with
Miller-compensated inner amplifiers (Type I) and opamps with
III. P ROPOSED A PPROACH uncompensated inner amplifiers (Type II). For both types,
we propose a functional module decomposition approach that
This section presents ATOM, a fully automatic opamp decomposes opamps into functional modules. As shown in
topology synthesis framework. The framework of ATOM is Fig. 1(a), both types of topologies comprise ten modules:
depicted in Fig. 1. We first construct a behavior-level topology three main amplification stages AMP1-AMP3, two feedback
design space for opamps. Next, we design a DAG representa- modules FB1-FB2, three feedforward modules FF1-FF3, and
tion for opamp topologies and employ DVAE to convert the two loads LD1-LD2. The parasitic components, R and C, are
DAGs into continuous topological representations. Finally, we omitted in Fig. 1(a) for brevity. This functional module decom-
develop freeze-thaw BO to efficiently explore the continuous position disentangles the compensation structure of opamps
topology space and identify high-quality opamp topologies. and simplifies the functionality of each module.
To determine the types of different modules, we refer to a
FB1 FB1 comprehensive analysis of module structures in opamp topolo-
FB2 FB2
gies presented in [14]. This ensures the interpretability of the
AMP1 AMP2 AMP3 AMP1 AMP2 AMP3
topologies within our design space. The polarity of AMP1-
- + - + - +
input
LD1 LD2
output input
LD1 LD2
output AMP3 is determined by the requirements of each opamp type.
Main Amplifiers The allowed types for other modules are summarized as
Feedback FF1 FF1
ground ground
Feedforward FF3 FF3
• FB1, FB2: Miller capacitor, Nulling resistor, Active ca-
FF2 FF2
Load pacitive feedback with positive/negative polarity of gm ,
Type I Type II
and No connection. 5 types.
(a) Opamp Topology Design Space • FF1-FF3: With/without feed-forward stage. 2 types.
Input DAG Dataset G
Reconstruction Likelihood
Reconstructed DAG Dataset G’ • LD1, LD2: With/without serial RC. 2 types.
input input The unique functionalities of different modules enable any
DVAE DVAE
Encoder
Latent
Decoder combination of these modules, within the allowed types, to
AMP1 FF1 Space Z AMP1 FF1
constitute a valid three-stage opamp topology. Comprising
FF2
LD1
AMP2 q (z | g ) p ( g | z ) FF2
LD1
AMP2 1600 topologies, our design space not only offers a good
FF3 LD2
FB1
FF3 LD2
FB1
coverage of the manually designed topologies in the review
ground
AMP3 FB2
ground
AMP3 FB2
article [14], but also contains novel topologies with good per-
output output
formance. Expanding the design space may introduce unvali-
(b) Continuous Topological Representation Learning dated, uninterpretable modules, thereby increasing the sparsity
of high-quality solutions and complicating the identification of
znew from Latent
Freeze-thaw Predict Freeze-thaw these solutions within the design space.
Space Z Predicted Quality of
z1, …, zN from
Gaussian
z1, …, zN, and znew
Selection To ensure the stability and proper functionality of opamps,
Process Model Scheme the opamp gain is required to monotonically decrease with
Candidate Basket
Update Update Select frequency, and the distribution of poles and zeros is carefully
Simulated Evaluate Decode
monitored. No right-half-plane poles are allowed, and the
Topology t* Representation z*
Quality of t*
quality factor Q is restricted to be between 0.6 and 0.8.
(c) Freeze-thaw Bayesian Optimization

Fig. 1: The overall framework of ATOM. B. Continuous Topological Representation Learning

The topology of an opamp can be fully characterized by its
circuit module types and their interconnections. This obser-
A. Opamp Topology Design Space vation motivates us to adopt a graph-based representation for
Following the common practice of circuit designers, we opamp topologies. In this representation, each circuit module
adopt a behavior-level approach for opamp topology design. is transformed into a node within the circuit graph. Three
An amplification stage is represented as a voltage-controlled auxiliary graph nodes named input, output, and ground are
current source (gm ), along with two parasitic components—a added to ensure the circuit graph possesses a single start
resistor (R) and a capacitor (C)—that are connected to the node and a single end node. To maintain the interconnections
ground. These components are critical determinants of the between modules, the remaining circuit nets are represented

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 This article has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This is the author's version which has not been fully edit
content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2024.3463534

as graph edges. We introduce an additional inductive bias into simulations to different topologies based on their predicted
our circuit graphs by setting the direction of all edges based quality, thereby enhancing efficiency.
on the signal flow, thereby simulating how opamps process The quality of a topology is defined as its optimal FOM
signals and converting the circuit graph into a DAG. The DAG while satisfying the performance constraints. We evaluate the
shown in Fig. 1(b) illustrates the Type I topology in Fig. 1(a). quality of topologies using a BO-based sizing approach [15],
Our circuit graphs accurately represent topologies in our which employs the weighted Expected Improvement (wEI)
design space, including parallel connections of functional acquisition function to handle constraints.
modules connecting the same pair of circuit nets, such as FF3 Freeze-thaw BO comprises two essential components: a
and FB1. In contrast, the graph representation in [12] cannot freeze-thaw Gaussian Process (GP) surrogate model, which
accommodate such parallel connections. Therefore, our graph predicts the quality of topologies, and a freeze-thaw selection
representation better captures the similarity of topologies and scheme, which determines the topology that requires more
allows for more accurate performance modeling. accurate evaluation through an additional round of sizing.
In the current approach, one-hot encoding is utilized as the The freeze-thaw GP model integrates GP models from two
node feature to represent module types. However, alternative levels [16]. At the upper level, one GP model characterizes
embeddings that effectively capture the semantic meanings of the quality of various topologies based on their topology
node types can be readily employed. Unlike the representation representations. At the lower level, a separate GP model
in [12], which employs a single number to indicate the module is constructed for each topology to model its quality about
type, our representation is more expressive and offers greater the number of allocated simulations. Let {zi }M i=1 denote the
extensibility. Moreover, a circuit graph can be transformed into topological representations of M topologies {ti }M i=1 , and
an opamp topology by reversing this conversion. yi = [yi1 , yi2 , · · · , yiNi ]⊤ denote the evaluation history of the
Optimizing topologies on circuit graphs is inefficient due to quality of ti , where Ni is the number of sizing rounds and
their discrete nature. To address this issue, we propose to learn yij , j = 1, · · · , Ni is the quality recorded in j rounds of sizing.
continuous topological representations leveraging DVAE [13]. The GP at the lower level for ti is yi ∼ N (fi 1i , KNi ), where
This approach allows us to utilize continuous optimization fi is the predicted quality of ti , 1i is a vector of 1’s with length
algorithms for topology optimization. The flow of continuous Ni , and KNi is a covariance matrix defined by a kernel for
topological representation learning is illustrated in Fig. 1(b). curves [16]. The GP at the upper level is f ∼ N (m, KM ),
DVAE employs a message passing process that follows where f = [f1 , f2 , · · · , fM ]⊤ , m is a constant vector with
the signal propagation direction in opamps. The same DVAE length M , and KM [i, j] = kmat [zi , zj ] where kmat is the
encoder as [13] is utilized. In our DVAE decoder, a multi-layer Matérn-5/2 kernel. By combining the above GPs, freeze-thaw
perceptron (MLP) topology classifier is employed to determine GP models the evaluation history of all visited topologies as
the type of opamp to be reconstructed. Subsequently, the   Z    
main amplification stages in the DAG are reconstructed based M M M M
P {yi }i=1 |{zi }i=1 = P {yi }i=1 |f ·P f | {zi }i=1 df
on the determined opamp type. The remaining module types M
are then inferred using another MLP classifier, based on the
ZY   (3)
M
reconstructed graph hidden state that is continuously updated = P (yi |fi )·P f | {zi }i=1 df
by a gated recurrent unit (GRU). i=1

The dimensions of the node hidden state and the topological The freeze-thaw GP model predicts both the mean and vari-
representation space are set to 500 and 10, respectively. Our ance of the quality of topological representations based on the
DVAE encoder and decoder are jointly trained using the loss simulation results of visited topologies. It is an online surro-
function defined in Eq. (2). A random 90%-10% training- gate model that is continuously updated during optimization
testing split is applied to all topologies in our design space. through maximum likelihood estimation, ensuring its accuracy.
The DVAE model is trained for 500 epochs on an Nvidia To mitigate the computational burden associated with topol-
2080Ti GPU. The training process completes in approximately ogy evaluation through sizing, only one topology is allowed
20 minutes. The trained DVAE achieves a 100% reconstruction to undergo an additional round of sizing in each iteration of
accuracy for all the topologies within our design space, indi- topology optimization. This topology is selected by a freeze-
cating that the learned topological representations effectively thaw selection scheme. A candidate basket is constructed to
capture the information pertaining to the opamp topologies. store the current best topological representations. During the
Our methodology can generalize to a broader design space, initial stages of topology optimization, when the basket is not
including more complex three-stage opamps and opamps with yet full, indicating an insufficient collection of high-quality
varying numbers of stages. To make our approach applicable topologies, a new representation znew found by optimizing the
across categories, the topology design space must be crafted to wEI acquisition function αwEI is selected for performance
ensure diversity while maintaining a high proportion of valid evaluation. Once the basket is filled, the benefits of conducting
topologies for different stages. The architecture of the DVAE an initial topology evaluation for znew versus a more accurate
model should be modified to increase its model capacity to evaluation for the best existing representations stored in the
achieve high reconstruction accuracy for each category. The candidate basket should be compared to select the represen-
revised DVAE model should be trained with a dataset of tation for evaluation. The benefits are measured using the en-
topologies covering various stages. tropy search (ES) acquisition function αES [17], which reflects
the expected information gain after evaluating representation
z. The representation with the highest ES value is selected for
C. Freeze-thaw Bayesian Optimization evaluation. The freeze-thaw selection scheme employs a two-
We propose a topology optimization method based on round comparison for selecting the representation, striking a
freeze-thaw BO to efficiently explore the continuous topology better balance between exploration and exploitation.
space. Freeze-thaw BO maximizes the utilization of simula- Then the trained DVAE decoder is utilized to reconstruct an
tions by integrating iterative topology evaluation processes into opamp topology from the selected representation. The type of
the topology optimization workflow. It dynamically allocates the reconstructed topology is decided by the topology classifier

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 This article has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This is the author's version which has not been fully edit
content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2024.3463534

in the decoder. An additional round of sizing is performed TABLE I: Opamp Specifications

for the topology. Upon completion of sizing, the evaluation Specs Gain(dB) UGF(MHz) PM(°) Power(µW) CL (pF)
history of the topology is expanded, and the freeze-thaw GP Spec1 >85 >0.7 >60 <250 10000
is updated. This process continues until the simulation budget Spec2 >80 >50 >60 <9000 10
is exhausted. Opamp topology optimization using freeze-thaw
BO is summarized in Algorithm 1 and Fig. 1(c).
TABLE II: Behavior-level Opamp Optimization Results

Algorithm 1: Freeze-thaw Bayesian Optimization Success Final No. Sim

Specs Methods
Rate FOM(103 )* Sim Speedup
input : Representation space Z, basket size Nb
FE-GA 10/10 81.48±30.85 2080 1×
1 Get initial dataset D0 by doing initial evaluation for
Spec1 VGAE-BO 10/10 97.41±35.60 1840 1.13×
the reprensentions randomly sampled from Z; ATOM 10/10 236.57±132.28 325 6.40×
2 for i = 1 to N do FE-GA 3/10 0.089±0.014 2240 1×
3 Train the freeze-thaw GP using Di−1 ; Spec2 VGAE-BO 3/10 0.117±0.026 600 3.73×
4 znew = argmaxz∈Z αwEI (z); ATOM 10/10 0.362±0.190 275 8.15×
5 if the number of representations that meet all *Final FOM presented as mean±standard deviation.
performance constraints in Di−1 < Nb then
B. Behavior-level Optimization Results
6 z∗ = znew ;
The optimization results from ten runs are summarized
7 else in Table II, and the average results of the successful runs
8 Add the best Nb representations to B; are plotted in Fig. 2. ATOM achieves superior success rates,
9 z∗ = argmaxz∈{znew }∪B αES (z); optimization efficiency and final results compared to the
baselines. Specifically, ATOM achieves a simulation speedup
10 Decode z∗ into topology t∗ ; of 5.66× to 6.40× and a final FOM improvement of 2.43× to
11 Evaluate t∗ using an additional round of sizing; 2.90× for Spec1. For Spec2, ATOM is the only method that
12 Update Di with the best quality recorded for t∗ ; consistently identifies good topologies across ten optimization
13 return the current best topology t∗ runs, and it achieves a simulation speedup of 2.18× to 8.15×
and a final FOM improvement of 3.09× to 4.06×. This
superior performance is attributed to the improved topology
In freeze-thaw BO, the integration of the freeze-thaw GP design space with better coverage of three-stage opamp topolo-
model with the freeze-thaw selection scheme enables the gies, enhanced topological representation that more accurately
method to make informed decisions about when to resume measures topology similarity and allows for more precise
sizing for previously explored topologies and when to initiate performance modeling, and the advanced freeze-thaw BO
sizing for new ones. As a result, freeze-thaw BO allocates sim- optimization algorithm that allocates simulations based on the
ulation resources more efficiently based on topology quality, quality of topologies rather than equally across all topologies.
in contrast to conventional methods [10, 12] that distribute
simulations uniformly across all topologies. This approach 1e5 Spec1 1e2 Spec2
addresses the sparsity of high-quality solutions in the design
space by freezing most low-quality topologies after an initial 2.0 3
FE-GA
evaluation, thereby reducing simulation costs, and by retaining 1.5 VGAE-BO FE-GA
ATOM 2 VGAE-BO
FOM

FOM

promising topologies in the candidate pool for detailed sizing,

fully exploiting their performance potential. 1.0 ATOM
0.5 1
IV. E XPERIMENTAL R ESULTS
500 1000 1500 2000 2500 500 1000 1500 2000 2500
A. Experiment Setup Number of simulations Number of simulations

We conduct our experiments with two 2.9GHz CPUs and Fig. 2: Behavior-level opamp optimization curves plotted using
512 GB memory. The Hspice circuit simulator is utilized. the average results from the successful runs. The number
Our baselines include opamp topology optimization meth- of simulations for each method to achieve the same FOM
ods FE-GA [10] and VGAE-BO [12]. The maximum simula- (marked with the dashed lines) is given in Table II.
tion budget for each method is set to 2400. The bi-level BO
encompasses 60 upper-level iterations, each with a budget of C. Circuit Analysis
40. For ATOM, we specify a basket size of 3, 160 topology
optimization rounds, and 10 sizing iterations per round. The topologies found by ATOM include both those similar
We examine four important opamp performance metrics: to classic ones in [14] and novel topologies. The performances
Gain, unit gain frequency (UGF), phase margin (PM) and of the two best opamps found by ATOM, as illustrated in
Power. Gain, UGF, and PM are measured using behavior-level Fig 3, and the best opamps identified by baseline methods,
simulations. Power is estimated following [12]. We evaluate are presented in Table III. The opamps found by ATOM
all methods under two distinct sets of specifications (specs), achieve high UGF with low power consumption, resulting in
each utilizing a fixed load capacitor, as detailed in Table I. the highest FOM. For ATOM, the best topology for Spec1
The optimization goal is and Spec2 undergoes 14 and 9 sizing rounds, respectively.
The baselines miss the better solutions found by ATOM
UGF[MHz]×CL [pF]
maximize FOM = Power[mW] . (4) due to limited topology coverage and the sparsity of their
topology design space, inferior topological representations,

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 This article has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This is the author's version which has not been fully edit
content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2024.3463534

TABLE III: Performance of the Best Opamps

FOM Gain UGF PM Power
Specs Level Method
(103 ) (dB) (MHz) (°) (µW)
FE-GA 127.42 96.9 1.36 60.7 106.8
Behavior VGAE-BO 159.69 91.2 0.77 71.3 48.3
ATOM 356.56 106.7 1.62 62.9 45.4
Spec1
FE-GA 87.55 106.3 1.94 61.6 221.7 (a) (b)
Transistor VGAE-BO 103.54 96.4 1.00 70.9 96.4
ATOM 271.86 117.2 1.30 65.5 47.9 Fig. 5: The (a) bode plot and (b) transient response of the best
FE-GA 0.177 82.5 81.82 60.8 4623 opamp found by ATOM for Spec2.
Behavior VGAE-BO 0.246 92.8 73.98 69.4 3012
ATOM 0.484 82.1 124.0 61.8 2560 V. C ONCLUSION
Spec2 This paper presents ATOM, an automatic topology synthesis
FE-GA 0.049 94.2 35.8 60.1 7304
Transistor VGAE-BO 0.091 102.5 42.1 64.0 4625 framework for opamps. To construct a concise behavior-level
ATOM 0.501 98.1 138.0 60.0 2752 topology space, we employ functional module decomposition
and leverage manual design expertise. We propose a novel
and an inadequate number of simulations to fully exploit the DAG representation and utilize DVAE to learn a continuous
performance potential of high-quality topologies. topological representation. Additionally, we develop freeze-
The behavior-level opamps are further mapped to the tran- thaw BO to intelligently allocate simulations to different
sistor level using a gm /id -based mapping method [12]. In topologies based on their predicted quality, thereby efficiently
this method, a gm is implemented as a differential pair or a exploring the topology space. Experimental results demon-
common-source amplifier. The transistor sizes are determined strate that ATOM outperforms state-of-the-art methods in
based on their gm /id values, which are optimized by BO to terms of success rate, optimization results, and efficiency.
meet the target specifications. General specifications can also
be addressed by incorporating them into the constraints of R EFERENCES
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