Advanced

Packaging
Fundamentals
for Semiconductor Engineers
Contents

Introduction . . . . . . . . . . . . . . . . . . . . . 4 Pillars . . . . . . . . . . . . . . . . . . . . . . . 33 Recent developments . . . . . . . . . . . . 61

The overloaded notion of Hybrid bonding . . . . . . . . . . . . . . . 35 Heterogeneous integration . . . . . 61
Heterogeneous Integration . . . . . . 8 Assembly processes . . . . . . . . . . . . . 36 Leadframes . . . . . . . . . . . . . . . . . . 62
Why advanced packages? . . . . . . . . 10 Basic flip-chip packaging . . . . . . . 36 Bonding . . . . . . . . . . . . . . . . . . . . . 62
Higher bandwidth . . . . . . . . . . . . . 10 Package-on-package assembly . . 37 Interposers and bridges . . . . . . . 64
Lower power . . . . . . . . . . . . . . . . . 12 Chip on wafer . . . . . . . . . . . . . . . . 38 Panels . . . . . . . . . . . . . . . . . . . . . . . 64
Package types . . . . . . . . . . . . . . . . . . 13 Adding interposers . . . . . . . . . . . . 40 Assembly . . . . . . . . . . . . . . . . . . . . 64
Through-hole vs. surface-mount 13 Passives, optical, MEMS, and other Thermal . . . . . . . . . . . . . . . . . . . . . 65
Edge leads vs. lead arrays . . . . . . 14 components . . . . . . . . . . . . . . . . . . . . 41 Reliability . . . . . . . . . . . . . . . . . . . . 66
Single component vs. multi- Thermal considerations . . . . . . . . . . 42 Other . . . . . . . . . . . . . . . . . . . . . . . 67
component . . . . . . . . . . . . . . . . . . 14 Design implications . . . . . . . . . . . . . 43 Standards . . . . . . . . . . . . . . . . . . . . . . 68
The confusing notion of an RDL . 15 Two very different scales . . . . . . . 46
Fan-in vs. fan-out . . . . . . . . . . . . . 16 From Wild West to
Advanced-package components . . 17 standardization . . . . . . . . . . . . . . . 46
2D, 2.5D, and 3D . . . . . . . . . . . . . . 18 Test considerations . . . . . . . . . . . . . . 48
Package substrates . . . . . . . . . . . . . . 19 Standard modifications for special
Material choices . . . . . . . . . . . . . . 20 cases . . . . . . . . . . . . . . . . . . . . . . . . 49
Building a substrate . . . . . . . . . . . 21 Reliability . . . . . . . . . . . . . . . . . . . . . . 53
Interposers . . . . . . . . . . . . . . . . . . . . . 23 Security . . . . . . . . . . . . . . . . . . . . . . . . 55
Interposers vs. chips, packages, Advanced-package
and PCBs . . . . . . . . . . . . . . . . . . . . 23 vulnerabilities . . . . . . . . . . . . . . . . 55
Different interposer materials . . 25 Information leaks . . . . . . . . . . . 56
Silicon interposers . . . . . . . . . . . 25 Control usurpation . . . . . . . . . . 56
Glass interposers . . . . . . . . . . . . 26 Fault injection . . . . . . . . . . . . . . 56
Organic interposers . . . . . . . . . . 27 Side-channel attacks . . . . . . . . . 57
Active interposers . . . . . . . . . . . 27 Reverse engineering . . . . . . . . . 57
Silicon bridges . . . . . . . . . . . . . . . . . . 28 Trojan horses . . . . . . . . . . . . . . . 57
Bonding . . . . . . . . . . . . . . . . . . . . . . . . 30 Counterfeiting . . . . . . . . . . . . . . 57
Wire bonding . . . . . . . . . . . . . . . . . 31 Attack mitigations . . . . . . . . . . . . . 58
C4 balls and bumps . . . . . . . . . . . 31 Encrypting intra-package traffic . 58
Thermocompression bonding . . 32 A fast-moving technology . . . . . . . . 60 ©2025 Sperling Media Group LLC/Semiconductor Engineering. All rights reserved.
No portion of this report may be reproduced in any form without written
permission from the publisher or author, except as permitted by U.S. copyright law.

2 3
Introduction

By Bryon Moyer
With the SE Staff
Designed by Jesse Allen Common in such a discussion are mentions of 2.5D or 3D packaging,
with those descriptions referring to the ways in which internal
Technical advisors:
components may be arranged.
• John Park, product management group director for advanced IC packaging at This starts with a discussion of package types as viewed from the
Cadence Design Systems
outside, moving inward from there to the basic components that
• Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA advanced packages integrate. After that it explores each of those
• Robert Patti, president and CEO of NHanced Semiconductors components in more detail. The bulk of the discussion will deal with the
• Gretchen Patti, senior member of technical staff at NHanced Semiconductors varying processes by which an advanced package can be assembled.

I ntegrated circuits have been housed in packages since the beginning The report wraps up by examining four topics that must accompany
of the semiconductor industry. The original idea was largely to protect any discussions of technology — how engineers design advanced
the delicate piece of silicon inside from the elements outside, but the packages, how they test them, the reliability implications of advanced
nature and role of packaging have evolved dramatically in the last packages in general, and any security implications.
decade. While chip protection is still important, it has become the least
Two related broad topics are addressed briefly, as well. The first is
interesting of the roles that packaging provides.
bonding. Although a necessary part of packaging, it is a big topic on
This eBook addresses the biggest changes in packaging, typically its own and one that will not be discussed in detail here. The second
referred to as advanced packaging. There’s no clear definition of what includes the various types of components that aren’t integrated circuits,
advanced means. Instead, the term broadly covers a number of possible but which may be included in a package. Optical components and
packaging scenarios, all of which are far more complex than traditional MEMS (microelectromechanical systems) are two prominent examples,
one-chip packaging. Advanced packages typically encapsulate multiple and each has its own set of considerations that can push outside the
components, but the means of assembling the unit can vary widely. scope of this eBook. So again, they are discussed at a high level.

4 5
 SPONSOR CONTENT

Introduction

Coverage focuses on techniques which will be defined and described, 3D Packaging vs.
largely in production today, since because they’re typically less familiar
they’re relatively stable. Developments to an electrical engineer. The goal is 3D Integration
since mid-2024 on are not included to keep this accessible and relevant to
because they typically deal with new anyone with a working knowledge of
ideas that are still in flux and haven’t semiconductors.
settled out yet. Semiconductor
Engineering will continue to refresh This topic also raises a question Integrated circuits (IC) are breaking traditional boundaries with advancements like 3D packaging
the content in future reports, adding about the distinction between a and 3D integration. But what sets these cutting-edge approaches apart, and how will they
any topics that have made it into chip and a die. In the past, there shape the future of IC design?
commercial production since the prior was no real distinction, because a
edition. package housed a single chip. The Improved Performance: Boosts efficiency
question is, however, does the chip
3D Packaging vs. 3D f

by reducing interconnect delays and

Our expectation is that readers are refer to the packaged product, or Integration—What’s the
enhancing thermal management
electrical/electronic engineers — is it simply another name for a die? Difference?
or at least that they have a good Some people use the latter definition, f Future-Ready Designs: With hetero-
grasp of basic engineering and while others now say a chip is the 3D packaging focuses on back-end
geneous integration rising, workflows must
semiconductor concepts. Electrical packaged unit. By that definition, an processes like stacking dies, wire bonding,
adapt to incorporate both IC and advanced
notions in packaging largely relate advanced package is likely to be a and using interposers for connectivity. 3D
packaging methods
to connections and signal integrity. single chip containing more than one integration, however, goes further by
Circuits or transistors, or any of the die. We have not tried to adjudicate merging IC logic and interconnects with Unlike traditional packaging, 3D integration
functions that may reside on the chips this debate and have tried to use the technologies like through-silicon vias (TSVs) requires precise accuracy at every level,
in the package, are not part of this words in ways that should be obvious redefining workflows to meet semiconductor
and hybrid bonding, enabling advanced
report. Readers are assumed to know from the context.
vertical stacking. These methods optimize market demands.
what processors, memories, and other
fundamental chips are. Finally, as this is a new area, there performance, power efficiency, and size,
are very many configurations and driving a shift in IC design. Learn More—Download the
Packaging also involves a wide range approaches to advanced packaging. Ebook Today!
of materials, and those may be less Most of them are in research; a few of Why IC Designers Should Ready to see how 3D packaging and
familiar to someone trained to work them are in commercial production,
with digital logic or analog circuits. So, but without any standards. The focus
Care About 3D Integration integration can transform your designs?
where helpful, this eBook will describe will be on those shipping in volume, The move from multi-chip modules (MCM) to Download “3D Packaging vs. 3D Integration”
any such materials in more detail. adding more in the future as they gain chiplet-based designs brings new challenges for insights, strategies, and technical details
Similarly, processing steps may use a traction. to understand the next era of IC innovation.
and opportunities:
number of arcane terms and brands,
f Increased Complexity: Requires tools
I'M INTERESTED
that manage concurrent, transistor-level
designs across multiple dies

Unleash Imagination cadence.com

6
 SPONSOR CONTENT

Introduction

The overloaded notion of We largely avoid the term here

as a buzzword with imprecise
Heterogeneous Integration connotations, other than the fact
that there are multiple things in a
Advanced packaging implements single package. All of what follows
what is often called heterogeneous could be considered heterogeneous
integration. Although liberally integration, depending on one’s
bandied about, the term has no strict definition.
definition, and various entities use it
in slightly different ways.

Some use it to mean integration of

more than one element in a package,
although this is infrequent because
it doesn’t really meet the definition
of heterogeneous if the components
are merely multiples of the same die.
Others use it to indicate that different
chips or chiplets are co-packaged
(where, loosely speaking, a chiplet
is a die that has some I/Os designed
to communicate with another die
within a package). Yet others refer
to the inclusion of non-electrical
components, such as optical.

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 SPONSOR CONTENT

Why advanced packages?

A dvanced packaging follows the age-old move toward increasing

integration. In this case, rather than integrating onto a single
chip, it’s integration of multiple components into one package. The
motivation for doing so ties directly into a few different trends,
although those trends are often intertwined. One is the increasing
use of chiplets, while another is the halting move toward co-packaged
optics. These two examples typify the two primary issues driving this
whole movement — bandwidth and power. Cost also may be a factor
motivating chiplets, but that’s specific to chiplets, and a fully costed
advanced package may still be expensive, despite the use of any
chiplets.

Higher bandwidth gives high-bandwidth memory (HBM)

its value — a much wider bus than
The bandwidth in this case refers to is possible on a PCB. Distances are
the speed with which components can also much shorter, permitting more
exchange data — particularly when aggressive signaling techniques.
accessing memory. Faster physical
This notion of how many signals to
communication mechanisms, such
run ties into the concept of beachfront.
as PAM4 and PAM8, are part of the
Beachfront is measured in terms
solution, but at this point increasing
of I/Os per square millimeter and
gains are hard won.
relates to the line/space rules inside
Given a set speed for a signal, another the package, as well as the ball
way to increase bandwidth is simply to dimensions of the dies. Although older
make more signals available. Printed chips had peripheral pads for I/Os,
circuit boards (PCBs, also known as modern chips have arrays of balls. The
printed wiring boards, or PWBs) provide first few rows of that array may be
a given set of line and spacing rules usable as related I/Os in a bus, but the
that limit the number of signals that number of usable rows is limited by
can run next to each other. Additional how easy it is to route inner rows out.
layers on the PCB can help with the
In theory, any ball can be routed
routing, but at some point costs
out, but when it comes to buses, the
mount, and longer, more tortuous
signals need to be as well matched
routes also hinder speed.
as possible to limit skews across the
Achievable dimensions inside a bus. Those considerations limit the
package are much more aggressive number of ball rows that can be part
than those available for PCBs, allowing of a single bus, which along with the
more signals. This is specifically what ball pitch determines how many I/Os

10
 Package types
Why advanced packages?

T
are available for a bus per mm2 of he semiconductor industry has developed countless types of
the edge of the die. Routing may be packages for integrated circuits (ICs). Most of them contain one chip
further limited if noise considerations
and serve both to protect that chip from the ambient environment
necessitate ground lines between
signals. and to achieve a means of attaching the chip to a PCB. We will not be
addressing most of those package types.
Lower power “Advanced packaging” is a vague and somewhat unhelpful term. At any
given point in time, the latest packaging technologies, whatever they
Reducing power is the other big are, qualify as advanced. So expectations of what that means today
motivator, and that relates directly to
the distances signals must travel. A
may change in the future. This report will narrowly define which types
longer trace requires more signaling of packages are being discussed.
energy to ensure that data travels
to its endpoint in good enough Through-hole vs. Surface-mount technology addresses
shape to be accurately received and that challenge by eliminating pins
interpreted. surface-mount that go through a board. Instead of
pins, solder balls are attached to
Many more signals will travel inside Older packages have pins intended the outside of the package. All such
a package than would be possible to go through a hole drilled in a components are placed on a board
on a PCB, but because distances are PCB. These are simpler packages for and run through a heat cycle that
measured in millimeters rather than simpler boards. They’re assembled by slightly melts (or reflows) the solder
centimeters, drive strength can be placing all the components on the top balls so that they make a clean
eased, saving energy. It’s possible that side of the board and then running
net energy could still be higher given it through a wave-soldering process,
the greater number of signals. In that where a “wave” of molten solder
case, the bandwidth motivation (if not gently wipes the bottom of the board,
simply the space savings) would be sticking to the appropriate pads and
the more important one, sacrificing being wicked up into the holes around
total power for higher performance. the package leads to form reliable
But even then, the power per signal connections.
will be lower. Fig. 1: Pin-grid array vs. ball-grid array.
This is a well-established technology, The left image shows the bottom of
and it’s relatively inexpensive. The a package with pins intended to go
downside is that only the top side of through holes in a PCB. The right
the board is available for components. image shows the surface-mount
The through-holes and solder wave equivalent, with solder balls that
make assembly on the back side mount to the surface of the PCB. Note
impossible. So this approach results in that the arrays don’t have to be fully
a low density of components. populated with pins or balls. (Sources:
Left: Liam McSherry, CC BY-SA 3.0,
via Wikimedia Commons; Right: ASE
Group)

12 13
Package types

connection to a pad on the surface are all located on the edge of the die, fewer connections to the PCB may be The confusing
of the PCB. That leaves the back and the resulting pins are at the edge necessary.
side of the PCB available for other of the package. notion of an RDL
components. The latter effect is related to a
Such an arrangement places a limit relationship established years ago Many packages include what’s called a
The types of packages considered on how small a die can be since between the number of gates on a redistribution layer, or RDL. The original
here typically have a huge number of bond pads on a die have a minimum chip and the resulting number of I/Os. concept was that of a few layers of
connections, and pin-grid arrays (PGAs) required size and spacing governed Called Rent’s Rule, it finds that as the interconnect for routing signals from
and ball-grid arrays (BGAs) provide two by the size of the wires, not by the number of gates on a chip increases, one pattern to another — typically
examples of high-lead-count package. silicon process. A very small circuit so does the number of I/Os — but from the lead or ball pattern of a chip
The former is a through-hole package; that needs lots of connections may not as fast. That’s because many package to a landing pattern on a PCB.
the latter is surface mount. need so much room for the bond pads connections remain internal to the This becomes particularly important
that the die size is determined only by die. when the connection pitch on the
This eBook focuses only on surface- the pads, not the circuitry on the chip. package is too tight for line and space
mount technology, and the BGA is the Such a die is said to be pad-limited. The same effect happens with the rules on a PCB. An RDL is necessary
most widely used style of package that package. If two chips that might for taking those signals and spreading
meets the remaining criteria. For hundreds or thousands of otherwise be in separate packages them out.
connections, leads on the edge have connections between them,
would result in enormous packages those connections will disappear from
Edge leads vs. lead arrays and horrible performance due to the PCB because they’re made inside
That’s the general idea, and it applies
in most advanced packages. But many
the length of the connections and the package instead. elements can serve to reroute signals,
Older packaging technology works leadframes. Instead, modern large including interposers and package
by using wires to attach chip bonding packages have arrays of leads — balls substrates. Technically, these act as
pads to a leadframe that routes the in the case of a BGA. Array leads can RDLs. But the term RDL seems to have
signals from the die’s bond pads to derive from edge pads on a die if a more specific usage that refers to
the package pins. Those bond pads the die is extremely large, or the die the addition of routing layers above
itself can have an array of balls with the metal layers of a die, added after
circuitry skirting around them. die passivation, or on the backside of
the die, rerouting through-silicon vias
Single component vs. (TSVs).

multi-component In general, they have a few layers built

up out of organic resin that provide
nothing more than a rerouting of
There are many possible reasons for
Fig. 3: The left image shows two chips signals. This more limited definition
wanting to integrate multiple chips
that share five connections. If those of an RDL doesn’t permit component
into a single package. The resulting
two chips are co-packaged together, embedding passives or other
Fig. 2: Top view of a pad-limited die. size will use less space on a PCB
then those five shared connections components in a way that might be
The size of the die is set by the pads on than if multiple packages were used.
are made inside the package and possible with interposers.
the periphery. Shrinking the circuitry Performance can be higher and
in the middle would not result in a more efficient because of shorter disappear from the package’s leads.
smaller die unless the pads were connections. And in many cases,
removed.

14 15
 Advanced-package components
Package types

Fan-in vs. fan-out

O
up to about 1.2X the size of the chip lder package styles tend to have few components: a substrate,
is called chip-scale. And because in a leadframe, a chip, and then molding compound (for a plastic
this situation the signals route from
Because older technology runs wires package) or some other enclosure. Advanced packages are based on
from die pads to a leadframe, the the edges inward under the die, the
technique is called fan-in. this architecture, but they add a few elements:
signals have nowhere to go but away
from the die. The package footprint • Substrates provide the connection • Microbumps are even smaller
The opposite is fan-out, where some
on the PCB is larger than the die it between the package contents and connections between a die and
leads are routed away from the die,
contains. In current parlance, the the PCB to which the package will another die or an interposer.
making the package larger than the
signals fan out from the die. eventually be attached.
die (even if some signals fan in as • Depending on the interposer
Advanced packaging techniques well). This may be necessary even • Balls made of solder form the PCB material (discussed below), bridges
include the use of RDLs that can for a single chip because PCB design connections. may provide connections between
route the signals anywhere. If the rules require connections to be much the components mounted to the
• Interposers act similarly to
die has few connections, they can farther apart than bond pads on a interposer.
substrates, but they typically can
be routed under the die, with the chip.
accommodate tighter spacing
resulting package being only slightly between metal lines, and bumps In addition to these basic elements,
Finally, the advanced assembly additional components for managing
larger than the die itself. Called can form many more connections
processes include manufacturing of heat, for example, may be added.
chip-scale packaging (CSP), it’s the than balls.
panels. These are larger rectangular
smallest possible practical packaging
boards that effectively act like PCBs,
technique, given there’s no way to
but with more aggressive dimensions.
go smaller than the die. Anything
Panels haven’t yet achieved
mainstream status.

In summary, then, advanced packages

for the purposes of this eBook will be
characterized as:

• Using surface-mount technology

(probably BGA or related);
• Having bump arrays rather than
edge connections;
Fig. 4: Fan-in vs. fan-out. The left image • Encapsulating multiple
shows all signals being routed towards components (with the exception of
the center of the package, which CSP); and
is possible because of the limited
• Having a fan-out RDL or some
number of signals. The right shows
other element that routes signals
fan-out, with some signals routing out
away from a die.
beyond the die. With fan-out, some Fig. 5: Basic advanced-package components. Like all packages, it contains a substrate.
signals can still route inward. It also includes an interposer on which components are mounted and routed to each
other. Microbumps connect a die to an interposer, bumps connect the interposer to
the substrate, and balls connect the substrate to the PCB.

16 17
 Package substrates
Advanced-package components

2D, 2.5D, and 3D

T
3D refers to the literal stacking of he substrates used in packages resemble PCBs, although they’re
components atop each other. The most similar to high-density-interconnect (HDI) PCBs. Like PCBs, they
best example of this today is HBM,
When integrating multiple consist of alternating layers of a dielectric and metal. In this manner,
components in an advanced package, which consists of several memory
chips stacked to look like one large they also resemble the back-end-of-line (BEOL) of a semiconductor,
the industry has developed a notion which also has alternating layers of dielectric and metal. But substrates
of dimensionality that isn’t strictly memory. But AMD, for example, also
accurate but helps to describe how uses the approach to place its V-Cache feature an organic dielectric rather than an oxide. The differences
things are arranged in the package. above a compute die, and more between PCBs and substrates are more about dimensions than
It’s unusual to see 2D, but that would heterogeneous examples like this are materials.
refer to the default arrangement in a expected in the future.
standard package, where the chip is Substrates typically start with a may be necessary. Vias provide
Real-world designs tend to feature a
placed directly on the substrate. 2.5D core, which is a rigid layer of organic connections between metal layers,
combination of 2.5D and 3D, often
involves multiple chips laid out on an dielectric with copper on both sides. with three types:
referred to as 3.5D. For example, one
interposer. That interposer lies above Construction is additive, meaning
might have one or more compute
the main substrate, so there’s a bit of that the substrate is built by adding • Through (or through-hole) vias are
chiplets and one or more I/O chiplets
vertical going on — a half-dimension’s materials — in this case, building accessible on both sides of the
arranged next to each other along
worth. up additional layers of dielectric finished substrate.
with HBM stacks. Figure 5 and Figure 6
and metal. This leads to the other • Blind vias are accessible only on
illustrate such a combination.
descriptive name for the process: a one side, terminating on an interior
build-up process. layer.

The metal layers act in two capacities. • Buried vias start and end on
The obvious one is to route signals internal layers and aren’t accessible
from a die connection inside the from outside the substrate.
package to a connection for soldering
Micro-vias are simply vias with smaller
onto a PCB. Depending on how those
diameters — below 150 µm. These
signals route, one or more layers
allow greater via density, but they’re
harder to build, requiring laser
drilling and higher precision. With a
narrower “barrel,” the aspect ratio
(ratio of height to width) must also
be considered since plating into high-
aspect-ratio holes is more difficult.

The other role that metal layers

provide is as power and ground
Fig. 7: A cross-section of a package planes. They primarily contribute to
substrate. Much like a PCB, it consists power stability for the component(s)
Fig. 6: HBM as a 3D stack in an advanced package. A single HBM unit contains of layers of metal separated by layers in the package. But for high-frequency
multiple individual thinned-down memory dies that communicate through small-pitch of organic dielectric. Vias of different signals or high-performance circuitry,
microbumps. TSVs carry signals from the top die down to the base die. As shown, the types allow connections between metal where noise is the enemy, the
processor is next to the HBM in a 2.5D configuration. layers.

18 19
Package substrates

planes act as shields that keep metal FR-4 (also written FR4) is by far the application. The sheet of dielectric surface. That process can be done
layers from interacting through the best-known resin for PCBs. The “FR” may come with a layer of copper. either chemically or using plasma.
dielectric. Ground lines also may be stands for flame-retardant; the 4 was The latter produces a cleaner, more
routed on a single layer between assigned by the National Electrical In addition to its lower dielectric uniform result but costs more.
signals to mitigate any crosstalk Manufacturers Association (NEMA). It’s constant, it also has a coefficient of
between the signals. a composite, consisting of a fiberglass thermal expansion (CTE) closer to
cloth impregnated with epoxy. that of copper and other materials on Building a substrate
On PCBs, such layers are also essential the substrate. As a result, repeated
for creating strip- or microstrip- For higher performance, BT epoxy thermal cycles are less likely to lead The steps for building a substrate are
lines with controlled impedances. (which stands for bismaleimide- to cracks and other defects. It’s straightforward conceptually — start
Substrates’ smaller dimensions make triazine) is available. It’s more tolerant helpful for packaging circuits that with a core and add layers, patterning
such structures less common because of high heat as measured by the glass must demonstrate high reliability. The and drilling as you go. Buried vias
there will be fewer signals acting as temperature (Tg), the temperature cost is higher, however, than simpler and micro-vias can go on any layer,
transmission lines. A 6 GHz signal, at which the resin starts to reflow materials and processes. blind vias go on an outside layer, and
for example, has a wavelength of and lose structural integrity. It also through-hole vias are drilled once all
around 50 mm, so traces longer than provides a lower dielectric constant, Note that an entire substrate need layers are in place. A more detailed
about 25 mm (a half-wavelength) which helps protect against inter-layer not consist of the same dielectric. recipe would look like:
bear consideration as transmission signal crosstalk. Different layers can feature different
lines when carrying signals of that resins, depending on the needs of the 1. Start with a core metallized on
frequency. Only the largest packages Both of these materials are available signals they support. both sides.
have dimensions in that range, and in a form called prepreg, which stands 2. Drill and plate vias:
few signals do. Careful routing can for pre-impregnated. A fabric matrix is Vias in PCBs are traditionally made by
mechanical drilling, but the smaller a. Drill mechanically or with a laser.
keep the traces low enough. But if impregnated with resin and partially
controlled impedances are necessary, cured to stabilize it. Prepreg thus dimensions of substrate vias make b. Desmear and clean.
the ground planes can assist with that. makes a convenient layer that can be laser-drilling more common. Unlike c. Apply copper seed.
laid down and then fully cured after holes drilled for through-hole pins,
d. Electroplate.
it’s in place. Once all the layers are in where solder wicks down into the
Material choices place, both heat and pressure provide hole, or for mechanical attachment, 3. Pattern the metal:
thorough curing and bonding between which needs no material in the hole, a. Apply photoresist.
Substrates have two main materials layers. vias must conduct between layers.
b. Expose pattern.
that remain after processing, the That’s most commonly handled with
dielectric and the metal. The metal is A more recent material from a electroplating, where a small amount c. Remove developed photoresist.
overwhelmingly copper, with solder company called Ajinomoto is of copper in the holes acts as a seed d. Etch copper.
making connections. In a lead-free ABF (Ajinomoto build-up film). It layer, and then copper is deposited e. Remove all remaining
environment, SAC (tin/aluminum/ provides improved dielectric in a bath with the board electrically photoresist and clean.
copper) solder dominates. and thermal properties for high- connected as a cathode to attract the
performance signals. It comes in a copper. 4. If more layers are needed, add
In contrast with the metal, the roll, encapsulated between an ortho- another layer of resin and copper.
dielectric provides more choice. The phenylphenol (OPP) film on one side, When drilling holes mechanically or 5. Repeat steps 2 and 3 until all layers
two most common ones are different which is removed prior to application, by laser, nearby resin tends to melt, are in place.
forms of epoxy resin that are curable and a polyethelene (PET) film on the causing a “smear.” For substrates with 6. Bond layers together using
by heat (also known as thermoset). other side, which is removed after four or more layers, a desmearing pressure and heat.
process is necessary to clean up the

20 21
 Interposers
Package substrates

S
The steps and materials shown are for ubstrates have been standard for packages for years, but they
the most common types of substrate. primarily provided a surface on which to mount a die. Today,
Other materials may be used for the
substrates that also reroute signals are well established. In theory,
core, such as ceramic or metal. Other
special-purpose resins may be used, one could place more than one chip on a substrate, but in practice,
as well. When making choices on the resulting substrate would be too large if the number of die-to-die
the materials to use, cost, reliability, connections were too high. And some of today’s chips have thousands
thermal management, signal integrity, of connections. It’s impractical to route that many signals on a standard
and power integrity must be balanced organic substrate in a reasonable (or manufacturable) size. In addition,
according to the needs of the
signal routes are likely to be long and circuitous, increasing the power
application.
needed to communicate with high reliability.
This has been a primary motivator of the use of interposers. Technically, an
interposer is any kind of intermediary or shim that makes or redirects connections
between something on one side and something else on the other. In this case,
silicon chips, passives, and other components lie on one side and the substrate lies
below. Connections from the chips are through microbumps; connections to the
substrate are through C4 bumps (both discussed below). This type of interposer is
called passive. Silicon interposers also make possible active interposers that contain
transistors.

Interposers vs. chips,

packages, and PCBs
Interposers create an additional layer
of connectivity hierarchy. At the top
of that hierarchy is the die itself with
its on-die connections. Below that is
the interposer, which interconnects
the components inside the package.
Below that is the substrate, which
makes connections between signals
that need to be visible outside the
Fig. 8: Process for manufacturing a typical substrate. Starting with a core, Fig. 9: An interposer, top view and package and the package pads. The
layers are successively added, drilled, and patterned until the layers are edge view. Components lie atop final level is the PCB itself.
all in place. The final substrate layers are bonded together using heat the interposer connected through
and pressure. microbumps. Layers within the Each of those levels has different line/
interposer route signals between space and pad densities, with chips
the components and to bumps for having the highest density and PCBs
connection to a package substrate the lowest.
below.

22 23
Interposers

Interposers bring four fundamental if taking into account what the cost addressed through careful design. organic-material build-up. Adding to
benefits over package substrates and would be using multiple packages But that design brings package, the cost, a single interposer must be
PCBs. instead of integrating into a single interposers, and chips together into large enough for all of the silicon it will
package. one big co-design effort with many carry, making it larger than the sum of
• The tighter metal and pad moving parts. all of the silicon sitting atop it. So cost
dimensions allow for many more Interposers don’t introduce new per square micron is lower than that
signals to be routed either between thermal issues themselves, but of an advanced die, but an interposer
in-package components or to packages using them are putting more Different interposer will have more square microns than a
package balls. silicon into a single package, which
always has the potential to introduce
materials typical die.
• More inter-component connections
mean fewer signals leave the heat challenges. Those issues can be Building a passive silicon interposer is
addressed by ensuring, for example, Interposers are primarily a means to like building a die, but using only the
package. route signals. The material used to
that two high-power silicon chips metal layers. As such, many layers can
• Die-to-die connections travel aren’t stacked atop each other or even build them therefore depends less be created. But each layer adds cost,
shorter distances and therefore placed side-by-side. on their electrical characteristics and so minimizing layers while ensuring
have less signal-quality more on their physical nature. Critical adequate signal routability with good
degradation. One classic challenge is placing HBM parameters include isolation between signal quality is a design optimization
• The shorter distances mean signal memory, which like all DRAM is signals, thermal conductivity, and CTE challenge.
drivers can reduce the energy highly sensitive to heat, as close as as compared to that of the silicon
needed to drive the signal and possible to the processor chip using above and the substrate below. One frequent component on a silicon
the voltage swing, both of which it. The connections need to be as interposer is the through-silicon via
reduce system power. short as possible, and yet that brings Silicon interposers (TSV), which routes a signal from one
the memory chips closer to the hot side straight through to the other. This
The downsides of using interposers processor, potentially compromising The most common interposer is more typical for power and ground
are their cost, thermal considerations, memory performance. material is silicon. The idea is that pins, but it can be used for signals,
and design complexity. Cost depends silicon manufacturing, depending on as well. TSVs have “keep-out” regions
on the material used, but obviously Both cost and thermal concerns which process node is being used, around them, where TSV creation
having an interposer costs more relate in general to a third concern allows far greater wire density than may affect the neighboring silicon.
than not having one. Still, the cost — complexity. Cost, thermal, and the organic materials typically used A passive interposer never uses
comparison is likely more favorable any other issues typically can be for PCBs and package substrates. silicon’s semiconducting properties,
Silicon interposers are thus made however, acting only as a medium for
in semiconductor fabs, with connections. So the preponderance of
Interposer/ TSMC currently being the biggest TSVs doesn’t practically limit passive-
Die Substrate PCB
Bridge manufacturer of them. interposer layout. It does, however,
greatly affect the cost. Using thinner
Min. metal pitch (µm) 0.02 – 0.04 4 50 250 Leading-edge silicon processes aren’t silicon can lower that cost because
necessary for interposers; they tend the TSVs can be shallower, but
Typical number of to remain on nodes such as 65 nm or carrier wafers — wafers whose sole
9 4 8 15
metal layers 45 nm. That keeps their cost below purpose is to act as a more substantial
what would be necessary for a leading holder for a thin wafer — are
Table 1: Connectivity comparison between chips, interposers, package substrates, and node, but it’s still more expensive required beyond a certain thinness
PCBs. Dies are the densest, PCBs are the least dense. Adding layers raises routability per area than would be necessary for to help maintain structural integrity
but adds cost and can reduce signal integrity due to additional vias.

24 25
Interposers

throughout the build process. The reticle, called a scanner, repeatedly too. Its large-scale manufacturing in Active interposers
carriers are removed when finished. exposes the wafer, with the platen large sizes means that both wafers
holding the wafer moving one reticle and panels are available for use as All three materials discussed are
A typical piece of silicon being distance after each exposure. Over interposers. vying for roles as passive interposers,
manufactured is limited in size. For time, the entire wafer moves past the serving only to make connections.
most dies, the limit is set by the size reticle. The two primary features to build But silicon is a semiconductor, and
of the mask-holding apparatus, called are the through-vias, here called it’s possible to build circuits directly
a reticle. Most dies are far smaller In most cases, each exposure through-glass vias, or TGVs, and the into the interposer itself, making it an
than a reticle, and masks can include creates an independent chip. But metal connections. Creating and filling active interposer.
multiple dies within one reticle to for interposers (or very large chips), vias is well established, and copper
improve wafer throughput. Other multiple exposures are required for can be plated onto the glass. Glass No such approach is yet in production,
high-performance chips push to the a single chip. That means that the interposers are still largely being but discussions include putting
limit of the reticle size. boundaries between the exposures researched. None is in high-volume power management and I/O circuits
must somehow be stitched together. production today. near their respective signals in the
A very few active chips exceed the That’s easier to do at the relaxed interposer. This will increase the
reticle size, the most obvious case dimensions used for interposers, Organic interposers cost of the interposer, because it
being Cerebras with an entire wafer but it’s still a critical part of the now needs front-end-of-line (FEOL)
acting as a single “chip.” But silicon manufacturing process that a processing as well as BEOL.
The high cost of silicon interposers
interposers can also exceed the reticle silicon fab must perfect. Means of
has developers moving in yet another
limit, although TSMC currently limits building larger interposers are under Given the older process nodes
direction, this time to organic
them to three reticles in size. development. If they prove successful, used for interposers, these won’t
interposers. These are largely the
they would eliminate the need for be leading-edge high-performance
During photolithography steps, where same as PCBs and package substrates,
stitching. circuits, but rather ones that can
patterns are exposed through masks except that the features are much
smaller. Metallization leverages either remove some circuitry from
onto the wafer, each reticle is a single Glass interposers the chips atop it, or remove an entire
exposure. The machine holding the equipment used for silicon rather
than for PCBs, since the latter aren’t chip outright. Depending on routing
The cost of silicon interposers has capable of the necessary dimensions. density, it may be that the circuits
motivated the use of glass interposers. add no area to the interposer, so the
The manufacturing process for glass The fabrication of organic substrates increased material cost should be
is very different from that of silicon, is still in early days, and it’s seen some limited to the FEOL processing. But full
and it introduces some limitations. But production. But it hasn’t yet taken costing will also rise somewhat due
it brings benefits — including better over from silicon. Ultimately, if glass to, for example, the need for more
signal isolation — for some designs. and organic interposers take off, the extensive testing to ensure a known-
demand for silicon interposers should good interposer.
“Glass” is a broad term, and it includes fall to only those designs that require
Fig. 10: Multi-reticle interposer. When many variations with different the tightest dimensions or ones
patterning the interposer, three properties based on additives in requiring active interposers.
different exposures are required in this the glass. Many of these are kept
example. Where the exposures meet, as trade secrets. Corning’s process
special care must be taken to ensure for producing strong glass used
that any signals crossing the boundary in cell phones and other mobile
are stitched together. devices serves well for interposers,

26 27
Silicon bridges

S ilicon interposers have applications limited to those that can recover A silicon bridge is a very simple The silicon technology used for
the advanced packaging cost. But the cost of a silicon component is silicon die that requires only BEOL building the bridge is capable of very
processing. That said, they’re fine lines. The limits on precision
famously related to the area of the component. And silicon interposers
proprietary, and the manufacturing often are not determined by the
are very large compared with typical chips. Silicon bridges take the details aren’t public. Intel’s version bridge itself, but by the alignment
interposer concept and cut it down so that it uses a few small pieces of is probably best known, called an of the bridge within the cavity. The
silicon rather than one big one. Embedded Multi-Die Interconnect tolerances on machines placing such
Bridge (EMIB). Amkor, ASE Group, components tends to be much looser
Instead of using a silicon interposer, bridges are embedded into an organic Samsung, and imec also have been than the line spacing on the bridge.
interposer or substrate. The manufacturing flow has bridge manufacturers sending working on bridges. Planarity also can limit the bridge size.
bridges to the interposer or substrate makers, who do the embedding. The
completed interposer or substrate then goes to the packaging houses that perform Embedding the bridge in the
the assembly. interposer requires:

1. Building up the layers of the

interposer up to the final layer.
2. Before encapsulation, creating
cavities in the substrate where
the bridge will go. Intel has some
patents on cavity creation to
improve cost and turnaround as
compared to typical laser ablation.
3. The bridge is placed in the cavity
and held there by adhesive.
Alignment is critical.
4. The final substrate layers are built
and other typical subsequent
operations such as drilling are
performed.

Fig. 11: Silicon interposer vs. silicon bridge. A silicon interposer Fig. 12: Cross-section of a silicon
uses a large silicon area, whereas a bridge puts silicon only where bridge. The bridge is embedded into
the interconnecting signals are. the package substrate.

28 29
Bonding

B Wire bonding
onding refers here to the attachment of a die to a substrate or end, which causes the end of the wire
attaching one substrate to another (including PCBs, package to form a ball that can then be placed
on the pad. Any of these bonding
substrates, and interposers), as well as the signal connections. Many By far the most prevalent bonding
techniques involve some type of techniques may involve a combination
techniques are available for creating these bonds, and their details of pressure, heat, and ultrasonic
exceed the scope of this discussion. The goal here is to provide an adhesive between the die and the
substrate. A eutectic bond may be vibration to soften the wire, scrub
overview of the different bonding techniques, highlighting those used formed to improve both stability and the pad, and form a solid, reliable
more often for advanced packages. thermal conductivity. A eutectic bond connection.
is formed when an intermediate layer
For traditional packaging, die attach and making signal connections are two Although there’s no formal definition
of a metal alloy is placed between
separate steps. With more recent packaging techniques, such as flip-chip, the signal of “advanced” packaging, wire bonding
the die and substrate and heated.
connections become the die bond, although underfill materials improve mechanical isn’t generally considered an advanced
The “eutectic” nature of the material
and thermal stability. technique. Early, less-expensive
means that the two metals in the alloy
versions of die stacking still may use it
individually have higher melting points
as long as each die is smaller than the
than the combined alloy, and once it
one it rests on so that the underlying
melts, it does so all together rather
die’s pads are exposed.
than having some intermediate phase
when there are solid and melted parts
Although wire bonding is less
mixed together.
expensive, it limits the number of I/
Os available based on clearances
The wire bonds themselves can be
necessary for creating the wire bonds,
attached using several techniques.
where a machine attaches each wire
Wedge bonding uses pressure to
to a pad on either end of the wire. It
force the wire down onto the pad,
therefore can’t be used in applications
squishing it into a wedge shape. It’s
requiring high communication
directional in that the wedge must
bandwidth.
be aligned with the direction of the
wire to its other end. Ball bonding
lacks that requirement, making it C4 balls and bumps
faster and easier. In that case, a
wire protrudes from the bonding For higher connection density,
equipment and is heated briefly at the particularly in BGA packages, flip-
chip assembly has become the norm.
It’s so-named because, unlike with
wire bonding, a die is flipped over
with the active layer close to the
substrate. Instead of wires forming
Fig. 14: 3D die stacking using wire the connections, solder balls serve
bonds. This is a less expensive way to that function.
Fig. 13: The primary bonding techniques. With wire bonding, the die and signals stack chips, but it requires the upper
are bonded separately. For the remaining techniques, the signal connections chips to be smaller than the lower
form the die connection as well. ones.

30 31
Bonding

After a die has completed processing, Thermocompression helps dissipate heat better than sometimes called the stand-off. If
solder balls are formed on the die standard microbumps can. the bumps are too small, then that
pads. The substrate pads may receive bonding gap will be too narrow to admit the
some flux, and then the inverted die The tradeoff is that this isn’t a batch underfill material.
is aligned and placed so that the balls Standard flip-chip bonding is procedure in the way a reflow oven
land on the pads. The temperature is inexpensive and quick, but it has is. Instead of bonding a tray-full of Pillars have stepped in to provide
briefly raised in a reflow step, which some drawbacks. Because reflow chips all at once, the bonding tool — better-controlled pitch and stand-off
causes the balls to partially melt and is performed in an oven, the entire which is also more expensive than control. Unlike a sphere, a cylinder
bond the die to the substrate. Because board heats up, and thermal the tools used for microbumps — can have independent heights and
of the carefully engineered way this mismatch issues may weaken bonds bonds each chip individually. The diameters, providing two degrees
process proceeds, such connections or cause warping as everything cools reduction in throughput makes this a of freedom. Pillars and balls can
are called controlled-collapse chip back down. If the die or board isn’t more expensive process that’s better even be used together on one die
connections, or C4. perfectly flat, then some bonds may tolerated with high-margin devices. if it partially overlaps another die,
be weak. In addition, metals such as requiring the short reach of a bump
This technique can apply at several to the underlying die and then longer
levels and with connections of varying
aluminum form oxides, which must be
breached to get a good connection.
Pillars pillars (sometimes called columns) to
size and density. At the bottom of reach the interposer where there is no
the BGA package, balls form the One solution to this is Microbumps cannot be made underlying die.
connection to a PCB. Inside the thermocompression bonding (TCB), arbitrarily small. One issue is that,
package, bumps form connections which applies heat and pressure despite the controlled nature of The process of building pillars
between the die and substrate. Those chip-by-chip from the top. It can be the solder collapse during reflow, resembles that for building bumps.
bumps are smaller than the balls on used to bond multiple dies in a stack the exact profile of the finished The difference is the step where the
the outside of the package. Finally, or to bond a package to a board. In connection isn’t well controlled, copper pillar is added, as Figure 16
for 3D stacking, where one die stacks the latter case, instead of reflowing limiting how close together they can shows.
atop another, even smaller bumps by heating the entire board, only the be without interfering with each other.
called microbumps are employed, chip and its balls are heated, which The other challenge is the fact that the
made possible by the finer lines and eliminates the warpage issue. The bump size also determines the gap
spaces that silicon technology permits. applied pressure helps to ensure a between the die and the substrate,
reliable bond, breaking through any
Immediately after a die is bonded, oxides and forcing surface compliance
only the metal connections provide between chip and board to combat
mechanical adhesion, and this any warpage. It’s typically done with
can result in reliability issues as copper and aluminum but also can be
temperature and other challenges performed using gold.
may cause cracks or outright breaks
in the solder. To stabilize things, an HBM uses thermocompression Fig. 15: A die partially overlapping
underfill material is applied after bonding extensively to bond the die another die to which its attached can
bonding to fill the gap. The material stack. In addition to addressing the theoretically use bumps and pillars to
wicks under the die, and it helps with above issues, it also reduces the manage the two different standoffs.
CTE mismatches and the dissipation of gap between the dies in the stack, This would challenge the achievable
heat from the die onto the substrate. resulting in a shorter stack. It also height of pillars with good yield. Die,
pillar, and bump sizes not shown to
scale.

32 33
Bonding

Hybrid bonding It’s a challenging process in practice,

however, because all pads must be
The latest hot topic in advanced co-planar, and surface preparation
packaging is hybrid bonding, used is key to a reliable connection. It’s
primarily for die-to-die connections, been used in a limited number of
including those made prior to wafer applications such as newer flash
dicing when bonding wafers to wafers memory and some image sensors, but
or dies to wafers. Instead of adding it hasn’t achieved widespread use and
material like solder to form the is subject to much ongoing research
connection, pads and the surrounding and development.
oxide are brought into intimate
Each of these interconnect
contact, making a connection with no
technologies permits a different size
intervening materials. The “hybrid”
connection (e.g., ball diameter) and
name refers to the fact that it’s both
pitch. Most have a range between
oxide and metal forming the bond.
what’s in widespread production and
The metal pads are recessed slightly, the leading edge.
causing the oxide to bond first, with
the metal pads following suit. It’s
intended to improve the connection
quality and electrical performance by
eliminating the solder. Only the pad
materials from the two chips make
the connection. The bonded oxide
provides mechanical strength.

Wirebond
Ball Bump Microbump Hybrid
pad
Diameter
25 – 50 250 – 800 50 – 100 30 0.3
(µm)

Pitch (µm) 50 – 100 300 – 500 50 – 150 10 – 50 0.4 – 1

Fig. 16: Steps to create solder balls or bumps and copper pillars. The steps are Table 2: Comparison of interconnect sizes and pitches. The low end tends to reflect
mostly the same. It’s primarily the materials that change, with balls/bumps advanced processes that may or may not be in high-volume production.
simply reflowing solder into a ball while pillars do the same with solder atop the
copper pillar.

34 35
Assembly processes

C ompared with silicon manufacturing processes, packaging is much Illustrated in Figure 17, a die with balls attached is placed face down on the
less regimented. A given silicon node available from a foundry (or substrate following the deposition of solder flux onto the substrate. A reflow
step melts the solder to form a tight connection, after which the flux is removed.
the manufacturing division of an integrated device manufacturer, or
Underfill then closes up any gaps between the die and the package for better
IDM, such as Intel or Samsung) is typically a fixed formula. For the mechanical stability. A final curing step completes the process.
most part, everything made on that process will go through the same
sequence of steps.

Packaging is, at least at present, more For a given process, several key
flexible. Some manufacturers have a parameters will vary. They include
few well-known processes, but each the number of layers available in a
company capable of such packaging is substrate, interposer, or RDL, the
likely to have its own version of those maximum size interposer (sometimes
same processes. For example, Amkor’s expressed in multiples of a reticle),
process named HDFO is roughly and the bonding pitch. The latter is
equivalent to TSMC’s CoWoS-R. Just a function of the type of bond used
as a given silicon node will differ in its as well as the capabilities of the
details from foundry to foundry, the manufacturer.
assembly steps will vary at different
outsourced assembly and test (OSAT)
houses. Basic flip-chip packaging Fig. 17: Flip-chip packaging. A bumped die is placed face-down on the package
substrate. The solder is reflowed, underfill is added for mechanical stability, and then
It’s also a time of rapid change, and Although single-chip packaging isn’t the whole unit is cured.
the industry has not yet settled the focus of this eBook, advanced
into neat, tidy processes. Each techniques largely derive from basic
customer may want something flip-chip techniques, so understanding
slightly different, and manufacturers that process will make the other ones Package-on-package
are accommodating them as much easier to grasp.
as possible. This report will review assembly
some of the better-known branded
processes from TSMC and Intel, but One of the simpler approaches
they don’t represent all of what’s to 3D assembly is to stack chips
available or possible. that are already in packages. Such
approaches are often named with
PoP (for package-on-package) in
the brand. One specific application
of this is for placing a DRAM chip
above a logic chip. This is one Fig. 18: Package-over-package assembly.
version of what TSMC brands InFO. If the top die isn’t larger than the bottom,
then an RDL may be necessary. The top-die
connections reach the board or bottom die
through vias, being routed to the appropriate
place using an RDL if necessary.

36 37
Assembly processes

Chip on wafer The first builds the RDL on the Intel’s Foveros process is another
carrier wafer before placing the variant intended for bonding two dies
One of the earliest means of connecting dies in a package is to use a wafer as a pre-singulated dies, bumps-down, (or one die and an active interposer)
carrier on which an RDL can be built, a technique branded CoW by TSMC. Two onto the carrier. There they can be face-to-face. The bottom die will
examples are shown below, illustrating two possible approaches to the assembly over-molded into what’s effectively a be facing up, so it connects to the
process. reconstituted wafer. At that point, the substrate using TSVs.
carrier wafer can be removed, balls
created, and the wafer singulated.

The other approach places the dies

upside down on the carrier wafer
before the over-molding. Once the
carrier is removed, the RDL is built,
balls are formed, and then finally the
reconstituted wafer is singulated.

Fig. 20: Intel’s Foveros process. It connects dies or chiplets face-to-face.

Fig. 19: Two ways of implementing a chip-on-wafer process. In the top example, the
RDL is built before the dies are placed; in the other, the RDL is built after the dies are in
place.

38 39
 Passives, optical, MEMS, and other components
Assembly processes

Adding interposers
The prior approaches added only
T he focus of this report so far has been on integrating multiple silicon
dies into a package. But other components also can be included,
with passives being the most common.
RDLs to route signals to balls. Adding
interposers to the mix creates yet Passives include capacitors (the most common, used for decoupling
more routing flexibility. One well- to reduce noise), resistors, and inductors. The latter are likely only in
known example from TSMC, CoWoS,
has three variants, depending on the
packages that include radio-frequency (RF) capabilities. Resistors are
nature of the interposer. CoWoS-S less common, and can serve for signal termination.
is for silicon interposers; CoWoS-R
Modern resistors and capacitors transition between the fiber and
implements an organic RDL; and
are exceedingly small, making it the optical receiver or transmitter is
CoWoS-L employs small chips whose
possible to embed them into organic important for minimizing light loss,
function is to provide routing. The
interposers and substrates. Capacitor so the angle at which the fiber enters
latter resembles a silicon bridge
modules from companies such as is important. The assembly process,
except that it also can include vias
Saras make possible the integration of if done manually, fiber-by-fiber, can
down to the substrate.
a network or collection of capacitors be slow and expensive. The use of
with a single component, rather than connectors forming an array of fibers
dozens or hundreds of individual that sit into so-called V-grooves can
capacitors. simplify the process.

Optical and MEMS components are Some MEMS components also have
more typically mounted atop an important alignment considerations.
interposer or substrate. It’s possible Earlier accelerometers, for instance,
to do so in the same manner what’s typically handled only one dimension,
done with another die, but alignment meaning that three would be required
may be more critical. for covering all three degrees of
freedom (x, y, and z). Ideally, those
Optical components typically involve three would need to be carefully
ports for fiber in the package. That aligned to be oriented precisely 90°
from each other. Depending on the
unit, some may have the capability
of calibrating out small orientation
errors.

Modern accelerometers (as well

as other navigational units such as
Fig. 21: Packages with substrates. Processes such as CoWoS-S use silicon for the gyroscopes and magnetometers)
Fig. 22: An embedded passive integrate all three dimensions into
interposer; those similar to CoWoS-R employ organic interposers. The CoWoS-L
component in a package substrate. a single die, where orientation is
approach includes an interconnect chip that resembles a silicon bridge.
This would typically be a resistor or guaranteed by design. That makes the
capacitor added during the build-up orientation of the die itself less of an
process. issue.

40 41
Thermal considerations Design implications

O ne of the functions of a package is to dissipate the heat generate

by the die inside. Given the prevalence of inexpensive plastic
packaging, which isn’t a great thermal conductor, this duty hasn’t put a
A dvanced packaging challenges the traditional ways chips and their
packages are designed. Those processes historically involved two
separate groups, the chip designers and the packages designers. The
strain on package design. But as more components are added, and as former did the electronic design, while the latter focused more on the
some of them increase in power, wicking heat away becomes critical. mechanical aspects of the housing. Being separate groups, the chip
This is an issue with HBM today, and the challenges facing efforts to plans were largely tossed over to the packaging folks, and in the end,
grow HBM’s capacity include dealing with yet more heat to dissipate. the chip went into the package.

Package design therefore necessarily Whereas heat sinks and spreaders are
includes thermal analysis to identify attached to the package on the side
whether the package will adequately opposite the leads, thermal pipes use
remove heat without leaving any hot connection balls to dissipate heat.
spots. Thermal analysis must now be Although all signals and balls carry
performed for the package as a whole, some heat out of the package along
including the components, to ensure with their electrical functions, thermal
the chip’s ability to remain within its pipes have no electrical function.
target power so that it can perform as Their only role is to form a connection
specified. between hot portions of the package
contents and the PCB.
If the leads, interposers, bridges,
substrates, and molding compound
are insufficient for maintaining proper
temperatures across operating
conditions, then the package may
need to include components whose
function lies only in moving heat
around.

Examples of such components are

heat sinks, heat spreaders, and
thermal pipes. The former are pieces
of metal (or any thermally conductive
material) affixed externally to the top
of the package. The second is similar,
but it’s embedded in the package.
Spreaders smooth out internal hot Fig. 23: Thermal mitigation options.
spots, moving heat from where it’s in Extra inert metal structures may be Fig. 24: A simplified view of the supply chain for advanced packaging. One or more dies
abundance to areas with less heat, necessary to provide adequate heat are designed and fabricated in a foundry. Silicon and glass interposers also typically
helping the package dissipate it. dissipation. Choices include, but require foundries. Organic elements typically come from the packaging houses.
are not limited to, heat sinks, heat Additional components also may be included at assembly. With advanced packaging,
spreaders, and thermal pipes. the lines between foundries and OSATs are blurring.

42 43
Design implications

With advanced packages, such Regardless of the style of interposer Each of the components being housed case, the substrate or interposer will
an arm’s-length collaboration is or bridge, designers must pay — from the highest-performance die have an impact on performance and
insufficient. All stakeholders must attention to: to the lowliest capacitor — will have an power. Simulating performance must
participate early in the planning impact on performance, power, and/ include the effect of that interconnect.
and design optimization process. • Die and passive placement or cost. Optimizing dies, interposers, Passives will impact signal and power
Components that will co-reside in • Routing to bumps bridges, substrates, and packaging integrity. The placement and routing
the package will come from a wide requires the early collaboration of all of signals to these passives will also
• Interposer TSVs (or more generally,
variety of sources. They include chip designers, starting from the planning impact performance.
through-interposer vias, or TIVs)
designers, designers of interposers or stages and continuing on from there.
other substrates, package designers, • Mechanical integrity, including Perhaps most critically, the
and even makers of off-the-shelf thermal, stress, and co-planarity Silicon design teams will create the arrangement of components in the
items such as passives, MEMS, optical, • Reliability — particularly principal chips or chiplets. That package must be able to dissipate
or other electronic chips that are electromigration and IR drops process may result in the partitioning the heat that the components will
included in a given package. (EMIR) of a single die into multiples. Those generate. The operating junction
partitioned dies may lay next to each temperature will impact the allowable
Each of those roles has a specific Package designers must include the other as chiplets communicating performance — such as the maximum
set of tasks to perform. The items following in their design efforts: laterally or they may be stacked, with clock speed — and thus must be
that silicon designers must attend to signals flowing through TSVs. considered during silicon design.
include: • Accurate stack-up definitions
Stacked chips can be simulated A traditional flow could be viewed as
• Physical and electrical constraint-
• Meeting performance targets together in a chip-only environment, serial, with package design following
driven signal routing (die-to-die
• Meeting power targets but chiplets arranged side-by- die design, or as a parallel effort. But
and die-to-substrate)
side must communicate through a in the latter case, the two designs —
• Determining any chiplet • Surface-mount and embedded substrate. That substrate could be chip and package — come together
partitioning and whether the passive placement the package substrate, but it will only at the end. By contrast, the flow
pieces should lay out side-by-side more likely be an interposer. In either for advanced packaging requires
• Power and ground plane
or be stacked
generation and management
• Place-and-route
• Design for assembly
• TSV placement
• Design for manufacturability,
• Bump/microbump/pillar placement including stress
• Power integrity • Design for test
• Signal integrity • Thermal analysis and management
• Reliability • System-level power
• Mechanical integrity, including • Die-to-die signal integrity (for
thermal, stress, and co-planarity interface compliance)
• Extraction of package parasitics
Glass and silicon interposers require
silicon-like design and fabrication, • Reliability
while organic interposers involve Fig. 25: Advanced-packaging design flow. All components must be verified in parallel,
teams similar to those creating PCBs. communicating data between tools so that the entire system can be designed and
optimized together.

44 45
Design implications

not only parallel design efforts, but From Wild West to • Technology files that specify As the number of process variations
constant communication between details such as how layers stack evolve from numerous ones that cater
tools so that the effects of decisions standardization up, the materials used and to specific projects into a few well-
on one team can be communicated their properties and thickness, accepted standard processes, ADKs
to the other teams. Over time, initial Advanced packaging creates an any physical or electrical layout will be critical enablers of further
estimates are replaced by simulated incredible number of options for constraints including line and automation to ensure that the vast
values as the design converges. designers — so many that each space dimensions, special signals number of constraints have been met
project is likely to evolve in ways such as differential pairs, and any and that the design will function as
custom design-rule checks (DRCs) intended.
Two very different scales different from prior projects.
Variables include the number of necessary to validate the design.
dies, if and how they’re divided and • Libraries specifying physical
It would be ideal if system sign-off interconnected, where they’re placed, footprints and models for power
directly involved all the design inputs other components, the interposer and thermal behavior for all
from chips, interposers, and packages. material, interposer vs. bridge vs. a components including chiplets,
But the dimensions involved in silicon combination of both, and materials to passives, interposers, vias, routing
and packages are different by three help with thermal issues just to name between dies, and mechanical
orders of magnitude, with silicon the obvious ones. characteristics.
working in nanometers and packages
working in microns (or larger). Simply Silicon processes are also quite • Assembly rules that respect the
using one tool to verify at both scales complex, and process design kits, constraints that a given set of
would be extremely time-consuming. or PDKs, have long been available pick-and-place tools will require,
as a way of informing electronic- including spacing between devices,
What’s more typical is that the chip- design automation (EDA) tools of distances between devices and
design data will be abstracted and fed the many details associated with other elements or the edge of
to the sign-off engine by the system- a given process. No such standard the package, and the maximum
planning tool. That’s why the package format exists for advanced packaging, allowed stack height.
design block above directly feeds the although work is underway to • Any electrical specifications
sign-off block, whereas the chip design establish assembly design kits with which signals must comply,
block doesn’t. (ADKs). Those will be more complex including libraries of interconnects
than PDKs owing to the number of and I/Os, eye masks, jitter
Meanwhile, the chip design goes considerations they must encompass, tolerance, and insertion or return
through its own independent sign-off including: losses.
process that leads to tape-out. The
• Manufacturing rules laying out
system sign-off tools don’t have the
checks for substrates, solder
resolution necessary to bless the chip-
masks, soldering, and silkscreen
design data.
patterns.

46 47
Test considerations

T esting chips in advanced packaging is fundamentally the same as targeted faults were simple stuck- a much smaller signature, which then
testing a single die in a package, but the logistics are more difficult. at faults. But as integration levels can be scanned out and compared
increased and new fault models were to the expected result. The increased
Test circuitry and standards are all about one thing — making potential
introduced, more efficient ways of uptake of such testing technologies
defects within a circuit controllable and observable. If you can’t control testing became necessary. This was created a need for a universal
certain nodes, then you can’t test them thoroughly. If you can’t observe the era of design-for-test, or DFT, mechanism to set up, configure, and
the results, then even if you did manage to apply a test, you can’t see which involves automatic test-pattern control the test circuits in a manner
the result, so it does no good. Combining multiple dies in a package generation (ATPG) and compression. similar to JTAG. This resulted in a new
makes controllability and observability more difficult. standard, IEEE 1687, informally known
EDA companies developed technology as internal JTAG, or IJTAG.
that, when generating test patterns
For many years, two complementary But given the desire for testing the
at design time, takes a mass of test
test approaches have dominated the internals of a chip after packaging,
input data and compresses it to Standard modifications
semiconductor business. The first companies ran scan chains internal to
is IEEE 1149.1, also known as JTAG the chips, as well. In fact, at the time,
speed up the time necessary to load
it when testing. An on-chip circuit
for special cases
(which stands for Joint Test Action internal test may have been more
decompresses the test inputs, sending
Group — the committee that defined common than external test. Two special cases required revisions
them across a dedicated test network.
the standard originally). The second is to these two standards. JTAG is a
Rather than scanning out individual
so-called design-for-test. Driving scan chains through package static DC test. It therefore cannot
bits, the results are compressed into
pins for internal testing worked in test signals that are AC coupled.
JTAG enables scan test, which is the the early days of testing, when the AC coupling allows high-speed
ability to serially scan data into test signals to be impedance matched,
infrastructure, apply a test, and then but capacitors lie between driver
scan the results out. The registers and line and between line and
into which the data is scanned are receiver. Whereas DC-coupled lines
dedicated to test, and the serial communicate via voltage levels,
sequence of registers is known as AC-coupled lines communicate via
the scan chain. The serial approach is transitions that can pass through the
important because, especially when capacitors. The benefit is the lack of a
the standard emerged, few pins were DC component to the current as well
available for use in testing. As it is, a as the ability to cross voltage domains.
JTAG test access port (or TAP) consists
of only four pins (with the option for a
fifth reset pin).
Fig. 26: A basic JTAG scan chain testing
JTAG originally was intended to test board connections. Registers on the
PC board connections. By loading data left side are loaded with data and then
into each pin on one chip, the result clocked across to the right side where Fig. 27: Internal chip test. Compressed Fig. 28: DC- vs. AC-coupled lines.
could be detected on the connected the data is captured and scanned back test stimulus data is scanned in and Capacitors on AC-coupled lines
chip, verifying the integrity of the out. On the test access port (TAP), only decompressed into the test network. eliminate DC current from the
PCB connection. The same approach one signal is shown for simplicity: the The results of the tests are then connection, but require signal
allows testing chiplets on a substrate data-in signal on the left and the data- compressed into a small signature and transitions in order to pass through
in a package. out signal on the right. scanned out for verification. the capacitors.

48 49
Test considerations

IEEE 1149.6 provides a means of multiplexing analog signals, and The final capability necessary for Figure 30 illustrates an example of a
testing AC-coupled signals. It’s reference values. generating tests for an advanced two-die-plus-HBM combination in a
complementary to 1149.1 and can package is software that can combine single package. The HBM stack can
reside on the same scan chain. Some regular circuits, such as individual chip and other component use memory BIST (MBIST) plus scan
memories, can be outfitted with tests into a single unified scan chain.
The internal test standard, meanwhile, circuits that run tests internally,
works for digital logic, but not for without the need for external test
analog blocks. The standard is in stimulus. Called built-in self-test,
the process of being augmented or BIST, such circuits can simplify
to handle analog circuits. Currently the remaining test circuitry. Such
called IEEE P1687.2 (The P indicates a BIST circuits can still be controlled
work in progress), it will complement by JTAG externally, and that’s how
IEEE 1687. It allows the digitizing of manufacturing test proceeds. But they
the result of key parameters when are particularly useful for systems
compared to reference values. Each requiring occasional in-field tests,
analog sub-block (essentially, some such as in vehicles, where they’re run
analog function) can have its own by an internal JTAG controller rather
associated test block, or one test than external JTAG pins.
block can handle multiple sub-blocks,

Fig. 29: An example set of analog tests. The test blocks fit onto the scan chain, but Fig. 30: An example package with two dies and an HBM stack. One die has two digital
they consist of comparisons of signal values to references. The specific tests are highly blocks and one analog one. The digital block is shown as tested via IEEE 1687; the
dependent on the analog function being performed. A test block can multiplex tests for analog block is tested via a future IEEE 1687.2. The HBM stack can have its logic tested
multiple functions or each function can have its own test block. via JTAG, with MBIST testing the memory cells.

50 51
 Reliability
Test considerations

A
testing. The other dies can use IEEE dvanced packages share the same basic reliability concerns as
1687 (or 1687.2) to test their internals. standard packages, but they’re amplified by the new materials
In theory, this entire sub-system
and number of components being co-packaged. The largest concerns
can be tested through a single TAP, deal with three aspects — co-planarity, electromigration, and
although additional TAPs are possible thermomechanical effects.
for parallel testing. For the latter
case, another standard, IEEE 1838, Co-planarity is always important for any die that has many connections, as is typical
specifies how the multiple controllers for a BGA package, for example. If not co-planar with the substrate or interposer it’s
are configured and interconnected, being mounted on, then some of the balls may not make contact. Such a situation
identifying a primary TAP (PTAP) and would be a test failure and the unit wouldn’t be shipped to customers. But if the
secondary TAPs (STAPs). IEEE 1838 co-planarity weren’t that far off, then solder balls might make poor connections on
specifically targets stacked dies, each some pads — connections that could come loose after mechanical shocks or too
of which has its own controller, but many thermal cycles.
which are accessible only through
the bottom die, with TSVs (typically) Warping is a concern particularly for a very fine metal lines as compared with
providing access to the upper dies. component with built-up layers, such PCBs, they tend to have higher current
as a substrate or an interposer. The density and therefore are more
A number of other test-related different layers of materials can create subject to migration.
standards have been inactivated internal stresses that cause bowing,
because IEEE 1149.1 has been broadly so materials for these applications Electromigration can happen
taken up and handles the situations are carefully chosen for dimensional anywhere that current density is too
the other standards covered. These stability. high, however, not just on a die. The
include 1149.4 for mixed signals, IEEE whole point of using interposers and
1532 for in-system programming of Electromigration has long been a reducing the sizes of bumps is to allow
programmable chips, and IEEE 1581, concern, especially on silicon. It’s a higher interconnect density than is
which targeted memory chips that function of current density, with high possible on a PCB. Those finer lines
lacked TAPs. currents literally pushing metal atoms mean that electromigration will be
around. Because silicon chips have more of an issue than it would be for

Fig. 31: Co-planarity issues caused when one surface is warped more than the one to
which it’s bonded. If too far off, connections will fail outright and should be caught at
test. But if a poor solder joint forms instead, it may not fail until in the field.

52 53
 Security
Reliability

N
a standard PCB. Analysis tools are Although the assembly flows in o discussion of electronic systems of any kind can be complete
important for identifying traces with commercial production today have without considering security. In the semiconductor realm, that has
high current density so they can be addressed these issues to the extent
primarily dealt with monolithic chips — especially systems-on-a-chip
fixed prior to production. possible, it’s still early days for this
type of assembly. So designers can’t (SoCs), because so much valuable activity takes place on a single piece
Thermal considerations include two assume that all materials will be of silicon. Much effort has gone into protecting chips and the traffic
important aspects. The first is simply perfectly flat, that in-package metal between chips on boards. Their security involves not just protecting
the ability to remove the heat being lines can handle the current, and against hackers, but also against supply-chain threats that could
generated inside the chips. With that the overall assembly will survive enhance vulnerability to hacking or simply act as an economic leak as
multiple components, higher heat is a lifetime of temperature cycles. Die
possible than if those components
system builders buy fake components, perhaps unwittingly.
and package analyses are important
were packaged separately. If that heat prior to taping out or committing to
can’t escape sufficiently, then junction a packaging configuration to avoid Advanced packages contain such targeted strike. To this hacker, the
temperatures will rise too high and possible future rework. chips plus other components — chip is a white box.
chips will cease operating properly. silicon or otherwise. The chips may
be protected, but without extra Given the number of components in
Of longer-term concern are the effects thought, there is no unifying security an advanced package, it’s possible that
of repeated heating and cooling cycles that protects the entire package a hacker may have more information
on the assembly. As the unit heats contents. Die protections already are about some components than others,
up, different elements will expand at well documented, but the additional giving a mixed black-box/white-
different rates according to their CTEs. considerations for advanced packages box situation. But the package also
For example, if not managed properly, are not. contains more than simply the chips.
the balls attached to a die may expand The substrate, interposers, bridges,
a different amount than the substrate One of the important concepts for and passives all must be considered in
and pad it’s connected to, potentially assessing vulnerability has to do with addition to any active elements.
breaking the connection — especially how much an attacker knows about
the technology they’re probing. A
after many cycles.
random hacker who has access only Advanced-package
The risk of such issues depends to the physical package will have no vulnerabilities
entirely on the materials used. If a idea what’s inside and so must play
silicon die is mounted onto a silicon guessing games to break in. Such a
Advanced packages suffer the same
interposer, the risk is lower because hacking target acts as a black box.
vulnerabilities that SoCs do, but the
both elements are silicon. But that specific points of vulnerability and
same die bonded onto an organic At the other end of the spectrum
would be an attacker who is part their impact differ. Two important
interposer may fare differently. considerations help characterize the
Materials and physical arrangements of the supply chain, and hence has
access to design information, be it RTL nature of a specific type of attack.
are chosen to minimize the effects of First, is it destructive or can (or must)
CTE mismatches such as these, and (the hardware design specification)
it occur while the system is running?
some compliant materials are used or GDSII (the physical mask data).
Although it requires extensive work And second, does the attack occur
to help dissipate the stresses such during some stage of manufacturing
mismatch causes. and sophisticated tools, much can be
and distribution, or does it occur in
learned from this information, making
the field after deployment?
hacking not so much a guess as a

54 55
Security

Considerations for 2.5D and 3D latter situation is less likely and more probably also be protected since the reveal how the package components
configurations are different. In easily addressed by controlling the additional components are likely to be are interconnected.
general, multi-die stacks will be assembly and test flow to eliminate passive.
harder to probe and reverse engineer such opportunities. Attacks are Trojan horses (N, S)
— especially in cases such as HBM, obviously easier if the system is a Side-channel attacks (N, F, B)
where the stack consists of chiplets all white box.
Supply-chain attacks include the
of the same size. As 3D connections
The two most typical types of side- possible insertion of Trojan horses at
evolve to hybrid bonds, which literally Control usurpation (N, F, W) channel attack involve analysis either any of various design stages. A given
result in the knitting together of both
of power noise or electromagnetic die could have such circuitry either
the oxide and the copper on both
The prior attack merely releases emissions (EMI, where the I stands surreptitiously designed into the die
chiplets, reverse engineering will
information. This one allows an for interference). Both can be used to by an attacker on the design team or
become even more difficult due both
attacker to take control by accessing extract information (and so are a form it could inherit such a weakness in IP
to the greater difficulty in prying the
internal resources, such as registers of information leak), with the most purchased for use in the die. Package-
chiplets apart and to the finer pitch
and memory, and contaminating common target being encryption keys level interconnect infrastructure,
and smaller pads that such technology
them to repurpose the system. This during encryption and decryption. If especially if built out of silicon,
allows. 2.5D arrangements expose
is most likely a white-box attack, such keys are unique to each device could theoretically house active
more signals, and so most of the
although necessary information such (as they should be), then analysis components, but a typical fabrication
issues below deal with 2.5D.
as processor architectures can be must be non-destructive since the process wouldn’t include the kinds of
found in trade publications, meaning keys will work only on that one unit. lithography and depositions required.
The following are the different
that it doesn’t necessarily have to be These attacks require a huge number More likely would be adding signals
categories of threat and how they
an insider performing the attack. It of individual assaults in order to to the outside world that ought to
apply to advanced packages. Attack
requires both access to signals and amass the amount of data necessary remain inside, or re-routing the
characteristics are denoted as D
knowledge of how to apply them, to statistically deduce key values, likely signals between components.
(destructive), N (non-destructive), S
although some amount of guessing is with the aid of AI.
(supply chain), F (field), W (white box)
or B (black box).
likely to determine finer details that Counterfeiting (N, S)
haven’t been published. Reverse engineering (D, F, W/B)
Information leaks (N, F, W/B) There are different opportunities in
Fault injection (N, F, B) Although some amount of reverse the supply chain for counterfeiting.
engineering can be done non- In one case, legitimate units may be
Although individual chips may be
This sort of attack typically works by destructively, a thorough analysis will diverted through techniques such
robustly protected, they communicate
glitching the power in an attempt to require careful deconstruction of the as overbuilding. Those devices will
with each other and the outside
put one or more chips into an illegal package and its components. Aside operate correctly. The impact is
world through interposers, bridges,
state that might release information from the chips, the interconnect is economic, with revenues going to the
redistribution layers, and the
or allow a control change. The latter the most likely target. That means counterfeiter. In other cases, failed or
substrate. Anyone who can open the
works only if, after the change, the interposers, bridges, and the marginal units might be diverted and
package delicately enough to not
system can be returned to a legal substrate. The more advanced the sold, in which case the purchaser may
damage it can probe the inter-die
state without power cycling (which technology being targeted, the more get bad material. Finally, attempts
connections to get information. An
might undo the control change). If expensive the equipment necessary to build counterfeit units based on
attacker in the supply chain might
the active chips in the package are both to deconstruct the package reverse engineering could turn out
be able to do so prior to package
well protected against fault-injection and to analyze what it reveals. units that work properly, with only
encapsulation if there’s a stage where
attacks, then the package will Delaminating built-up structures can an economic impact, or they may
the product can be powered up. The

56 57
Security

be unreliable if manufacturing and critical signals on inner layers may be that lay atop one of two physical Given complete chiplet designs, it’s
testing are sloppy or if the reverse the best defense against probing. arrangements, UCIe and Bunch impractical to go back and tell the
engineering effort was only partially of Wires (BoW). The very use of a chiplet designers to add active EMI
successful. Silicon bridges should be harder to protocol adds latency to signals obfuscation. That means that signals
probe. The bridges expose pads on crossing between chiplets. Adding outside the chiplets but inside the
both sides that chips attach to. Those encryption to that would further package may still radiate. Encryption
Attack mitigations pads are under the chips, with the burden performance, potentially would make such radiation far
signals within the bridge being buried dramatically. less meaningful, but it’s unclear if
The three main aspects to protecting in the unit. Reverse engineering is encryption will become an accepted
the packaged components beyond possible by removing the chiplets and Although no standard specifies mitigation.
mitigations already in place for figuring out which signals the bridge encryption for inter-chiplet
the chiplets are the interposer, connects. That may be an issue for communication, both UCIe and BoW Adding obfuscation in the package
traffic in general, and side-channel a chiplet assembly of the type that’s are looking into security. Neither has would entail adding a component with
vulnerability. typical now, where a single company established a standardized approach the sole purpose of emitting confusing
creates all of the chiplets. But in a yet. Although added security always EMI signals, contributing to noise and
The interposer is vulnerable to future open chiplet market, those means some loss of performance, the consuming energy. It may work for
probing and reverse engineering. interfaces would be public, anyway. cost for chiplets would be particularly some applications, but is unlikely to
Probing non-destructively is possible So bridges would appear to resist significant. This is an area in active be appealing across the board.
only if the accessible layer on top probing and, to a lesser degree, development, and changes in this
exposes critical signals. If critical reverse engineering more effectively space are likely over the next couple If sensitive signals are radiating,
signals are buried on inner layers, than interposers. years. further shielding at the package level
probing becomes more difficult. may be necessary. That could mean
Turning probing into a successful Side-channel attacks, meanwhile, are an additional metal layer above the
attack also requires that the attacker Encrypting intra- most effectively protected at the die components and embedded within
know which signals are which. Reverse
engineering may be necessary to
package traffic level, especially for power analysis. If
every die has side-channel protections
the substrate.

make that determination unless the and the only components outside As with any discussion of security,
attacker can identify signals based on If probing can’t be avoided, the best the chiplets are passive, then power likely attack surfaces and mitigations
signaling patterns. defense is the same one used for any analysis should be difficult. must be considered early in the design
network connection — encrypt the phase. After-the-fact stop-gap efforts
Complete reverse engineering traffic. Although that’s standard for If chiplets are protected against EMI are likely to be less effective — or
requires delaminating the interposer some communication protocols, it radiation, then the package itself will even ineffective. Part of that calculus
layer-by-layer to trace out where the may meet with resistance from chiplet have a smaller, but non-zero, EMI deals with the value of a given chip
metal leads run. It may be possible designers. The idea of breaking a signature. If active countermeasures or chiplet in a system, but one can’t
to obfuscate the layout by including monolithic chip apart into different are used on all the chiplets, then lose sight of the fact that attacks on
false routing, but ultimately, if an chiplets works best if chiplet-to-chiplet the package EMI signature would be one component may not occur for
attacker can stack all the decoded connections cause as little speed loss meaningless since it would consist of the sake of probing that component.
layers graphically, they should be as possible. The fastest connection, as combined obfuscated signals from all It may just be a way to get onto the
able to determine the intended long as the topology permits, would chiplets. But if the chiplets rely only network, and then get to some other
routing from the pads connecting the simply be wires on the interposer. on shielding for protection, then the component. So designers must look
chiplets. So obfuscation is likely to be interposer and other connections may more broadly at the impact of security
only minimally helpful. Thus, keeping But in the interests of standardization, still radiate the signals. (or its lack) in the systems for which
connections typically use protocols the chips are designed.

58 59
A fast-moving technology Recent developments

A Heterogeneous integration
dvanced packaging remains an incredibly dynamic area. Although Experts at the Table: Heterogeneous
employed primarily on high-value chips for now, its use is growing Integration
at a rapid rate. This report presents a number of processes and October 19, 2023 (Part 1)
Challenges Of Heterogeneous
November 15, 2023 (Part 2)
options, some of them branded. Those should not be considered Integration
November 29, 2023 (Part 3)
processes that are standardized across the industry. New ideas and July 13, 2023
techniques are the rule, not the exception, during this formative phase Experts at the Table: Semiconductor
Heterogeneous integration opens the
of the technology. door to an almost unlimited number
Engineering sat down to discuss
problems and potential solutions
of features in a single package, but
The high-level impact continues an integration trend started long ago. We’ve moved in heterogeneous integration with
it also adds system-level challenges
from systems on boards to systems on a chip, and although systems in a package Dick Otte, president and CEO of
into a small space filled with a whole
aren’t entirely new, they’re now being embraced into the mainstream. Advanced Promex Industries; Mike Kelly,
spectrum of possible interactions.
packages are making that possible, shrinking systems and allowing more to be vice president of chiplets/FCBGA
Mike Kelly, vice president of chiplets/
done in smaller spaces. integration at Amkor Technology;
FCBGA integration at Amkor
Shekhar Kapoor, senior director of
Technology, talks about a variety of
Semiconductor Engineering expects that new approaches will make appearances product management at Synopsys;
issues ranging from uneven aging,
every year. Some will stay, others will fade as better ideas succeed them. Future John Park, product management
warpage, and different mechanical
updates to this eBook will look to sorting the lasting developments from the fleeting group director in Cadence‘s Custom IC
stresses, as well as some possible
ones. The one guarantee is that from year to year, leading-edge packaging will look & PCB Group; and Tony Mastroianni,
benefits.
different. advanced packaging solutions director
at Siemens Digital Industries Software.
Smarter Systems Through What follows are excerpts of that
Heterogeneous Integration: conversation. (Part 1)
Highlights From 3D & Systems
Summit Many More Hurdles In
SEMI Heterogeneous Integration
July 25, 2023 January 18, 2024

It has taken decades of research and Advanced packaging options

development and strong commitment continue to stack up in the pursuit
to various industry programs, but of “More than Moore” and higher
the stars are finally aligning for 3D levels of integration. It has become
semiconductor systems. No one could a place where many high-density
have left the 3D & Systems Summit interconnects converge, and where
2023 – held in late June in Dresden – many new and familiar problems need
with any doubt that heterogeneous to be addressed.
integration, enabled by increasingly
mature 3D packaging technologies,
is becoming a key driver of the
semiconductor industry’s success.

60 61
Recent developments

Integration Hurdles For Analog And Leadframes artificial intelligence (AI), data cloud LAB Flip Chip Reflow Process
RF In Next-Gen Packages and more that are expecting and Robustness Prediction By Thermal
March 23, 2024 experiencing rapid growth. As Simulation
High Performance, Multi-Chip most of these applications require Amkor
A rapid increase in wireless Leadframe Package With Internal high performance, single-die Flip
November 16, 2023
connectivity and more sensors, Connections Chip packages may no longer be
coupled with a shift away Amkor appropriate and multi-dies in a chiplet Nowadays, there are many
from monolithic SoCs toward December 19, 2023 module packages could be the new interconnects in IC chips. One of
heterogeneous integration, is driving solution. From the viewpoint of the the packaging goals is to connect
up the amount of analog/RF content For high performance applications, bump interconnection methodology, an IC to the next level of subsystem
in systems and changing the dynamics demand for highly integrated mass reflow (MR), thermocompression circuitry (package substrates/print
within a package. packages has increased. This is due bond (TCB) and laser assisted bonding circuit boards). Mass reflow (MR)
to the highly integrated package’s (LAB) are widely used in the industry. of solder joints is a widely adapted
Powering The Automotive electrical performance advantages and stable process in the industry.
Revolution: Advanced Packaging For of reduction of interchip distance Wirebonding Is Here To Stay The applications of MR include flip
Next-Generation Vehicle Computing (delay), high density I/O counts for chip, ball mounting, surface mount
October 19, 2023
multi-function and small form factor. technology (SMT), and even reliability
Amkor
With the increasing importance of Few technologies in semiconductor tests. SMT reflow ovens contain 8 to
April 18, 2024 highly integrated packages, the need manufacturing have stood the test of 20 heating zones and can be used
Automotive processors are rapidly for improved thermal management time as steadfastly as wirebonding. for inline production. However, not
adopting advanced process nodes. is also increasing. When the high- This process, which involves only the silicon solder joints but the
NXP announced the development of density I/O signals operate for the electrically connecting semiconductor entire packages inside reflow ovens
5-nm automotive processors in 2020, highest performance, heat generation devices to their packages, has been are heating up during the MR process.
Mobileye announced EyeQ Ultra using increases on the die. The high heat a cornerstone of the electronics This thermal budget will increase
5-nm technology during CES 2022, generation without effective heat industry since the beginning of the package warpage and affect solder
and TSMC announced its “Auto Early” dissipation has adverse effects on electronics industry. joint quality in fine pitch (i.e., less
3-nm processes in 2023. In the past, reliability and electrical performance than 60 µm) conditions. Thermal
the automotive industry was slow of electronic products. Gearing Up For Hybrid Bonding compression with non-conductive
to adopt the latest semiconductor October 23, 2023 paste (TCNCP) and laser assisted
technologies due to reliability Bonding Hybrid bonding is becoming the
bonding (LAB) were introduced
to address fine pitch devices with
concerns and lack of a compelling
need. Not anymore. preferred approach to making localized heating to reduce package
Reverse Laser Assisted Bonding heterogeneous integration work, as warpage.
(R-LAB) Technology For Chiplet the semiconductor industry shifts its
focus from 2D scaling to 3D scaling.
Module Bonding On Substrate
Amkor
September 21, 2023

In the recent semiconductor

market, there are many applications
including smartphone, tablets,
central processing units (CPUs),

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Recent developments

Interposers and bridges been introduced for more advanced optimization study has revealed complete connectivity verification,
applications. This technology would that the application of the two-step DRC, and assembly validation. Another
also benefit from PL processing for pressure-profile and the medium primary reason is the ongoing focus
Building Better Bridges In Advanced cost reduction. Due to the large reflow temperature profile within on reducing the design cycle time. This
Packaging package dimensions, applications the vacuum reflow process has is possible by beginning with clear and
September 21, 2023 such as an application processor (AP) successfully eliminated the die-pop proven manufacturing and assembly
or multichip module (MCM) will have occurrence when packaging ultrathin checks that can be implemented
The increasing challenges and rising
greater benefits than the smaller dies. Together with the appropriate during the initial layout phase,
cost of logic scaling, along with
power management integrated circuit selection of the solder paste volume thereby reducing the need for rework
demands for an increasing number of
(PMIC), transceiver or audio codec and the bond line thickness (BLT) of of the design layout during post-
features, are pushing more companies
applications typical of chip-first FO solder layer, majority of the samples process checking. In a blog discussing
into advanced packaging. And while
packaging. attained the solder void size over die Package Assembly Kits, Paul McLellan
that opens up a slew of new options, it
size of below 2% with zero die pop mentions, “New challenges face both
also is causing widespread confusion
detected, without compromising the IC designers and package designers
over what works best for different Assembly manufacturing productivity. and new approaches are required.”
processes and technologies.
Finally, and possibly one of the most
Elimination Of Die-Pop Defect By Fan-Out Panel-Level Packaging impactful reasons, is the need to
The Race To Glass Substrates maintain design integrity amid the
Vacuum Reflow For Ultrathin Die Hurdles
May 29, 2024 growing demands and complexity
With Warpage In Semiconductor January 24, 2024
of the high-density fan-out (HDFO)
The chip industry is racing to develop Packaging Assembly package design environment.
glass for advanced packaging, setting Fan-out panel-level packaging (FOPLP)
Siang Miang Yeo et al, Amkor, Universiti
the stage for one of the biggest shifts promises to significantly lower
Tunku Abdul Rahman, Kajang, Malaysia
in chip materials in decades — and assembly costs over fan-out wafer- Controlling Warpage In Advanced
January 18, 2024
one that will introduce a broad new level packaging, providing the relevant Packages
set of challenges that will take years to Semiconductor die thickness is getting processes for die placement, molding June 24, 2024
fully resolve. thinner over time due to improvement and redistribution layers (RDLs)
of power efficiency in advance power formation can be scaled up with Warpage is becoming a serious
electronic packages. Ultrathin die equivalent yield. concern in advanced packaging, where
Panels with convex warpage can easily a heterogeneous mix of materials can
deteriorate the solder void removal Package Assembly Design Kits: The cause uneven stress points during
A Hybrid PLP Technology Based On process during solder reflow, leading Future Of Advanced Package Design assembly and packaging, and under
to various packaging reliability issues. real workloads in the field.
A 650mm x 650mm Platform Amkor
In particular, a new type of packaging May 23, 2024
Amkor
July 25, 2023
defect phenomenon—die-pop—is
observed. Vacuum reflow process has Why should there be an interest in
Thermal
A panel-level (PL) approach to fan-out been able to reduce the solder void Package Assembly Design Kits (PADK)
(FO) packaging has been discussed size to minimum value consistently today? For the most part, it is due to Navigating Heat In Advanced
for several years to reduce the cost but there is an observable number the advancement in the accumulation Packaging
of chip-first FO packaging based on of die-pop occurrence during the of files forming the PADK now offering January 18, 2024
redistribution layer (RDL) technology. single-step pressure-profile reflow a customized heterogeneous design
process for ultrathin dies that come experience that optimizes the device’s The integration of multiple
More recently, multilayer high-
with convex warpage. Nevertheless, intended package performance with heterogeneous dies in a package is
density chip-last packages have

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Recent developments

pivotal for extending Moore’s Law Reliability it’s becoming more difficult to contain
and enhancing performance, power in leading-edge designs.
efficiency, and functionality, but it also
is raising significant issues over how to
Electromigration Performance Of
manage the thermal load. Fine-Line Cu Redistribution Layer Other
(RDL) For HDFO Packaging
Package Integrated Vapor Chamber Amkor Big Shifts In Power Electronics
Heat Spreaders January 18, 2024 Packaging
Amkor November 16, 2023
The downsizing trend of devices
March 21, 2024 gives rise to continuous demands The power semiconductor market
With continuous increases in of increasing input/output (I/O) and is poised for remarkable growth in
computational demand in nearly all circuit density, and these needs the next several years, fueled by
electronics market segments, even encourage the development of a High- the adoption of electric vehicles and
historically lower power packaging Density Fan-Out (HDFO) package with renewable energy, but it also driving
is being driven into challenging fine copper (Cu) redistribution layer big changes in the packaging needed
thermal management situations. (RDL). For mobile and networking to protect and connect these devices.
Node shrink alone is reaching a application with high performance,
limit in maintaining track with HDFO is an emerging solution
Moore’s law. The economics and because aggressive design rules can
yield challenges of large monolithic be applied to HDFO compared to the
system on chip (SoC) designs are other package types such as Wafer
driving the development of silicon Level Fan-Out (WLFO). HDFO allows
disaggregation or chiplet adoption. assembly of more than one chip in
Trends in total power dissipation are one package and mostly fine Cu RDL
driving the development of extremely is used to interconnect the chips.
low thermal resistance cooling In addition, HDFO can be made in
systems. High-performance systems wafer and substrate level depending
may implement a combination of on the application, which has better
heat pipes, vapor chambers, or liquid scalability in terms of package size.
cooling, driving sink-to-ambient
thermal resistance less than 0.5°C/W Electromigration Concerns Grow In
[1]. These low resistance cooling Advanced Packages
solutions translate to the package now April 18, 2024
comprising a much larger percentage
of the total junction-to-ambient The incessant demand for more
thermal resistance. As a result, these speed in chips requires forcing more
trends in power density and extremely energy through ever-smaller devices,
low resistance cooling solutions increasing current density and
are forcing the need for thermal threatening long-term chip reliability.
enhancement closer to the silicon While this problem is well understood,
than ever before.

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Standards

Standards
Standard Coverage
body

IEEE 1149.1 JTAG

Mixed signals; now inactive since 1149.1 can

IEEE 1149.4
handle

IEEE 1149.6 AC coupling

IEEE 1149.7 Enhanced JTAG

In-system programming; now inactive since 1149.1

IEEE 1532
can handle
Testing for memory ICs that lacked a JTAG TAP;
IEEE 1581
now inactive due to prevalence of TAPs

IEEE 1687 Internal JTAG, or IJTAG

IEEE 1838 Multiple TAP controllers for stacked dies

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