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VLSI Lab Experiment 7-1

The document outlines an experiment to model a bidirectional buffer using VIVADO software. It includes the theory behind bidirectional buffers, the procedure for creating a project, synthesizing, implementing, and generating a bitstream, along with VHDL code for both the buffer and its testbench. Observations and expected outcomes from the experiment are also mentioned, emphasizing the functionality of the buffer in storing and transmitting data.

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Dhruv Ramchandani
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© © All Rights Reserved
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4 views

VLSI Lab Experiment 7-1

The document outlines an experiment to model a bidirectional buffer using VIVADO software. It includes the theory behind bidirectional buffers, the procedure for creating a project, synthesizing, implementing, and generating a bitstream, along with VHDL code for both the buffer and its testbench. Observations and expected outcomes from the experiment are also mentioned, emphasizing the functionality of the buffer in storing and transmitting data.

Uploaded by

Dhruv Ramchandani
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Bharati Vidyapeeth (Deemed to be University)

College of Engineering, Pune


Department of Electronics & Communication
Engineering

SUBJECT: VLSI DESIGN TECHNOLOGY SEM: VI

Experiment No: 07

AIM: To model bidirectional buffer

APPARATUS: VIVADO (XILINX) Software Tool

THEORY:

A bidirectional buffer includes first and second unidirectional buffer connected for retransmitting
signals and in opposite directions between first and second.
In bidirectional buffer, data can be transferred from both sides, chip enable is provided to enable
or disable chip. If CE=0, then the buffer is in high impedance state.

OPERATION: The word to be stored is 1010.


 These bits are connected to the D input of the four D flip flops.
 The clock pulse is applied.
 Corresponding to the first negative edge of the clock pulse, the output of all the D flip
flops will be, Q3Q2Q1Q0=B3B2B1B0=1010
 Even if the input is now changed, the output remains latched to 1010 till the next negative
edge of the clock.
 Thus, the buffer is capable of storing digital data.

PROCEDURE:

1. Create a Vivado Project


1. Vivado Projects
2. Start Vivado
3. Open Create Project Dialog
4. Set Project Name and Location
5. Select Project Type
6. Add Existing Sources
7. Add Constraints
8. Select Parts
9. Check Project Configuration Summary
10. Vivado Project Window

2. Edit The Project - Create source files


1. Add or create design source
2. Design Sources
3. Design Constraints

3. Synthesize, Implement, and Generate Bitstream


1. Synthesis
2. Implementation
3. Generate Bitstream

4. Download Bitstream

1. Open Hardware Manager


2. Connecting Your Board via USB
3. Connecting your Board to Vivado
4. Verify that Your Board is Identified
5. Download Bitstream

OBSERVATIONS:

1. Check the complete program


2. RTL Schematic of program
3. Add the stimuli
4. Verify the waveform
5. Verification in hardware
VHDL CODE FOR BIDERCTIONAL BUFFER

SIMULATION CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BidirectionalBuffer is
Port (
data_in : in std_logic_vector(3 downto 0); -- Input data lines
data_out : inout std_logic_vector(3 downto 0); -- Bidirectional data lines
clk : in std_logic; -- Clock signal
CE : in std_logic -- Chip Enable (Active HIGH)
);
end BidirectionalBuffer;

architecture Behavioral of BidirectionalBuffer is


signal buffer_reg : std_logic_vector(3 downto 0) := "0000"; -- Internal register
begin
process (clk)
begin
if rising_edge(clk) then
if CE = '1' then
buffer_reg <= data_in; -- Store data on clock edge if CE is enabled
end if;
end if;
end process;

-- Drive data_out only if CE is enabled, else high-impedance


data_out <= buffer_reg when CE = '1' else (others => 'Z');
end Behavioral;

TESTBENCH CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BidirectionalBuffer_tb is
end BidirectionalBuffer_tb;

architecture testbench of BidirectionalBuffer_tb is


-- Component declaration
component BidirectionalBuffer
Port (
data_in : in std_logic_vector(3 downto 0);
data_out : inout std_logic_vector(3 downto 0);
clk : in std_logic;
CE : in std_logic
);
end component;

-- Signals for testing


signal data_in_tb : std_logic_vector(3 downto 0) := "0000";
signal data_out_tb : std_logic_vector(3 downto 0) := "ZZZZ"; -- Initialized to high impedance
signal clk_tb : std_logic := '0';
signal CE_tb : std_logic := '0';

begin
-- Instantiate the Bidirectional Buffer
uut: BidirectionalBuffer
port map (
data_in => data_in_tb,
data_out => data_out_tb,
clk => clk_tb,
CE => CE_tb
);

-- Clock process
clk_process: process
begin
while now < 100 ns loop
clk_tb <= '0';
wait for 5 ns;
clk_tb <= '1';
wait for 5 ns;
end loop;
wait;
end process;

-- Stimulus Process
stim_proc: process
begin
-- Initial state: CE=0, data_out should be high impedance (Z)
CE_tb <= '0';
wait for 10 ns;

-- Store 1010 in buffer (CE=1)


data_in_tb <= "1010";
CE_tb <= '1';
wait for 10 ns;

-- Change input, but output should remain 1010 (latched)


data_in_tb <= "1100";
wait for 10 ns;

-- Disable buffer (high impedance output)


CE_tb <= '0';
wait for 10 ns;

-- Re-enable buffer and load new value


CE_tb <= '1';
data_in_tb <= "0110";
wait for 10 ns;

-- End simulation
wait;
end process;
end testbench;

RTL DIAGRAM:

WAVEFORM:

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