M

PIC16C717/770/771
Data Sheet
18/20-Pin, 8-Bit CMOS Microcontrollers
with 10/12-bit A/D

 2002 Microchip Technology Inc. DS41120B

Note the following details of the code protection feature on PICmicro® MCUs.

• The PICmicro family meets the specifications contained in the Microchip Data Sheet.
• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.

Information contained in this publication regarding device Trademarks

applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab,
ensure that your application meets with your specifications. KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
No representation or warranty is given and no liability is PRO MATE, SEEVAL and The Embedded Control Solutions
assumed by Microchip Technology Incorporated with respect Company are registered trademarks of Microchip Technology
to the accuracy or use of such information, or infringement of Incorporated in the U.S.A. and other countries.
patents or other intellectual property rights arising from such
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
use or otherwise. Use of Microchip’s products as critical com-
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
ponents in life support systems is not authorized except with
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
express written approval by Microchip. No licenses are con-
MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select
veyed, implicitly or otherwise, under any intellectual property
Mode and Total Endurance are trademarks of Microchip
rights.
Technology Incorporated in the U.S.A.

Serialized Quick Term Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

© 2002, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.

DS41120B - page ii  2002 Microchip Technology Inc.

M PIC16C717/770/771
18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D
Microcontroller Core Features: Pin Diagram
• High-performance RISC CPU 20-Pin PDIP, SOIC, SSOP
• Only 35 single word instructions to learn
RA0/AN0 1 20 RB3/CCP1/P1A
• All single cycle instructions except for program
RA1/AN1/LVDIN 2 19 RB2/SCK/SCL
branches which are two cycle 18
RA4/T0CKI 3 RA7/OSC1/CLKIN

PIC16C770/771
• Operating speed: DC - 20 MHz clock input RA5/MCLR/VPP 4 17 RA6/OSC2/CLKOUT
DC - 200 ns instruction cycle VSS 16 VDD
5
Memory AVSS 6 15 AVDD
A/D A/D
Device Program Data Pins Resolution Channels RA2/AN2/VREF-/VRL 7 14 RB7/T1OSI/P1D
x14 x8 RA3/AN3/VREF+/VRH 8 13 RB6/T1OSO/T1CKI/P1C
RB0/AN4/INT 9 12 RB5/SDO/P1B
PIC16C717 2K 256 18, 20 10 bits 6
RB1/AN5/SS 10 11 RB4/SDI/SDA
PIC16C770 2K 256 20 12 bits 6
PIC16C771 4K 256 20 12 bits 6
Peripheral Features:
• Interrupt capability (up to 10 internal/external
interrupt sources) • Timer0: 8-bit timer/counter with 8-bit prescaler
• Eight level deep hardware stack • Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
• Direct, indirect and relative addressing modes
crystal/clock
• Power-on Reset (POR)
• Timer2: 8-bit timer/counter with 8-bit period
• Power-up Timer (PWRT) and register, prescaler and postscaler
Oscillator Start-up Timer (OST)
• Enhanced Capture, Compare, PWM (ECCP)
• Watchdog Timer (WDT) with its own on-chip RC module
oscillator for reliable operation - Capture is 16-bit, max. resolution is 12.5 ns
• Selectable oscillator options: - Compare is 16-bit, max. resolution is 200 ns
- INTRC - Internal RC, dual speed (4 MHz and - PWM max. resolution is 10-bit
37 kHz nominal) dynamically switchable for - Enhanced PWM:
power savings - Single, Half-Bridge and Full-Bridge Output
- ER - External resistor, dual speed (user modes
selectable frequency and 37 kHz nominal) - Digitally programmable deadband delay
dynamically switchable for power savings • Analog-to-Digital converter:
- EC - External clock - PIC16C770/771 12-bit resolution
- HS - High speed crystal/resonator - PIC16C717 10-bit resolution
- XT - Crystal/resonator
• On-chip absolute bandgap voltage reference
- LP - Low power crystal
generator
• Low power, high speed CMOS EPROM
• Programmable Brown-out Reset (PBOR)
technology
circuitry
• In-Circuit Serial Programming™ (ICSP™)
• Programmable Low-Voltage Detection (PLVD)
• Wide operating voltage range: 2.5V to 5.5V circuitry
• 15 I/O pins with individual control for: • Master Synchronous Serial Port (MSSP) with two
- Direction (15 pins) modes of operation:
- Digital/Analog input (6 pins) - 3-wire SPI™ (supports all 4 SPI modes)
- PORTB interrupt on change (8 pins) - I2C™ compatible including Master mode
- PORTB weak pull-up (8 pins) support
- High voltage open drain (1 pin)
• Program Memory Read (PMR) capability for look-
• Commercial and Industrial temperature ranges up table, character string storage and checksum
• Low power consumption: calculation purposes
- < 2 mA @ 4V, 4 MHz
- 11 µA typical @ 2.5V, 37 kHz
- < 1 µA typical standby current

 2002 Microchip Technology Inc. DS41120B-page 1

PIC16C717/770/771
Pin Diagrams

18-Pin PDIP, SOIC 20-Pin SSOP

18 RA0/AN0 1 20 RB3/CCP1/P1A
RA0/AN0 1 RB3/CCP1/P1A
RA1/AN1/LVDIN 2 19 RB2/SCK/SCL
RA1/AN1/LVDIN 2 17 RB2/SCK/SCL
16 RA4/T0CKI 3 18 RA7/OSC1/CLKIN
RA4/T0CKI 3 RA7/OSC1/CLKIN

PIC16C717
RA5/MCLR/VPP

PIC16C717
RA5/MCLR/VPP 4 15 RA6/OSC2/CLKOUT 4 17 RA6/OSC2/CLKOUT
VSS(1) 5 16 VDD(2)
VSS 5 14 VDD
VSS(1) 6 15 VDD(2)
RA2/AN2/VREF-/VRL 6 13 RB7/T1OSI/P1D
RA2/AN2/VREF-/VRL 7 14 RB7/T1OSI/P1D
RA3/AN3/VREF+/VRH 7 12 RB6/T1OSO/T1CKI/P1C
RB0/AN4/INT 8 11 RB5/SDO/P1B RA3/AN3/VREF+/VRH 8 13 RB6/T1OSO/T1CKI/P1C
RB1/AN5/SS 10 RB4/SDI/SDA RB0/AN4/INT 9 12 RB5/SDO/P1B
9
RB1/AN5/SS 10 11 RB4/SDI/SDA

Note 1: VSS pins 5 and 6 must be tied together.

2: VDD pins 15 and 16 must be tied together.

Key Features
PICmicroTM Mid-Range MCU Family PIC16C717 PIC16C770 PIC16C771
Reference Manual, (DS33023)

Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz

RESETS (and Delays) POR, BOR, MCLR, POR, BOR, MCLR, POR, BOR, MCLR,
WDT (PWRT, OST) WDT (PWRT, OST) WDT (PWRT, OST)
Program Memory (14-bit words) 2K 2K 4K
Data Memory (bytes) 256 256 256
Interrupts 10 10 10
I/O Ports Ports A,B Ports A,B Ports A,B
Timers 3 3 3
Enhanced Capture/Compare/PWM (ECCP) 1 1 1
modules
Serial Communications MSSP MSSP MSSP
12-bit Analog-to-Digital Module – 6 input channels 6 input channels

10-bit Analog-to-Digital Module 6 input channels – –

Instruction Set 35 Instructions 35 Instructions 35 Instructions

DS41120B-page 2  2002 Microchip Technology Inc.

 PIC16C717/770/771
Table of Contents

1.0 Device Overview ...................................................................................................................................................... 5

2.0 Memory Organization............................................................................................................................................... 9
3.0 I/O Ports ................................................................................................................................................................. 25
4.0 Program Memory Read (PMR) .............................................................................................................................. 41
5.0 Timer0 Module ....................................................................................................................................................... 45
6.0 Timer1 Module ....................................................................................................................................................... 47
7.0 Timer2 Module ....................................................................................................................................................... 51
8.0 Enhanced Capture/Compare/PWM (ECCP) Modules............................................................................................ 53
9.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................. 65
10.0 Voltage Reference Module and Low-voltage Detect.......................................................................................... 101
11.0 Analog-to-Digital Converter (A/D) Module.......................................................................................................... 105
12.0 Special Features of the CPU ............................................................................................................................. 117
13.0 Instruction Set Summary.................................................................................................................................... 133
14.0 Development Support ........................................................................................................................................ 141
15.0 Electrical Characteristics.................................................................................................................................... 147
16.0 DC and AC Characteristics Graphs and Tables................................................................................................. 179
17.0 Packaging Information ....................................................................................................................................... 197
APPENDIX A: Revision History ............................................................................................................................... 207
APPENDIX B: Device Differences ............................................................................................................................ 208
Index .......................................................................................................................................................................... 209
On-Line Support.......................................................................................................................................................... 215
Reader Response ....................................................................................................................................................... 216
PIC16C717/770/771 Product Identification System .................................................................................................... 217

TO OUR VALUED CUSTOMERS

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 2002 Microchip Technology Inc. DS41120B-page 3

PIC16C717/770/771
NOTES:

DS41120B-page 4  2002 Microchip Technology Inc.

 PIC16C717/770/771
1.0 DEVICE OVERVIEW sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
This document contains device-specific information. of the peripheral modules.
Additional information may be found in the PICmicroTM
There are three devices (PIC16C717, PIC16C770 and
Mid-Range MCU Family Reference Manual,
PIC16C771) covered by this data sheet. The
(DS33023), which may be obtained from your local
PIC16C717 device comes in 18/20-pin packages and
Microchip Sales Representative or downloaded from
the PIC16C770/771 devices come in 20-pin packages.
the Microchip website. The Reference Manual should
be considered a complementary document to this data The following two figures are device block diagrams of
the PIC16C717 and the PIC16C770/771.

FIGURE 1-1: PIC16C717 BLOCK DIAGRAM

13 Data Bus 8 PORTA
Program Counter
EPROM RA0/AN0
Program RA1/AN1/LVDIN
Memory RA2/AN2/VREF-/VRL
RAM
8 Level Stack RA3/AN3/VREF+/VRH
2K x 14 File RA4/T0CKI
(13-bit) Registers
RA5/MCLR/VPP
256 x 8 RA6/OSC2/CLKOUT
Program
14 Program Memory RAM RA7/OSC1/CLKIN
Bus
Read (PMR) 9 Addr(1)

Addr MUX
Instruction reg PORTB
7 Indirect RB0/AN4/INT
Direct Addr
8 Addr RB1/AN5/SS
FSR reg RB2/SCK/SCL
RB3/CCP1/P1A
RB4/SDI/SDA
STATUS reg
Internal 8 RB5/SDO/P1B
4 MHz, 37 kHz RB6/T1OSO/T1CKI/P1C
and ER mode RB7/T1OSI/P1D
3 MUX
Instruction
Decode &
Control Power-up
Timer
ALU
Timing Oscillator
Generation Start-up Timer 8
OSC1/CLKIN
OSC2/CLKOUT Power-on
VDD, VSS Reset W reg
Watchdog
Timer
Brown-out
Reset

10-bit Bandgap Low-voltage

ADC Reference Detect

Timer0 Timer1 Timer2

Master
Enhanced CCP
Synchronous
(ECCP)
Serial Port (MSSP)

Note 1: Higher order bits are from the STATUS register.

 2002 Microchip Technology Inc. DS41120B-page 5

PIC16C717/770/771
FIGURE 1-2: PIC16C770/771 BLOCK DIAGRAM

13 Data Bus 8 PORTA

Program Counter
RA0/AN0
EPROM RA1/AN1/LVDIN
Program RA2/AN2/VREF-/VRL
RAM
Memory(2) 8 Level Stack RA3/AN3/VREF+/VRH
File RA4/T0CKI
(13-bit) Registers
RA5/MCLR/VPP
256 x 8 RA6/OSC2/CLKOUT
Program 14 Program Memory RAM RA7/OSC1/CLKIN
Bus
Read (PMR) 9 Addr(1)

Addr MUX
Instruction reg PORTB
7 Indirect
Direct Addr RB0/AN4/INT
8 Addr
RB1/AN5/SS
FSR reg RB2/SCK/SCL
RB3/CCP1/P1A
STATUS reg RB4/SDI/SDA
Internal 8 RB5/SDO/P1B
4 MHz, 37 kHz RB6/T1OSO/T1CKI/P1C
and ER mode RB7/T1OSI/P1D
3 MUX
Instruction
Decode &
Control Power-up
Timer
ALU
Timing Oscillator
Generation Start-up Timer 8
OSC1/CLKIN
OSC2/CLKOUT Power-on
VDD, VSS Reset W reg
Watchdog
Timer
Brown-out
Reset

AVDD 12-bit Bandgap Low-voltage

AVSS ADC Reference Detect

Timer0 Timer1 Timer2

Master
Enhanced CCP
Synchronous
(ECCP) Serial Port (MSSP)

Note 1: Higher order bits are from the STATUS register.

2: Program memory for PIC16C770 is 2K x 14. Program memory for PIC16C771 is 4K x 14.

DS41120B-page 6  2002 Microchip Technology Inc.

 PIC16C717/770/771
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION
Input Output
Name Function Description
Type Type
RA0 ST CMOS Bi-directional I/O
RA0/AN0
AN0 AN A/D input
RA1 ST CMOS Bi-directional I/O
RA1/AN1/LVDIN AN1 AN A/D input
LVDIN AN LVD input reference
RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input
RA2/AN2/VREF-/VRL
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input
RA3/AN3/VREF+/VRH
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4 ST OD Bi-directional I/O
RA4/T0CKI
T0CKI ST TMR0 clock input
RA5 ST Input port
RA5/MCLR/VPP MCLR ST Master clear
VPP Power Programming voltage
RA6 ST CMOS Bi-directional I/O
RA6/OSC2/CLKOUT OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7 ST CMOS Bi-directional I/O
RA7/OSC1/CLKIN OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/ER resistor connection
RB0 TTL CMOS Bi-directional I/O(1)
RB0/AN4/INT AN4 AN A/D input
INT ST Interrupt input
RB1 TTL CMOS Bi-directional I/O(1)
RB1/AN5/SS AN5 AN A/D input
SS ST SSP slave select input
RB2 TTL CMOS Bi-directional I/O(1)
RB2/SCK/SCL SCK ST CMOS Serial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3 TTL CMOS Bi-directional I/O(1)
RB3/CCP1/P1A CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4 TTL CMOS Bi-directional I/O(1)
RB4/SDI/SDA SDI ST Serial data in for SPI
SDA ST OD Serial data I/O for I2C
RB5 TTL CMOS Bi-directional I/O(1)
RB5/SDO/P1B SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.

 2002 Microchip Technology Inc. DS41120B-page 7

PIC16C717/770/771
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
RB6/T1OSO/T1CKI/P1C
T1CKI CMOS TMR1 clock input
P1C CMOS PWM P1C output
RB7 TTL CMOS Bi-directional I/O(1)
RB7/T1OSI/P1D T1OSI XTAL TMR1 crystal/resonator
P1D CMOS PWM P1D output
VSS VSS Power Ground reference for logic and I/O pins
VDD VDD Power Positive supply for logic and I/O pins
AVSS(2) AVSS Power Ground reference for analog
AVDD(2) AVDD Power Positive supply for analog
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.

DS41120B-page 8  2002 Microchip Technology Inc.

 PIC16C717/770/771
2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK OF THE
There are two memory blocks in each of these PICmi-
PIC16C771
cro® microcontrollers. Each block (Program Memory
and Data Memory) has its own bus, so that concurrent
access can occur. PC<12:0>
Additional information on device memory may be found CALL, RETURN 13
in the PICmicro Mid-Range MCU Family Reference RETFIE, RETLW
Manual, (DS33023).
Stack Level 1
2.1 Program Memory Organization
Stack Level 2
The PIC16C717/770/771 devices have a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. The PIC16C717 and the Stack Level 8
PIC16C770 have 2K x 14 words of program memory.
The PIC16C771 has 4K x 14 words of program mem-
ory. Accessing a location above the physically imple- RESET Vector 0000h
mented address will cause a wrap-around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
Interrupt Vector 0004h
FIGURE 2-1: PROGRAM MEMORY MAP 0005h
AND STACK OF THE Page 0
On-chip 07FFh
PIC16C717 AND PIC16C770 Program
0800h
Memory Page 1
PC<12:0>
0FFFh
CALL, RETURN 13
RETFIE, RETLW
1000h

Stack Level 1
Stack Level 2
3FFFh

Stack Level 8
2.2 Data Memory Organization
The data memory is partitioned into multiple banks,
RESET Vector 0000h which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.

Interrupt Vector 0004h RP1 RP0 (STATUS<6:5>)

On-chip 0005h = 00 → Bank0
Program Page 0 = 01 → Bank1
Memory 07FFh = 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some frequently used special func-
tion registers from one bank are mirrored in another
3FFFh bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indi-
rectly, through the File Select Register FSR.

 2002 Microchip Technology Inc. DS41120B-page 9

PIC16C717/770/771
FIGURE 2-3: REGISTER FILE MAP

File File File File

Address Address Address Address
Indirect addr.(*) 00h Indirect addr.(*)
80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
07h 87h 107h 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch
PIR2 0Dh PIE2 8Dh PMADRL 10Dh 18Dh
TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh
TMR1H 0Fh 8Fh PMADRH 10Fh 18Fh
T1CON 10h 90h 110h 190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUB 95h 115h 195h
CCPR1H 16h IOCB 96h 116h 196h
CCP1CON 17h P1DEL 97h 117h 197h
18h 98h 118h 198h
19h 99h 119h 199h
1Ah 9Ah 11Ah 19Ah
1Bh REFCON 9Bh 11Bh 19Bh
1Ch LVDCON 9Ch 11Ch 19Ch
1Dh ANSEL 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General General
Purpose Purpose
General Register
Purpose Register
80 Bytes 80 Bytes
Register
96 Bytes EFh 16Fh 1EFh
F0h accesses 170h accesses 1F0h
accesses
70h-7Fh 70h - 7Fh 70h - 7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ’0’.

* Not a physical register.

DS41120B-page 10  2002 Microchip Technology Inc.

 PIC16C717/770/771
2.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
The Special Function Registers are registers used by ciated with the core functions are described in detail in
the CPU and Peripheral Modules for controlling the this section. Those related to the operation of the
desired operation of the device. These registers are peripheral features are described in detail in that
implemented as static RAM. A list of these registers is peripheral feature section.
given in Table 2-1.

TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY

Value on: Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on
BOR Page:

Bank 0

00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23

01h TMR0 Timer0 module’s register xxxx xxxx 45

02h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22

03h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 14

04h(3) FSR Indirect data memory address pointer xxxx xxxx 23

05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 25

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx11 33

07h — Unimplemented — —

08h — Unimplemented — —

09h — Unimplemented — —

0Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22

0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16

0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0---0000 18

0Dh PIR2 LVDIF — — — BCLIF — — — 0--- 0--- 20

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx 47

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx 47

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 47

11h TMR2 Timer2 module’s register 0000 0000 51

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 51

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 70

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx 54

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx 54

17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53

18h — Unimplemented — —

19h — Unimplemented — —
1Ah — Unimplemented — —

1Bh — Unimplemented — —

1Ch — Unimplemented — —
1Dh — Unimplemented — —

1Eh ADRESH A/D High Byte Result Register xxxx xxxx 107

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 107

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.

 2002 Microchip Technology Inc. DS41120B-page 11

PIC16C717/770/771
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on
BOR Page:

Bank 1

80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15

82h(3) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22
(3)
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 14
84h(3) FSR Indirect data memory address pointer xxxx xxxx 23

85h TRISA PORTA Data Direction Register 1111 1111 25

86h TRISB PORTB Data Direction Register 1111 1111 33

87h — Unimplemented — —

88h — Unimplemented — —

89h — Unimplemented — —

8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22

8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16

8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 17

8Dh PIE2 LVDIE — — — BCLIE — — — 0--- 0--- 19

8Eh PCON — — — — OSCF — POR BOR ---- 1-qq 21

8Fh — Unimplemented — —

90h — Unimplemented — —

91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 69

92h PR2 Timer2 Period Register 1111 1111 52

2
93h SSPADD Synchronous Serial Port (I C mode) Address Register 0000 0000 76

94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 66

95h WPUB PORTB Weak Pull-up Control 1111 1111 34

96h IOCB PORTB Interrupt on Change Control 1111 0000 34

97h P1DEL PWM 1 Delay value 0000 0000 62

98h — Unimplemented — —

99h — Unimplemented — —

9Ah — Unimplemented — —

9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 102

9Ch LVDCON — — BGST LVDEN LVV3 LVV2 LVV1 LVV0 --00 0101 101
9Dh ANSEL — — Analog Channel Select --11 1111 25

9Eh ADRESL A/D Low Byte Result Register xxxx xxxx 107

9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 107

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.

DS41120B-page 12  2002 Microchip Technology Inc.

 PIC16C717/770/771
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on
BOR Page:

Bank 2

100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23

101h TMR0 Timer0 module’s register xxxx xxxx 45

102h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22

103h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 14

104h(3) FSR Indirect data memory address pointer xxxx xxxx 23

105h — Unimplemented — —

106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx11 33

107h — Unimplemented — —

108h — Unimplemented — —

109h — Unimplemented — —
(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
10Ah
(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
10Bh
10Ch PMDATL Program memory read data low xxxx xxxx

10Dh PMADRL Program memory read address low xxxx xxxx

10Eh PMDATH — — Program memory read data high --xx xxxx

10Fh PMADRH — — — — Program memory read address high ---- xxxx

110h-
— Unimplemented — —
11Fh

Bank 3

180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23

181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15

182h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22

183h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 14

184h(3) FSR Indirect data memory address pointer xxxx xxxx 23

185h — Unimplemented — —

186h TRISB PORTB Data Direction Register 1111 1111 33

187h — Unimplemented — —

188h — Unimplemented — —
189h — Unimplemented — —

18Ah (1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22

(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
18Bh

18Ch PMCON1 Reserved — — — — — — RD 1--- ---0

18Dh-
— Unimplemented — —
18Fh

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.

 2002 Microchip Technology Inc. DS41120B-page 13

PIC16C717/770/771
2.2.2.1 STATUS REGISTER For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 2-1, contains as 000u u1uu (where u = unchanged).
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, as with any other register. If the STATUS affect the Z, C or DC bits from the STATUS register. For
register is the destination for an instruction that affects other instructions not affecting any status bits, see the
the Z, DC or C bits, then the write to these three bits is "Instruction Set Summary."
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not Note: The C and DC bits operate as a borrow
writable. Therefore, the result of an instruction with the and digit borrow bit, respectively, in sub-
STATUS register as destination may be different than traction. See the SUBLW and SUBWF
intended. instructions for examples.

REGISTER 2-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 14  2002 Microchip Technology Inc.

 PIC16C717/770/771
2.2.2.2 OPTION_REG REGISTER
Note: To achieve a 1:1 prescaler assignment for
The OPTION_REG register is a readable and writable the TMR0 register, assign the prescaler to
register, which contains various control bits to configure the Watchdog Timer.
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.

REGISTER 2-2: OPTION REGISTER (OPTION_REG: 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit(1)

1 = PORTB weak pull-ups are disabled
0 = PORTB weak pull-ups are enabled by the WPUB register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate

000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

Note 1: Individual weak pull-up on RB pins can be enabled/disabled from the weak pull-up
PORTB Register (WPUB).

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 15

PIC16C717/770/771
2.2.2.3 INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
The INTCON Register is a readable and writable regis- condition occurs, regardless of the state of
ter, which contains various enable and flag bits for the its corresponding enable bit or the global
TMR0 register overflow, RB Port change and External enable bit, GIE (INTCON<7>). User soft-
RB0/INT pin interrupts. ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.

REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit(1)
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:0> pins changed state (must be cleared in software)
0 = None of the RB<7:0> pins have changed state

Note 1: Individual RB pin interrupt-on-change can be enabled/disabled from the

Interrupt-on-Change PORTB register (IOCB).

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 16  2002 Microchip Technology Inc.

 PIC16C717/770/771
2.2.2.4 PIE1 REGISTER Note: Bit PEIE (INTCON<6>) must be set to
This register contains the individual enable bits for the enable any peripheral interrupt.
peripheral interrupts.

REGISTER 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1: 8Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0

bit 7 Unimplemented: Read as ’0’

bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 17

PIC16C717/770/771
2.2.2.5 PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
This register contains the individual flag bits for the condition occurs, regardless of the state of
peripheral interrupts. its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.

REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’.

bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2 C Slave / Master
A transmission/reception has taken place.
I2 C Master
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was IDLE (Multi-master system).
A STOP condition occurred while the SSP module was IDLE (Multi-master system).
0 = No SSP interrupt condition has occurred.
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 18  2002 Microchip Technology Inc.

 PIC16C717/770/771
2.2.2.6 PIE2 REGISTER

This register contains the individual enable bits for the

SSP bus collision and low voltage detect interrupts.

REGISTER 2-6: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2: 8Dh)

R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIE — — — BCLIE — — —
bit 7 bit 0

bit 7 LVDIE: Low Voltage Detect Interrupt Enable bit

1 = LVD Interrupt is enabled
0 = LVD Interrupt is disabled
bit 6-4 Unimplemented: Read as '0'
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Bus Collision interrupt is enabled
0 = Bus Collision interrupt is disabled
bit 2-0 Unimplemented: Read as '0'

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 19

PIC16C717/770/771
2.2.2.7 PIR2 REGISTER .
Note: Interrupt flag bits get set when an interrupt
This register contains the SSP Bus Collision and low- condition occurs, regardless of the state of
voltage detect interrupt flag bits. its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.

REGISTER 2-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)

R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIF — — — BCLIF — — —
bit 7 bit 0

bit 7 LVDIF: Low Voltage Detect Interrupt Flag bit

1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software)
0 = The supply voltage is greater than the specified LVD voltage
bit 6-4 Unimplemented: Read as '0'
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred while the SSP module configured in I2C Master was
transmitting (must be cleared in software)
0 = No bus collision occurred
bit 2-0 Unimplemented: Read as '0'

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 20  2002 Microchip Technology Inc.

 PIC16C717/770/771
2.2.2.8 PCON REGISTER Note: BOR is unknown on Power-on Reset. It
The Power Control (PCON) register contains a flag bit must then be set by the user and checked
to allow differentiation between a Power-on Reset on subsequent RESETS to see if BOR is
(POR) to an external MCLR Reset or WDT Reset. clear, indicating a brown-out has occurred.
Those devices with brown-out detection circuitry con- The BOR status bit is a don’t care and is
tain an additional bit to differentiate a Brown-out Reset not necessarily predictable if the brown-out
condition from a Power-on Reset condition. circuit is disabled (by clearing the BODEN
bit in the Configuration word).
The PCON register also contains the frequency select
bit of the INTRC or ER oscillator.

REGISTER 2-8: POWER CONTROL REGISTER (PCON: 8Eh)

U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-q R/W-q
— — — — OSCF — POR BOR
bit 7 bit 0

bit 7-4 Unimplemented: Read as '0'

bit 3 OSCF: Oscillator Speed bit
INTRC Mode
1 = 4 MHz nominal
0 = 37 kHz nominal
ER Mode
1 = Oscillator frequency depends on the external resistor value on the OSC1 pin.
0 = 37 kHz nominal
All other modes
x = Ignored
bit 2 Unimplemented: Read as '0'
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit (See Section 2.2.2.8 Note)
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend: q = Value depends on conditions

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 21

PIC16C717/770/771
2.3 PCL and PCLATH 2.4 Stack
The program counter (PC) specifies the address of the The stack allows a combination of up to 8 program calls
instruction to fetch for execution. The PC is 13 bits and interrupts to occur. The stack contains the return
wide. The low byte is called the PCL register. This reg- address from this branch in program execution.
ister is readable and writable. The high byte is called Mid-range devices have an 8-level deep x 13-bit wide
the PCH register. This register contains the PC<12:8> hardware stack. The stack space is not part of either
bits and is not directly readable or writable. All updates program or data space and the stack pointer is not
to the PCH register occur through the PCLATH register. readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
2.3.1 PROGRAM MEMORY PAGING
causes a branch. The stack is POPed in the event of a
PIC16C717/770/771 devices are capable of address- RETURN, RETLW or a RETFIE instruction execution.
ing a continuous 8K word block of program memory. PCLATH is not modified when the stack is PUSHed or
The CALL and GOTO instructions provide only 11 bits of POPed.
address to allow branching within any 2K program After the stack has been PUSHed eight times, the ninth
memory page. When doing a CALL or GOTO instruction, push overwrites the value that was stored from the first
the upper 2 bits of the address are provided by push. The tenth push overwrites the second push (and
PCLATH<4:3>. When doing a CALL or GOTO instruc- so on).
tion, the user must ensure that the page select bits are
programmed so that the desired program memory
FIGURE 2-4: LOADING OF PC IN
page is addressed. A return instruction pops a PC
DIFFERENT SITUATIONS
address off the stack onto the PC register. Therefore,
manipulation of the PCLATH<4:3> bits are not required PCH PCL
for the return instructions (which POPs the address 12 8 7 0 Instruction with
PCL as
from the stack). Destination
PCLATH<4:0> 8
ALU
5

PCLATH

PCH PCL
12 1110 8 7 0
GOTO, CALL
PCLATH<4:3> 11
Opcode <10:0>
2

PCLATH

DS41120B-page 22  2002 Microchip Technology Inc.

 PIC16C717/770/771
The INDF register is not a physical register. Address- EXAMPLE 2-1: How to Clear RAM Using
ing INDF actually addresses the register whose Indirect Addressing
address is contained in the FSR register (FSR is a movlw 0x20 ;initialize pointer
pointer). This is indirect addressing. movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
Reading INDF itself indirectly (FSR = 0) will produce
incf FSR ;inc pointer
00h. Writing to the INDF register indirectly results in a
btfss FSR,4 ;all done?
no-operation (although STATUS bits may be affected). goto NEXT ;NO, clear next
A simple program to clear RAM locations 20h-2Fh CONTINUE
using indirect addressing is shown in Example 2-1. : ;YES, continue

An effective 9-bit address is obtained by concatenating

the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-5.

FIGURE 2-5: DIRECT/INDIRECT ADDRESSING

Direct Addressing Indirect Addressing

RP1:RP0 6 from opcode 0 IRP 7 FSR register 0

bank select location select bank select location select

00 01 10 11
00h 80h 100h 180h

Data
Memory(1)

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Note 1: For register file map detail see Figure 2-3.

 2002 Microchip Technology Inc. DS41120B-page 23

PIC16C717/770/771
NOTES:

DS41120B-page 24  2002 Microchip Technology Inc.

 PIC16C717/770/771
3.0 I/O PORTS present on a pin, the pin must be configured as an ana-
log input to prevent unnecessary current draw from the
Some pins for these I/O ports are multiplexed with an power supply. The Analog Select Register (ANSEL)
alternate function for the peripheral features on the allows the user to individually select the Digital/Analog
device. In general, when a peripheral is enabled, that mode on these pins. When the Analog mode is active,
pin may not be used as a general purpose I/O pin. the port pin will always read 0.
Additional information on I/O ports may be found in the Note 1: On a Power-on Reset, the ANSEL regis-
PICmicro™ Mid-Range MCU Family Reference Man- ter configures these mixed-signal pins as
ual, (DS33023). Analog mode.
3.1 I/O Port Analog/Digital Mode 2: If a pin is configured as Analog mode, the
RA pin will always read '0' and RB pin will
The PIC16C717/770/771 have two I/O ports: PORTA always read '1', even if the digital output is
and PORTB. Some of these port pins are mixed-signal active.
(can be digital or analog). When an analog signal is

REGISTER 3-1: ANALOG SELECT REGISTER (ANSEL: 9Dh)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0

bit 7-6 Reserved: Do not use

bit 5-0 ANS<5:0>: Analog Select between analog or digital function on pins AN<5:0>, respectively.
0 = Digital I/O. Pin is assigned to port or special function.
1 = Analog Input. Pin is assigned as analog input.

Note: Setting a pin to an analog input disables the digital input buffer on the pin. The cor-
responding TRIS bit should be set to Input mode when using pins as analog inputs.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

3.2 PORTA and the TRISA Register these pins as analog input/output, the ANSEL register
must have the proper value to individually select the
PORTA is a 8-bit wide bi-directional port. The corre- Analog mode of the corresponding pins.
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin Note: Upon RESET, the ANSEL register config-
an input (i.e., put the corresponding output driver in a ures the RA<3:0> pins as analog inputs.
Hi-impedance mode). Clearing a TRISA bit (=0) will All RA<3:0> pins will read as '0'.
make the corresponding PORTA pin an output (i.e., put Pin RA4 is multiplexed with the Timer0 module clock
the contents of the output latch on the selected pin). input to become the RA4/T0CKI pin. The RA4/T0CKI
Reading the PORTA register reads the status of the pin is a Schmitt Trigger input and an open drain output.
pins, whereas writing to it will write to the port latch. All Pin RA5 is multiplexed with the device RESET (MCLR)
write operations are read-modify-write operations. and programming input (VPP) functions. The RA5/
Therefore, a write to a port implies that the port pins are MCLR/VPP input only pin has a Schmitt Trigger input
read, this value is modified, and then written to the port buffer. All other RA port pins have Schmitt Trigger input
data latch. buffers and full CMOS output buffers.
Pins RA<3:0> are multiplexed with analog functions, Pins RA6 and RA7 are multiplexed with the oscillator
such as analog inputs to the A/D converter, analog input and output functions.
VREF inputs, and the onboard bandgap reference out-
The TRISA register controls the direction of the RA
puts. When the analog peripherals are using any of
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.

 2002 Microchip Technology Inc. DS41120B-page 25

PIC16C717/770/771
EXAMPLE 3-1: Initializing PORTA
BCF STATUS, RP0 ; Select Bank 0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0Fh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<7:4> as outputs. RA<7:6>availability depends on oscillator selection.
MOVLW 03 ; Set RA<1:0> as analog inputs, RA<7:2> are digital I/O
MOVWF ANSEL
BCF STATUS, RP0 ; Return to Bank 0

FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0, RA1/AN1/LVDIN

Data Data Latch

Bus
D Q
VDD VDD
WR
PORT
CK Q
P

TRIS Mode

D Q N

WR
TRIS VSS VSS
CK Q

RD
TRIS

Analog Select
Schmitt
D Q
Trigger
WR
ANSEL
CK Q

Q D

EN

RD
PORT

To A/D Converter input or LVD Module input

DS41120B-page 26  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 3-2: BLOCK DIAGRAM OF RA2/AN2/VREF-/VRL AND RA3/AN3/VREF+/VRH

Data Data Latch

Bus
D Q
VDD VDD
WR
PORT
CK Q
P
TRIS Mode
D Q N

WR
TRIS VSS VSS
CK Q

RD
TRIS
Analog Select
D Q Schmitt
Trigger
WR
ANSEL
CK Q

Q D

EN
RD
PORT

To A/D Converter input

and VREF+, VREF- inputs

VRH, VRL outputs

(From VREF-LVD-BOR Module)

VRH, VRL output enable

Sense input for

VRH, VRL amplifier

 2002 Microchip Technology Inc. DS41120B-page 27

PIC16C717/770/771
FIGURE 3-3: BLOCK DIAGRAM OF RA4/T0CKI

Data Data Latch

Bus
D Q

WR
Port
CK Q

TRIS Latch
N
D Q

WR
TRIS
CK Q VSS

VSS

RD Schmitt Trigger
TRIS
Input Buffer

Q D

EN

RD
PORT

TMR0 clock input

DS41120B-page 28  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 3-4: BLOCK DIAGRAM OF RA5/MCLR/VPP

To MCLR Circuit
MCLR Filter

Program Mode
HV Detect

Data VSS
Bus

RD
TRIS VSS

Schmitt
Trigger

Q D

EN

RD PORT

 2002 Microchip Technology Inc. DS41120B-page 29

PIC16C717/770/771
FIGURE 3-5: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN

(INTRC or ER) and CLKOUT

CLKOUT (Fosc/4) From OSC1 Oscillator

1 Circuit

0
VDD

Data D Q VDD
Bus

WR Q P
CK
PORTA VSS
Data Latch
D Q

N
WR CK Q
TRISA
TRIS Latch
VSS

Schmitt Trigger
Input Buffer
RD TRISA EC or [(ER or INTRC) and CLKOUT]

Q D

EN

RD PORTA

DS41120B-page 30  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 3-6: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN

To OSC2 Oscillator
Circuit VDD
To Chip Clock Drivers
Schmitt Trigger
Data D Q VDD Input Buffer
Bus
EC Mode
WR Q P
CK
PORTA
Data Latch
D Q

WR N
TRISA CK Q
TRIS Latch
INTRC Vss

INTRC
RD TRISA
Schmitt Trigger
Input Buffer

Q D

EN

RD PORTA

 2002 Microchip Technology Inc. DS41120B-page 31

PIC16C717/770/771
TABLE 3-1: PORTA FUNCTIONS

Input Output
Name Function Description
Type Type
RA0 ST CMOS Bi-directional I/O
RA0/AN0
AN0 AN A/D input
RA1 ST CMOS Bi-directional I/O
RA1/AN1/LVDIN AN1 AN A/D input
LVDIN AN LVD input reference
RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input
RA2/AN2/VREF-/VRL
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input
RA3/AN3/VREF+/VRH
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4 ST OD Bi-directional I/O
RA4/T0CKI
T0CKI ST TMR0 clock input
RA5 ST Input port
RA5/MCLR/VPP MCLR ST Master clear
VPP Power Programming voltage
RA6 ST CMOS Bi-directional I/O
RA6/OSC2/CLKOUT OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7 ST CMOS Bi-directional I/O
RA7/OSC1/CLKIN OSC1 XTAL Crystal/resonator
CLKIN ST/AN External clock input/ER resistor connection

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other
BOR RESETS

05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 uuuu 0000

85h TRISA PORTA Data Direction Register 1111 1111 1111 1111

9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by PORTA.

DS41120B-page 32  2002 Microchip Technology Inc.

 PIC16C717/770/771
3.3 PORTB and the TRISB Register Each of the PORTB pins, if configured as input, also
has an interrupt-on-change feature, which can be indi-
PORTB is an 8-bit wide bi-directional port. The corre- vidually selected from the IOCB register. The RBIE bit
sponding data direction register is TRISB. Setting a in the INTCON register functions as a global enable bit
TRISB bit (=1) will make the corresponding PORTB pin to turn on/off the interrupt-on-change feature. The
an input (i.e., put the corresponding output driver in a selected inputs are compared to the old value latched
Hi-impedance mode). Clearing a TRISB bit (=0) will on the last read of PORTB. The "mismatch" outputs are
make the corresponding PORTB pin an output (i.e., OR’ed together to generate the RB Port Change Inter-
put the contents of the output latch on the selected pin). rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
EXAMPLE 3-2: Initializing PORTB
user, in the interrupt service routine, can clear the inter-
BCF STATUS, RP0 ;
rupt in the following manner:
CLRF PORTB ; Initialize PORTB by
; clearing output a) Any read or write of PORTB. This will end the
; data latches mismatch condition.
BSF STATUS, RP0 ; Select Bank 1
a) Clear flag bit RBIF.
MOVLW 0xCF ; Value used to
; initialize data A mismatch condition will continue to set flag bit RBIF.
; direction Reading PORTB will end the mismatch condition and
MOVWF TRISB ; Set RB<3:0> as inputs allow flag bit RBIF to be cleared.
; RB<5:4> as outputs
; RB<7:6> as inputs The interrupt-on-change feature is recommended for
MOVLW 0x30 ; Set RB<1:0> as analog wake-up on key depression operation and operations
inputs where PORTB is only used for the interrupt-on-change
MOVWF ANSEL ; feature. Polling of PORTB is not recommended while
BCF STATUS, RP0 ; Return to Bank 0 using the interrupt-on-change feature.

Each of the PORTB pins has an internal pull-up, which

can be individually enabled from the WPUB register. A
single global enable bit can turn on/off the enabled pull-
ups. Clearing the RBPU bit, (OPTION_REG<7>),
enables the weak pull-up resistors. The weak pull-up is
automatically turned off when the port pin is configured
as an output. The pull-ups are disabled on a Power-on
Reset.

 2002 Microchip Technology Inc. DS41120B-page 33

PIC16C717/770/771
REGISTER 3-2: WEAK PULL-UP PORTB REGISTER (WPUB: 95h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0

bit 7-0 WPUB<7:0>: PORTB Weak Pull-Up Control bits

1 = Weak pull-up enabled
0 = Weak pull-up disabled

Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG
register must be cleared.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRIS = 0).

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

REGISTER 3-3: INTERRUPT-ON-CHANGE PORTB REGISTER (IOCB: 96h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
bit 7 bit 0

bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bits

1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled

Note: The interrupt enable bits GIE and RBIE in the INTCON Register must be set for indi-
vidual interrupts to be recognized.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 34  2002 Microchip Technology Inc.

 PIC16C717/770/771
The RB0 pin is multiplexed with the A/D converter ana- The RB1 pin is multiplexed with the A/D converter ana-
log input 4 and the external interrupt input (RB0/AN4/ log input 5 and the MSSP module slave select input
INT). When the pin is used as analog input, the ANSEL (RB1/AN5/SS). When the pin is used as analog input,
register must have the proper value to select the RB0 the ANSEL register must have the proper value to
pin as Analog mode. select the RB1 pin as Analog mode.
Note: Upon RESET, the ANSEL register config-
ures the RB1 and RB0 pins as analog inputs.
Both RB1 and RB0 pins will read as ’1’.

FIGURE 3-7: BLOCK DIAGRAM OF RB0/AN4/INT, RB1/AN5/SS PIN

WPUB Reg
Data Bus
D Q
WR
WPUB
CK Q VDD
RBPU
P weak
pull-up
PORTB Reg VDD

D Q
VDD
WR
PORT CK Q
P

TRIS Reg N
D Q
WR
TRIS VSS
CK Q

RD
TRIS VSS
Analog Select
D Q
WR
ANSEL
CK Q

TTL
IOCB Reg
D Q Schmitt
WR Set Trigger
IOCB RBIF
CK Q Q D
...

From Q1
EN
RB<7:0> pins

Q D
Q3
Q D
EN
EN
RD
EN
PORT

To INT input or MSSP module

To A/D Converter

 2002 Microchip Technology Inc. DS41120B-page 35

PIC16C717/770/771
FIGURE 3-8: BLOCK DIAGRAM OF RB2/SCK/SCL, RB3/CCP1/P1A, RB4/SDI/SDA,
RB5/SDO/P1B

WPUB Reg
Data Bus
D Q
WR
WPUB
CK Q VDD
Spec. Func En. RBPU VDD
SDA, SDO, SCK, CCP1, P1A, P1B P weak
pull-up
PORTB Reg 1 VDD

D Q 0
P
WR
PORT
CK Q
N

TRIS Reg
D Q VSS
WR
TRIS VSS
CK Q

RD
TRIS
TTL

IOCB Reg
Schmitt
D Q Trigger
WR Set
IOCB RBIF
CK Q Q D
...

From Q1
EN
RB<7:0> pins

Q D
Q D
Q3
EN
EN EN
RD
PORT

SCK, SCL, CC, SDI, SDA inputs

DS41120B-page 36  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 3-9: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/P1C
WPUB Reg
Data Bus VDD
D Q RBPU
WR P weak pull-up
WPUB
CK Q
VDD

D Q P
VDD
WR PORTB
CK Q

Data Latch

D Q

WR TRISB N
CK Q

TRIS Latch VSS

RD TRISB TTL
Input
T1OSCEN Buffer

RD PORTB
IOCB Reg
D Q
WR
IOCB
CK Q CMOS
TMR1 Clock
Serial programming clock Schmitt
Trigger
From RB7

TMR1 Oscillator

Q D

Q1
EN

Set RBIF
...

Q D
From RD Port
RB<7:0> pins EN Q3

Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB6 I/O port and P1C functions.

 2002 Microchip Technology Inc. DS41120B-page 37

PIC16C717/770/771
FIGURE 3-10: BLOCK DIAGRAM OF THE RB7/T1OSI/P1D
VDD
RBPU
TMR1 Oscillator
P weak pull-up
WPUB Reg To RB6
Data Bus
D Q
T1OSCEN
WR
WPUB
CK Q
VDD VDD

D Q P

WR PORTB CK Q

Data Latch

D Q

WR TRISB CK Q N

TRIS Latch VSS

RD TRISB
T10SCEN

TTL
RD PORTB Input
Buffer
IOCB Reg
D Q
WR
IOCB
CK Q

Serial programming input Q D

Schmitt Trigger Q1
EN
Set RBIF
...

From Q D
RB<7:0> pins
RD Port
EN Q3

Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB7 I/O port and P1D functions.

DS41120B-page 38  2002 Microchip Technology Inc.

 PIC16C717/770/771
TABLE 3-3: PORTB FUNCTIONS

Input Output
Name Function Description
Type Type
RB0 TTL CMOS Bi-directional I/O(1)
RB0/AN4/INT AN4 AN A/D input
INT ST Interrupt input
RB1 TTL CMOS Bi-directional I/O(1)
RB1/AN5/SS AN5 AN A/D input
SS ST SSP slave select input
RB2 TTL CMOS Bi-directional I/O(1)
RB2/SCK/SCL SCK ST CMOS Serial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3 TTL CMOS Bi-directional I/O(1)
RB3/CCP1/P1A CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4 TTL CMOS Bi-directional I/O(1)
RB4/SDI/SDA SDI ST Serial data in for SPI
SDA ST OD Serial data I/O for I2C
RB5 TTL CMOS Bi-directional I/O(1)
RB5/SDO/P1B SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
RB6/T1OSO/T1CKI/P1C
T1CKI CMOS TMR1 clock input
P1C CMOS PWM P1C output
RB7 TTL CMOS Bi-directional I/O(1)
RB7/T1OSI/P1D T1OSI XTAL TMR1 crystal/resonator
P1D CMOS PWM P1D output
Note 1: Bit programmable pull-ups.

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other
BOR RESETS

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx11 uuuu uu11

86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111

81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

95h WPUB PORTB Weak Pull-up Control 1111 1111 1111 1111

96h IOCB PORTB Interrupt on Change Control 1111 0000 1111 0000

9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

 2002 Microchip Technology Inc. DS41120B-page 39

PIC16C717/770/771
NOTES:

DS41120B-page 40  2002 Microchip Technology Inc.

 PIC16C717/770/771
4.0 PROGRAM MEMORY READ When interfacing the program memory block, the
PMDATH & PMDATL registers form a 2-byte word,
(PMR) which holds the 14-bit data. The PMADRH & PMADRL
Program memory is readable during normal operation registers form a 2-byte word, which holds the 12-bit
(full VDD range). It is indirectly addressed through the address of the program memory location being
Special Function Registers: accessed. Mid-range devices have up to 8K words of
program EPROM with an address range from 0h to
• PMCON1
3FFFh. When the device contains less memory than
• PMDATH the full address range of the PMADRH:PMARDL regis-
• PMDATL ters, the Most Significant bits of the PMADRH register
• PMADRH are ignored.
• PMADRL
4.1 PMCON1 REGISTER
PMCON1 is the control register for program memory
accesses.
Control bit RD initiates a read operation. This bit cannot
be cleared, only set, in software. It is cleared in hard-
ware at completion of the read operation.

REGISTER 4-1: PROGRAM MEMORY READ CONTROL REGISTER 1 (PMCON1: 18Ch)

R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0
Reserved — — — — — — RD
bit 7 bit 0

bit 7 Reserved: Read as ‘1’

bit 6-1 Unimplemented: Read as '0'
bit 0 RD: Read Control bit
1 = Initiates a Program memory read (read takes 2 cycles). RD is cleared in hardware.
0 = Reserved

Legend: S = Settable (cleared in hardware)

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

4.2 PMDATH AND PMDATL

REGISTERS
The PMDATH:PMDATL registers are loaded with the
contents of program memory addressed by the
PMADRH and PMADRL registers upon completion of a
Program Memory Read command.

 2002 Microchip Technology Inc. DS41120B-page 41

PIC16C717/770/771
REGISTER 4-2: PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh)
U-0 U-0 R-x R-x R-x R-x R-x R-x
— — PMD13 PMD12 PMD11 PMD10 PMD9 PMD8
bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL
after a Program Memory Read command.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-3: PROGRAM MEMORY DATA LOW (PMDATL: 10Ch)

R-x R-x R-x R-x R-x R-x R-x R-x
PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0
bit 7 bit 0

bit 7-0 PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after
a Program Memory Read command.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-4: PROGRAM MEMORY ADDRESS HIGH (PMADRH: 10Fh)

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — — PMA11 PMA10 PMA9 PMA8
bit 7 bit 0

bit 7-4 Unimplemented: Read as '0'

bit 3-0 PMA<11:8>: PMR Address bits

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-5: PROGRAM MEMORY ADDRESS LOW (PMADRL: 10Dh)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0
bit 7 bit 0

bit 7-0 PMA<7:0>: PMR Address bits

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 42  2002 Microchip Technology Inc.

 PIC16C717/770/771
4.3 READING THE EPROM PROGRAM the “BSF PMCON1,RD” instruction to be ignored. The data
MEMORY is available, in the very next cycle, in the PMDATH and
PMDATL registers; therefore it can be read as 2 bytes
To read a program memory location, the user must in the following instructions. PMDATH and PMDATL
write 2 bytes of the address to the PMADRH and registers will hold this value until another Program
PMADRL registers, then set control bit RD Memory Read or until it is written to by the user.
(PMCON1<0>). Once the read control bit is set, the
Program Memory Read (PMR) controller will use the Note: The two instructions that follow setting the
second instruction cycle after to read the data. This PMCON1 read bit must be NOPs.
causes the second instruction immediately following

EXAMPLE 4-1: OTP PROGRAM MEMORY Read

BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW MS_PROG_PM_ADDR ;
MOVWF PMADRH ; MS Byte of Program Memory Address to read
MOVLW LS_PROG_PM_ADDR ;
MOVWF PMADRL ; LS Byte of Program Memory Address to read
BSF STATUS, RP0 ; Bank 3
BSF PMCON1, RD ; Program Memory Read
NOP ; This instruction must be an NOP
NOP ; This instruction must be an NOP
next instruction ; PMDATH:PMDATL now has the data

4.4 OPERATION DURING CODE

PROTECT
When the device is code protected, the CPU can still
perform the Program Memory Read function.

FIGURE 4-1: PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Program
Memory PC PC+1 PMADRH,PMADRL PC+3 PC+4 PC+5
ADDR

INSTR(PC-1) BSF PMCON1,RD INSTR(PC+1) Forced NOP INSTR(PC+3) INSTR(PC+4)

Executed here Executed here Executed here Executed here Executed here Executed here

RD bit

PMDATH
PMDATL
register

 2002 Microchip Technology Inc. DS41120B-page 43

PIC16C717/770/771
TABLE 4-1: PROGRAM MEMORY READ REGISTER SUMMARY
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other
BOR RESETS

18Ch PMCON1 Reserved — — — — — — RD 1--- ---0 1--- ---0

10Eh PMDATH — — PMD13 PMD12 PMD11 PMD10 PMD9 PMD8 --xx xxxx --uu uuuu

10Ch PMDATL PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 xxxx xxxx uuuu uuuu

10Fh PMADRH — — — — PMA11 PMA10 PMA9 PMA8 ---- xxxx ---- uuuu

10Dh PMADRL PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Program Memory Read.

DS41120B-page 44  2002 Microchip Technology Inc.

 PIC16C717/770/771
5.0 TIMER0 MODULE Additional information on external clock requirements
is available in the PICmicro™ Mid-Range MCU Family
The Timer0 module timer/counter has the following fea- Reference Manual, (DS33023).
tures:
• 8-bit timer/counter 5.2 Prescaler
• Readable and writable An 8-bit counter is available as a prescaler for the
• Internal or external clock select Timer0 module, or as a postscaler for the Watchdog
• Edge select for external clock Timer, respectively (Figure 5-2). For simplicity, this
• 8-bit software programmable prescaler counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
• Interrupt on overflow from FFh to 00h
available which is mutually exclusively shared between
Figure 5-1 is a simplified block diagram of the Timer0 the Timer0 module and the Watchdog Timer. Thus, a
module. prescaler assignment for the Timer0 module means
Additional information on timer modules is available in that there is no prescaler for the Watchdog Timer, and
the PICmicro™ Mid-Range MCU Family Reference vice-versa.
Manual, (DS33023). The prescaler is not readable or writable.
The PSA and PS<2:0> bits (OPTION_REG<3:0>)
5.1 Timer0 Operation
determine the prescaler assignment and prescale ratio.
Timer0 can operate as a timer or as a counter. Clearing bit PSA will assign the prescaler to the Timer0
Timer mode is selected by clearing bit T0CS module. When the prescaler is assigned to the Timer0
(OPTION_REG<5>). In Timer mode, the Timer0 mod- module, prescale values of 1:2, 1:4, ..., 1:256 are
ule will increment every instruction cycle (without pres- selectable.
caler). If the TMR0 register is written, the increment is Setting bit PSA will assign the prescaler to the Watch-
inhibited for the following two instruction cycles. The dog Timer (WDT). When the prescaler is assigned to
user can work around this by writing an adjusted value the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
to the TMR0 register. selectable.
Counter mode is selected by setting bit T0CS When assigned to the Timer0 module, all instructions
(OPTION_REG<5>). In Counter mode, Timer0 will writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
increment either on every rising or falling edge of pin BSF 1, x....etc.) will clear the prescaler. When
RA4/T0CKI. The incrementing edge is determined by assigned to WDT, a CLRWDT instruction will clear the
the Timer0 Source Edge Select bit T0SE prescaler along with the WDT.
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are Note: Writing to TMR0 when the prescaler is
discussed in below. assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
When an external clock input is used for Timer0, it must
assignment.
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.

FIGURE 5-1: TIMER0 BLOCK DIAGRAM

Data Bus
Fosc/4 0
PSout 8
1
Sync with
1 Internal TMR0
clocks
RA4/T0CKI Programmable 0 PSout
pin Prescaler
T0SE (2 Tcy delay)
3
Set interrupt
PS2, PS1, PS0 PSA flag bit T0IF
T0CS on overflow
Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).

 2002 Microchip Technology Inc. DS41120B-page 45

PIC16C717/770/771
5.2.1 SWITCHING PRESCALER 5.3 Timer0 Interrupt
ASSIGNMENT
The TMR0 interrupt is generated when the TMR0 reg-
The prescaler assignment is fully under software con- ister overflows from FFh to 00h. This overflow sets bit
trol (i.e., it can be changed “on-the-fly” during program T0IF (INTCON<2>). The interrupt can be masked by
execution). clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
Note: To avoid an unintended device RESET, a
vice routine before re-enabling this interrupt. The
specific instruction sequence (shown in the
TMR0 interrupt cannot awaken the processor from
PICmicro™ Mid-Range Reference Man-
SLEEP since the timer is shut off during SLEEP.
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.

FIGURE 5-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (= Fosc/4) Data Bus

8
M 1
0
RA4/T0CKI U M
X SYNC
Pin U 2 TMR0 reg
1 0
X Cycles

T0SE
T0CS
PSA Set flag bit T0IF
on Overflow

0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer

8 - to - 1MUX PS<2:0>
PSA

0 1
WDT Enable Bit
MUX PSA

WDT
Time-out

Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>).

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other
BOR RESETS

01h,101h TMR0 Timer0 register xxxx xxxx uuuu uuuu

0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by Timer0.

DS41120B-page 46  2002 Microchip Technology Inc.

 PIC16C717/770/771
6.0 TIMER1 MODULE Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
The Timer1 module timer/counter has the following fea- Manual, (DS33023).
tures:
• 16-bit timer/counter 6.1 Timer1 Operation
(Two 8-bit registers; TMR1H and TMR1L) Timer1 can operate in one of these modes:
• Readable and writable (Both registers)
• As a timer
• Internal or external clock select
• As a synchronous counter
• Interrupt on overflow from FFFFh to 0000h
• As an asynchronous counter
• RESET from ECCP module trigger
The Operating mode is determined by the clock select
Timer1 has a control register, shown in Register 6-1. bit, TMR1CS (T1CON<1>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>). In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
Figure 6-2 is a simplified block diagram of the Timer1 edge of the external clock input.
module.

REGISTER 6-1: TIMER1 CONTROL REGISTER (T1CON: 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off(1)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI /P1C (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 47

PIC16C717/770/771
6.1.1 TIMER1 COUNTER OPERATION
In this mode, Timer1 is being incremented via an exter-
nal source. Increments occur on a rising edge. After
Timer1 is enabled in Counter mode, the module must
first have a falling edge before the counter begins to
increment.

FIGURE 6-1: TIMER1 INCREMENTING EDGE

T1CKI
(Initially high)

First falling edge

of the T1ON enabled

T1CKI
(Initially low)
First falling edge
of the T1ON enabled

Note: Arrows indicate counter increments.

FIGURE 6-2: TIMER1 BLOCK DIAGRAM

Set flag bit
TMR1IF on
Overflow Synchronized
TMR1 0
clock input
TMR1H TMR1L
1
TMR1ON
on/off T1SYNC
T1OSC
RB6/T1OSO/T1CKI/P1C 1
Synchronize
Prescaler
T1OSCEN Fosc/4 1, 2, 4, 8 det
Enable Internal 0
RB7/T1OSI/P1D Oscillator(1) Clock 2 SLEEP input
T1CKPS<1:0>
TMR1CS

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

DS41120B-page 48  2002 Microchip Technology Inc.

 PIC16C717/770/771
6.2 Timer1 Oscillator 6.3 Timer1 Interrupt
A crystal oscillator circuit is built in between pins T1OSI The TMR1 Register pair (TMR1H:TMR1L) increments
(input) and T1OSO (amplifier output). It is enabled by from 0000h to FFFFh and rolls over to 0000h. The
setting control bit T1OSCEN (T1CON<3>). The oscilla- TMR1 Interrupt, if enabled, is generated on overflow
tor is a low power oscillator rated up to 200 kHz. It will which is latched in interrupt flag bit TMR1IF (PIR1<0>).
continue to run during SLEEP. It is primarily intended This interrupt can be enabled/disabled by setting/clear-
for a 32 kHz crystal. Table 6-1 shows the capacitor ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
6.4 Resetting Timer1 using a CCP
The user must provide a software time delay to ensure Trigger Output
proper oscillator start-up. If the ECCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M<3:0> =
TABLE 6-1: CAPACITOR SELECTION FOR 1011), this signal will reset Timer1 and start an A/D
THE TIMER1 OSCILLATOR conversion (if the A/D module is enabled).

Osc Type Freq C1 C2 Note: The special event triggers from the CCP1
module will not set interrupt flag bit
LP 32 kHz 33 pF 33 pF TMR1IF (PIR1<0>).
100 kHz 15 pF 15 pF
Timer1 must be configured for either timer or Synchro-
200 kHz 15 pF 15 pF nized Counter mode to take advantage of this feature.
These values are for design guidance only. If Timer1 is running in Asynchronous Counter mode,
Note 1: Higher capacitance increases the stability this RESET operation may not work.
of oscillator but also increases the start-up In the event that a write to Timer1 coincides with a spe-
time. cial event trigger from ECCP, the write will take prece-
2: Since each resonator/crystal has its own dence.
characteristics, the user should consult the
resonator/crystal manufacturer for appro- In this mode of operation, the CCPR1H:CCPR1L regis-
priate values of external components. ters pair effectively becomes the period register for
Timer1.

TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on: Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS

0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer1 module.

 2002 Microchip Technology Inc. DS41120B-page 49

PIC16C717/770/771
NOTES:

DS41120B-page 50  2002 Microchip Technology Inc.

 PIC16C717/770/771
7.0 TIMER2 MODULE 7.1 Timer2 Operation
The Timer2 module timer has the following features: Timer2 can be used as the PWM time-base for PWM
mode of the ECCP module.
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2) The TMR2 register is readable and writable, and is
cleared on any device RESET.
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16) The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
• Software programmable postscaler (1:1 to 1:16)
(T2CON<1:0>).
• Interrupt on TMR2 match of PR2
The match output of TMR2 goes through a 4-bit
• SSP module optional use of TMR2 output to gen-
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
erate clock shift
to generate a TMR2 interrupt (latched in flag bit
Timer2 has a control register, shown in Register 7-1. TMR2IF, (PIR1<1>)).
Timer2 can be shut off by clearing control bit TMR2ON
The prescaler and postscaler counters are cleared
(T2CON<2>) to minimize power consumption.
when any of the following occurs:
Figure 7-1 is a simplified block diagram of the Timer2
• a write to the TMR2 register
module.
• a write to the T2CON register
Additional information on timer modules is available in
• any device RESET (Power-on Reset, MCLR
the PICmicro™ Mid-Range MCU Family Reference
Reset, Watchdog Timer Reset, or Brown-out
Manual, (DS33023).
Reset)
TMR2 is not cleared when T2CON is written.

REGISTER 7-1: TIMER2 CONTROL REGISTER (T2CON1: 12h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 51

PIC16C717/770/771
7.2 Timer2 Interrupt FIGURE 7-1: Timer2 Block Diagram
The Timer2 module has an 8-bit period register PR2. Sets flag
TMR2
bit TMR2IF
Timer2 increments from 00h until it matches PR2 and output (1)
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is RESET
TMR2 reg
Prescaler
Fosc/4
initialized to FFh upon RESET. 1:1, 1:4, 1:16
Postscaler 2
Comparator
7.3 Output of TMR2 1:1 to 1:16 EQ

The output of TMR2 (before the postscaler) is fed to the 4 PR2 reg
Synchronous Serial Port module which optionally uses
it to generate shift clock.
Note: TMR2 register output can be software
selected by the SSP Module as a baud
clock.

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on: Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS

0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

11h TMR2 Timer2 register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer2 module.

DS41120B-page 52  2002 Microchip Technology Inc.

 PIC16C717/770/771
8.0 ENHANCED CAPTURE/ Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
COMPARE/PWM (ECCP)
CCPR1H (high byte). The CCP1CON and P1DEL reg-
MODULES isters control the operation of ECCP. All are readable
The ECCP (Enhanced Capture/Compare/PWM) and writable.
module contains a 16-bit register which can operate as
a 16-bit capture register, as a 16-bit compare register
or as a PWM master/slave Duty Cycle register.
Table 8-1 shows the timer resources of the ECCP mod-
ule modes.

REGISTER 8-1: CCP1 CONTROL REGISTER (CCP1CON: 17h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0

bit 7-6 PWM1M<1:0>: PWM Output Configuration

CCP1M<3:2> = 00, 01, 10
xx = P1A assigned as Capture input, Compare output. P1B, P1C, P1D assigned as Port pins.
CCP1M<3:2> = 11
00 = Single output. P1A modulated. P1B, P1C, P1D assigned as Port pins.
01 = Full-bridge output forward. P1D modulated. P1A active. P1B, P1C inactive.
10 = Half-bridge output. P1A, P1B modulated with deadband control. P1C, P1D assigned as
Port pins.
11 = Full-bridge output reverse. P1B modulated. P1C active. P1A, P1D inactive.
bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRnL.
bit 3-0 CCP1M<3:0>: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; ECCP resets TMR1, and starts
an A/D conversion, if the A/D module is enabled.)
1100 = PWM mode. P1A, P1C active high. P1B, P1D active high.
1101 = PWM mode. P1A, P1C active high. P1B, P1D active low.
1110 = PWM mode. P1A, P1C active low. P1B, P1D active high.
1111 = PWM mode. P1A, P1C active low. P1B, P1D active low.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 53

PIC16C717/770/771
TABLE 8-1: ECCP MODE - TIMER EXAMPLE 8-1: Changing Between
RESOURCE Capture Prescalers
CLRF CCP1CON ; Turn ECCP module off
ECCP Mode Timer Resource MOVLW NEW_CAPT_PS ; Load WREG with the
Capture Timer1 ; new prescaler mode
; value and ECCP ON
Compare Timer1
MOVWF CCP1CON ; Load CCP1CON with
PWM Timer2
; this value

8.1 Capture Mode

FIGURE 8-1: CAPTURE MODE
In Capture mode, CCPR1H:CCPR1L captures the 16- OPERATION BLOCK
bit value of the TMR1 register when an event occurs on
DIAGRAM
pin CCP1. An event is defined as:
Set flag bit CCP1IF
• every falling edge (PIR1<2>)
Prescaler
• every rising edge ³ 1, 4, 16
• every 4th rising edge RB3/CCP1/ CCPR1H CCPR1L
P1A Pin
• every 16th rising edge
and Capture
An event is selected by control bits CCP1M<3:0> edge detect Enable
(CCP1CON<3:0>). When a capture is made, the inter-
TMR1H TMR1L
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
CCP1CON<3:0>
be cleared in software. If another capture occurs before Q’s
the value in register CCPR1 is read, the old captured
value will be lost.
8.2 Compare Mode
8.1.1 CCP1 PIN CONFIGURATION
In Compare mode, the 16-bit CCPR1 register value is
In Capture mode, the CCP1 pin should be configured constantly compared against the TMR1 register pair
as an input by setting the TRISB<3> bit. value. When a match occurs, the CCP1 pin is:
Note: If the RB3/CCP1/P1A pin is configured as • driven High
an output, a write to the port can cause a • driven Low
capture condition. • toggle output (High to Low or Low to High)
• remains Unchanged
8.1.2 TIMER1 MODE SELECTION
The action on the pin is based on the value of control
Timer1 must be running in Timer mode or Synchro- bits CCP1M<3:0>. At the same time, interrupt flag bit
nized Counter mode. In Asynchronous Counter mode, CCP1IF is set.
the capture operation may not work.
Changing the ECCP mode select bits to the clear out-
8.1.3 SOFTWARE INTERRUPT put on Match mode (CCP1M<3.0> = “1000”) presets
the CCP1 output latch to the logic 1 level. Changing the
When the Capture mode is changed, a false capture ECCP mode select bits to the clear output on Match
interrupt may be generated. The user should keep bit mode (CCP1M<3:0> = “1001”) presets the CCP1 out-
CCP1IE (PIE1<2>) clear to avoid false interrupts and put latch to the logic 0 level.
should clear the flag bit CCP1IF following any such
change in Operating mode. 8.2.1 CCP1 PIN CONFIGURATION

8.1.4 ECCP PRESCALER The user must configure the CCP1 pin as an output by
clearing the appropriate TRISB bit.
There are three prescaler settings, specified by bits
CCP1M<3:0>. Whenever the ECCP module is turned Note: Clearing the CCP1CON register will force
off or the ECCP module is not in Capture mode, the the CCP1 compare output latch to the
prescaler counter is cleared. This means that any default low level. This is not the port data
RESET will clear the prescaler counter. latch.

Switching from one capture prescaler to another may 8.2.2 TIMER1 MODE SELECTION
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from Timer1 must be running in Timer mode or Synchro-
a non-zero prescaler. Example 8-1 shows the recom- nized Counter mode if the ECCP module is using the
mended method for switching between capture pres- compare feature. In Asynchronous Counter mode, the
calers. This example also clears the prescaler counter compare operation may not work.
and will not generate the “false” interrupt.

DS41120B-page 54  2002 Microchip Technology Inc.

 PIC16C717/770/771
8.2.3 SOFTWARE INTERRUPT MODE FIGURE 8-2: COMPARE MODE
OPERATION BLOCK
When generate software interrupt is chosen, the CCP1
pin is not affected. Only an ECCP interrupt is generated DIAGRAM
(if enabled).
Special event trigger will:
8.2.4 SPECIAL EVENT TRIGGER RESET Timer1, but not set interrupt flag bit
TMR1IF (PIR1<0>).
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
Special Event Trigger
The special event trigger output of ECCP resets the
TMR1 register pair. This allows the CCPR1 register to Set flag bit CCP1IF
(PIR1<2>)
effectively be a 16-bit programmable period register for
CCPR1H CCPR1L
Timer1.
Q S Output
The special event trigger output of ECCP module will Comparator
RB3/CCP1/ Logic match
also start an A/D conversion if the A/D module is R
P1A Pin
enabled. TRISB<3> TMR1H TMR1L
Output Enable CCP1CON<3:0>
Note: The special event trigger will not set the Mode Select
interrupt flag bit TMR1IF (PIR1<0>).

TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISB PORTB Data Direction Register 1111 1111 1111 1111
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
T1CON — — T1CKPS T1CKP T1OSCEN T1SYNC TMR1CS TMR1O --00 0000 --uu uuuu
1 S0 N
CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.

 2002 Microchip Technology Inc. DS41120B-page 55

PIC16C717/770/771
8.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the ECCP
module produces up to a 10-bit resolution PWM output.
Figure 8-3 shows the simplified PWM block diagram.

FIGURE 8-3: SIMPLIFIED PWM BLOCK DIAGRAM

CCP1CON<5:4> PWM1M1<1:0> CCP1M<3:0>

Duty cycle registers
2 4
CCPR1L

CCP1/P1A RB3/CCP1/P1A

TRISB<3>

CCPR1H (Slave)
P1B RB5/SDO/P1B

OUTPUT TRISB<5>
Comparator R Q
CONTROLLER
RB6/T1OSO/T1CKI/
P1C
P1C
TMR2 (Note 1)
S TRISB<6>

P1D RB7/T1OSI/P1D
Comparator
Clear Timer, TRISB<7>
CCP1 pin and
latch D.C.
PR2 P1DEL

Note: 8-bit timer TMR2 is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.

8.3.1 PWM PERIOD

The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM PERIOD = [(PR2) + 1] • 4 • TOSC •
(TMR2 PRESCALE VALUE)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H

Note: The Timer2 postscaler (see Section 7.0) is

not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.

DS41120B-page 56  2002 Microchip Technology Inc.

 PIC16C717/770/771
8.3.2 PWM DUTY CYCLE FIGURE 8-4: SINGLE PWM OUTPUT
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up Period
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the CCP1(2)
two LSbs. This 10-bit value is represented by
Duty Cycle
CCPR1L:CCP1CON<5:4>. The following equation is
(1)
used to calculate the PWM duty cycle in time:
(1)
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into Note 1: At this time, the TMR2 register is equal to the PR2 register.
CCPR1H until after a match between PR2 and TMR2 2: Output signal is shown as asserted high.
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
FIGURE 8-5: EXAMPLE OF SINGLE
The CCPR1H register and a 2-bit internal latch are
OUTPUT APPLICATION
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation. PIC16C717/770/771
Using PWM as
When the CCPR1H and 2-bit latch match TMR2 con- a D/A Converter
catenated with an internal 2-bit Q clock or 2 bits of the
R
TMR2 prescaler, the CCP1 pin is cleared. CCP1 Vout
Maximum PWM resolution (bits) for a given PWM fre-
C
quency:

log  ---------------
F OSC
 F PWM
= -----------------------------bits Using PWM to
log ( 2 ) V+
Drive a Power
PIC16C717/770/771 Load
L
O
A
D
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be CCP1
cleared.

8.3.3 PWM OUTPUT CONFIGURATIONS

The PWM1M1 bits in the CCP1CON register allows
one of the following configurations: In the Half-Bridge Output mode, two pins are used as
• Single output outputs. The RB3/CCP1/P1A pin has the PWM output
signal, while the RB5/SDO/P1B pin has the comple-
• Half-Bridge output
mentary PWM output signal. This mode can be used
• Full-Bridge output, Forward mode for half-bridge applications, as shown on Figure 8-7, or
• Full-Bridge output, Reverse mode for full-bridge applications, where four power switches
In the Single Output mode, the RB3/CCP1/P1A pin is are being modulated with two PWM signal.
used as the PWM output. Since the CCP1 output is Since the P1A and P1B outputs are multiplexed with
multiplexed with the PORTB<3> data latch, the the PORTB<3> and PORTB<5> data latches, the
TRISB<3> bit must be cleared to make the CCP1 pin TRISB<3> and TRISB<5> bits must be cleared to con-
an output. figure P1A and P1B as outputs.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through cur-
rent in bridge power devices. See Section 8.3.5 for
more details of the deadband delay operations.

 2002 Microchip Technology Inc. DS41120B-page 57

PIC16C717/770/771
8.3.4 OUTPUT POLARITY The PWM output polarities must be selected before the
CONFIGURATION PWM outputs are enabled. Charging the polarity con-
figuration while the PWM outputs are active is not rec-
The CCP1M<1:0> bits in the CCP1CON register allow ommended, since it may result in unpredictable
user to choose the logic conventions (asserted high/ operation.
low) for each of the outputs. See Register 8-1 for fur-
ther details.

FIGURE 8-6: HALF-BRIDGE PWM OUTPUT

Period Period

Duty Cycle

P1A(2)
td

td
P1B(2)

(1) (1)
(1)

td = Deadband Delay

Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signals are shown as asserted high.

DS41120B-page 58  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 8-7: EXAMPLE OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+

PIC16C717/770/771
FET
DRIVER
+
P1A V
-

+ -
LOAD
FET
DRIVER
+
P1B V
-

V-

V+

PIC16C717/770/771 FET FET

DRIVER DRIVER
P1A

+ -
LOAD
FET FET
DRIVER DRIVER
P1B

V-

 2002 Microchip Technology Inc. DS41120B-page 59

PIC16C717/770/771
In Full-Bridge Output mode, four pins are used as out- P1A, P1B, P1C and P1D outputs are multiplexed with
puts; however, only two outputs are active at a time. In PORTB<3> and PORTB<5:7> data latches. TRISB<3>
the Forward mode, RB3/CCP1/P1A pin is continuously and TRISB<5:7> bits must be cleared to make the P1A,
active, and RB7/T1OSI/P1D pin is modulated. In the P1B, P1C, and P1D pins output.
Reverse mode, RB6/T1OSO/T1CKI/P1C pin is contin-
uously active, and RB5/SDO/P1B pin is modulated.

FIGURE 8-8: FULL-BRIDGE PWM OUTPUT

FORWARD MODE
Period

P1A(2) 1
0
Duty Cycle

1
P1B(2) 0

1
P1C(2) 0

1
P1D(2) 0

(1) (1)

REVERSE MODE

Period
Duty Cycle
(2) 1
P1A 0

1
P1B(2) 0

1
P1C(2) 0

P1D(2) 1
0
(1)
(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.

DS41120B-page 60  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 8-9: EXAMPLE OF FULL-BRIDGE APPLICATION

V+

PIC16C717/770/771
FET FET
DRIVER DRIVER
P1D

+ -
LOAD
P1C
FET FET
DRIVER DRIVER

P1A

V-
P1B

 2002 Microchip Technology Inc. DS41120B-page 61

PIC16C717/770/771
8.3.5 PROGRAMMABLE DEADBAND shorting the bridge supply. To avoid this potentially
DELAY destructive shoot-through current from flowing during
switching, turning on the power switch is normally
In half-bridge or full-bridge applications, driven by half- delayed to allow the other switch to completely turn off.
bridge outputs (see Figure 8-7), the power switches
normally require longer time to turn off than to turn on. In the Half-Bridge Output mode, a digitally program-
If both the upper and lower power switches are mable deadband delay is available to avoid shoot-
switched at the same time (one turned on, and the through current from destroying the bridge power
other turned off), both switches will be on for a short switches. The delay occurs at the signal transition from
period of time, until one switch completely turns off. the non-active state to the active state. See Figure 8-6
During this time, a very high current, called shoot- for illustration. The P1DEL register sets the amount of
through current, will flow through both power switches, delay.

REGISTER 8-2: PWM DELAY REGISTER (P1DEL: 97H)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1DEL7 P1DEL6 P1DEL5 P1DEL4 P1DEL3 P1DEL2 P1DEL1 P1DEL0
bit 7 bit 0

bit 7-0 P1DEL<7:0>: PWM Delay Count for Half-Bridge Output Mode: Number of FOSC/4 (Tosc•4)
cycles between the P1A transition and the P1B transition.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

8.3.6 DIRECTION CHANGE IN FULL- modulated outputs, P1A and P1C signals, will transition
BRIDGE OUTPUT MODE to the new direction TOSC, 4•TOSC or 16•TOSC (for
Timer2 prescale T2CKRS<1:0> = 00, 01 and 1x
In the Full-Bridge Output mode, the PWM1M1 bit in the respectively) earlier, before the end of the period. Dur-
CCP1CON register allows user to control the Forward/ ing this transition cycle, the modulated outputs, P1B
Reverse direction. When the application firmware and P1D, will go to the inactive state. See Figure 8-10
changes this direction control bit, the ECCP module will for illustration.
assume the new direction on the next PWM cycle. The
current PWM cycle still continues, however, the non-

FIGURE 8-10: PWM DIRECTION CHANGE

(1)
PERIOD PERIOD
SIGNAL
DC
P1A (Active High)

P1B (Active High)

P1C (Active High)

P1D (Active High) (2)

Note 1: The Direction bit in the ECCP Control Register (CCP1CON<PWM1M1>) is written anytime during the PWM cycle.
2: The P1A and P1C signals switch TOSC, 4*Tosc or 16*TOSC, depending on the Timer2 prescaler value, earlier when
changing direction. The modulated P1B and P1D signals are inactive at this time.

DS41120B-page 62  2002 Microchip Technology Inc.

 PIC16C717/770/771
Note that in the Full-Bridge Output mode, the ECCP example, since the turn off time of the power devices is
module does not provide any deadband delay. In gen- longer than the turn on time, a shoot-through current
eral, since only one output is modulated at a time, flows through the power devices, QB and QD, for the
deadband delay is not required. However, there is a sit- duration of t= toff-ton. The same phenomenon will occur
uation where a deadband delay might be required. This to power devices, QC and QB, for PWM direction
situation occurs when all of the following conditions are change from reverse to forward.
true: If changing PWM direction at high duty cycle is required
1. The direction of the PWM output changes when for the user’s application, one of the following require-
the duty cycle of the output is at or near 100%. ments must be met:
2. The turn off time of the power switch, including 1. Avoid changing PWM output direction at or near
the power device and driver circuit, is greater 100% duty cycle.
than turn on time. 2. Use switch drivers that compensate for the slow
Figure 8-11 shows an example, where the PWM direc- turn off of the power devices. The total turn off
tion changes from forward to reverse at a near 100% time (toff) of the power device and the driver
duty cycle. At time t1, the output P1A and P1D become must be less than the turn on time (ton).
inactive, while output P1C becomes active. In this

FIGURE 8-11: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

FORWARD PERIOD REVERSE PERIOD

P1A 1
0
1
P1B 0 (PWM)

1
P1C 0

P1D 1
0 (PWM)
ton
1
External Switch C 0

toff

1
External Switch D 0

Potential 1 t = toff - ton

Shoot Through 0
Current
t1

Note 1: All signals are shown as active high.

2: ton is the turn on delay of power switch and driver.
3: toff is the turn off delay of power switch and driver.

 2002 Microchip Technology Inc. DS41120B-page 63

PIC16C717/770/771
8.3.7 SYSTEM IMPLEMENTATION 8.3.9 SET UP FOR PWM OPERATION
When the ECCP module is used in the PWM mode, the The following steps should be taken when configuring
application hardware must use the proper external pull- the ECCP module for PWM operation:
up and/or pull-down resistors on the PWM output pins. 1. Configure the PWM module:
When the microcontroller powers up, all of the I/O pins
a) Disable the CCP1/P1A, P1B, P1C and/or
are in the high-impedance state. The external pull-up
P1D outputs by setting the respective
and pull-down resistors must keep the power switch
TRISB bits.
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates b) Set the PWM period by loading the PR2
the PWM output(s). register.
c) Set the PWM duty cycle by loading the
8.3.8 START-UP CONSIDERATIONS CCPR1L register and CCP1CON<5:4>
bits.
Prior to enabling the PWM outputs, the P1A, P1B, P1C
and P1D latches may not be in the proper states. d) Configure the ECCP module for the desired
Enabling the TRISB bits for output at the same time PWM operation by loading the CCP1CON
with the CCP module may cause damage to the power register. With the CCP1M<3:0> bits select
switch devices. The CCP1 module must be enabled in the active high/low levels for each PWM
the proper Output mode with the TRISB bits enabled as output. With the PWM1M<1:0> bits select
inputs. Once the CCP1 completes a full PWM cycle, one of the available Output modes: Single,
the P1A, P1B, P1C and P1D output latches are prop- Half-Bridge, Full-Bridge, Forward or Full-
erly initialized. At this time, the TRISB bits can be Bridge Reverse.
enabled for outputs to start driving the power switch e) For Half-Bridge Output mode, set the dead-
devices. The completion of a full PWM cycle is indi- band delay by loading the P1DEL register.
cated by the TMR2IF bit going from a ’0’ to a ’1’. 2. Configure and start TMR2:
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
b) Set the TMR2 prescale value by loading the
T2CKPS<1:0> bits in the T2CON register.
c) Enable Timer2 by setting the TMR2ON bit
in the T2CON register.
3. Enable PWM outputs after a new cycle has
started:
a) Wait until TMR2 overflows (TMR2IF bit
becomes a ’1’). The new PWM cycle begins
here.
b) Enable the CCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISB bits.

TABLE 8-3: REGISTERS ASSOCIATED WITH PWM

Value on Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS

0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 register 0000 0000 0000 0000
92h PR2 Timer2 period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
97h P1DEL PWM1 Delay value 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by ECCP module in PWM mode.

DS41120B-page 64  2002 Microchip Technology Inc.

 PIC16C717/770/771
9.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, etc. The MSSP module can operate in one
of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I 2C™)

 2002 Microchip Technology Inc. Advance Information DS41120B-page 65

PIC16C717/770/771
REGISTER 9-1: SYNC SERIAL PORT STATUS REGISTER (SSPSTAT: 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0

bit 7 SMP: Sample bit

SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for High Speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select (Figure 9-3, Figure 9-5, and Figure 9-6)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0 = STOP bit was not detected last
bit 3 S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0 = START bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit, or NACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
ORing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode
bit 1 UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only)
1 = Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 66 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0

bit 7 WCOL: Write Collision Detect bit

Master Mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting over-
flow. In Master mode, the overflow bit is not set since each new reception (and transmis-
sion) is initiated by writing to the SSPBUF register. (Must be cleared in software).
0 = No overflow
In I2 C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the I/O pins must be properly configured as input or output.
In SPI mode
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port
pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial
port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
In I2 C Slave mode SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (used to ensure data setup time)
In I2 C Master mode
Unused in this mode

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. Advance Information DS41120B-page 67

PIC16C717/770/771
REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h) (CONTINUED)

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / (4 • (SSPADD+1) )
1001 = Reserved
1010 = Reserved
1011 = Firmware controlled Master mode (slave idle)
1100 = Reserved
1101 = Reserved
1110 = 7-bit Slave mode with START and STOP condition interrupts
1111 = 10-bit Slave mode with START and STOP condition interrupts

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 68 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
REGISTER 9-3: SYNC SERIAL PORT CONTROL REGISTER2 (SSPCON2: 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0

bit 7 GCEN: General Call Enable bit (In I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge (NACK)
0 = Acknowledge (ACK)
bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only).
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence IDLE
bit 3 RCEN: Receive Enable bit (In I2C Master mode only).
1 = Enables Receive mode for I2C
0 = Receive IDLE
bit 2 PEN: STOP Condition Enable bit (In I2C Master mode only).
SCK Release Control
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
bit 1 RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by
hardware.
0 = Repeated START condition IDLE
bit 0 SEN: START Condition Enabled bit (In I2C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE

Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

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PIC16C717/770/771
9.1 SPI Mode FIGURE 9-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The SPI mode allows eight bits of data to be synchro-
nously transmitted and received simultaneously. All Internal
Data Bus
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used: Read Write

• Serial Data Out (SDO)

SSPBUF reg
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation: SSPSR reg
SDI bit0 Shift
• Slave Select (SS) Clock

9.1.1 OPERATION SDO

When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
SS Control
control bits (SSPCON<5:0> and SSPSTAT<7:6>). Enable
These control bits allow the following to be specified:
SS Edge
• Master Mode (SCK is the clock output) Select
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK) 2
• Data input sample phase Clock Select
(middle or end of data output time)
SSPM<3:0>
• Clock edge SMP:CKE 4 TMR2 Output
(output data on rising/falling edge of SCK) 2 2
• Clock Rate (Master mode only) Edge
Select Prescaler Tosc
• Slave Select Mode (Slave mode only)
SCK 4, 16, 64
Figure 9-1 shows the block diagram of the MSSP mod-
ule when in SPI mode. Data to TX/RX in SSPSR
Data direction bit

The MSSP consists of a transmit/receive Shift Register

(SSPSR) and a Buffer Register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR, until the received data is ready. Once the eight
bits of data have been received, that byte is moved to
the SSPBUF register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF register completed successfully.

DS41120B-page 70 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
When the application software is expecting to receive 9.1.2 ENABLING SPI I/O
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer To enable the serial port, MSSP Enable bit, SSPEN
full bit, BF (SSPSTAT<0>), indicates when the SSP- (SSPCON<5>) must be set. To reset or reconfigure SPI
BUF has been loaded with the received data (transmis- mode, clear bit SSPEN, re-initialize the SSPCON reg-
sion is complete). When the SSPBUF is read, bit BF is isters, and then set bit SSPEN. This configures the
cleared. This data may be irrelevant if the SPI is only a SDI, SDO, SCK and SS pins as serial port pins. For the
transmitter. Generally the MSSP Interrupt is used to pins to behave as the serial port function, some must
determine when the transmission/reception has com- have their data direction bits (in the TRIS register)
pleted. The SSPBUF must be read and/or written. If the appropriately programmed. That is:
interrupt method is not going to be used, then software • SDI is automatically controlled by the SPI module
polling can be done to ensure that a write collision does • SDO must have TRISB<5> cleared
not occur. Example 9-1 shows the loading of the SSP- • SCK (Master mode) must have TRISB<2>
BUF (SSPSR) for data transmission. cleared
• SCK (Slave mode) must have TRISB<2> set
EXAMPLE 9-1: Loading the SSPBUF
• SS must have TRISB<1> set, and ANSEL<5>
(SSPSR) Register
cleared
BSF STATUS, RP0 ;Specify Bank 1
LOOP BTFSS SSPSTAT, BF ;Has data been Any serial port function that is not desired may be over-
;received ridden by programming the corresponding data direc-
;(xmit complete)? tion (TRIS) register to the opposite value.
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0 9.1.3 TYPICAL CONNECTION
MOVF SSPBUF, W ;Save SSPBUF...
MOVWF RXDATA ;...in user RAM Figure 9-2 shows a typical connection between two
MOVF TXDATA, W ;Get next TXDATA microcontrollers. The master controller (Processor 1)
MOVWF SSPBUF ;New data to xmit initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
The SSPSR is not directly readable or writable, and grammed clock edge, and latched on the opposite
can only be accessed by addressing the SSPBUF reg- edge of the clock. Both processors should be pro-
ister. Additionally, the MSSP STATUS register grammed to same Clock Polarity (SSPCON<4>), then
(SSPSTAT) indicates the various status conditions. both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data

FIGURE 9-2: SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb

SDO SDI

Serial Input Buffer Serial Input Buffer

(SSPBUF) (SSPBUF)

Shift Register SDI SDO Shift Register

(SSPSR) (SSPSR)

MSb LSb MSb LSb

Serial Clock
SCK SCK
PROCESSOR 1 PROCESSOR 2

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PIC16C717/770/771
9.1.4 MASTER MODE Figure 9-3, Figure 9-5 and Figure 9-6, where the MSb
is transmitted first. In Master mode, the SPI clock rate
The master can initiate the data transfer at any time (bit rate) is user programmable to be one of the follow-
because it controls the SCK. The master determines ing:
when the slave (Processor 2, Figure 9-2) is to broad-
cast data by the software protocol. • FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI • FOSC/64 (or 16 • TCY)
module is only going to receive, the SDO output could • Timer2 output/2
be disabled (programmed as an input). The SSPSR This allows a maximum bit clock frequency (at 20 MHz)
register will continue to shift in the signal present on the of 8.25 MHz.
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as Figure 9-3 shows the waveforms for Master mode.
if a normal received byte (interrupts and status bits When CKE = 1, the SDO data is valid before there is a
appropriately set). This could be useful in receiver clock edge on SCK. The change of the input sample is
applications as a “line activity monitor”. shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
The clock polarity is selected by appropriately program- shown.
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in

FIGURE 9-3: SPI MODE WAVEFORM (MASTER MODE)

Write to
SSPBUF

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)
4 Clock
SCK modes
(CKP = 0
CKE = 1)

SCK
(CKP = 1
CKE = 1)

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

(CKE = 0)

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

(CKE = 1)
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit0
bit7

Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF

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 PIC16C717/770/771
9.1.5 SLAVE MODE SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
In Slave mode, the data is transmitted and received as a transmitted byte, and becomes a floating output.
the external clock pulses appear on SCK. When the External pull-up/ pull-down resistors may be desir-
last bit is latched the interrupt flag bit SSPIF (PIR1<3>) able, depending on the application.
is set.
Note 1: When the SPI module is in Slave mode
While in Slave mode, the external clock is supplied by
with SS pin control enabled, (SSP-
the external clock source on the SCK pin. This external
CON<3:0> = 0100) the SPI module will
clock must meet the minimum high and low times as
RESET if the SS pin is set to VDD.
specified in the electrical specifications.
2: If the SPI is used in Slave Mode with
While in SLEEP mode, the slave can transmit/receive
CKE = ’1’, then SS pin control must be
data. When a byte is received, the device will wake-up
enabled.
from SLEEP.
When the SPI module RESETS, the bit counter is
9.1.6 SLAVE SELECT forced to 0. This can be done by either forcing the SS
SYNCHRONIZATION pin to a high level or clearing the SSPEN bit.

The SS pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDO pin can
SPI must be in Slave mode with SS pin control be connected to the SDI pin. When the SPI needs to
enabled (SSPCON<3:0> = 0100). The pin must not operate as a receiver, the SDO pin can be configured
be driven low for the SS pin to function as an input. as an input. This disables transmissions from the SDO.
TRISB<1> must be set. When the SS pin is low, The SDI can always be left as an input (SDI function)
transmission and reception are enabled and the since it cannot create a bus conflict.

FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)

Write to
SSPBUF

SDO bit7 bit6 bit7 bit0

SDI bit0
(SMP = 0) bit7 bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF

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PIC16C717/770/771
FIGURE 9-5: SPI SLAVE MODE WAVEFORM (CKE = 0)

SS
optional
SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF

FIGURE 9-6: SPI SLAVE MODE WAVEFORM (CKE = 1)

SS
not optional
SCK
(CKP = 0
CKE = 1)

SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF

SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SDI
(SMP = 0) bit7 bit0

Input
Sample
(SMP = 0)

SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF

DS41120B-page 74 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
9.1.7 SLEEP OPERATION 9.1.8 EFFECTS OF A RESET
In Master mode, all module clocks are halted and the A RESET disables the MSSP module and terminates
transmission/reception will remain in that state until the the current transfer.
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the SSPIF
interrupt flag bit will be set and if enabled will wake the
device from SLEEP.

TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT

0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
9Dh ANSEL --11 1111 --11 1111
86h TRISB 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the MSSP in SPI mode.

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PIC16C717/770/771
9.2 MSSP I 2C Operation transferred from the SSPSR register to the SSPBUF
register and flag bit SSPIF is set. If another complete
The MSSP module in I 2Cmode fully implements all byte is received before the SSPBUF register is read a
master and slave functions (including general call sup- receiver overflow occurs, in which case, the SSPOV bit
port) and provides interrupts on START and STOP bits (SSPCON<6>) is set and the byte in the SSPSR is lost.
in hardware to determine when the bus is free (multi-
master function). The MSSP module implements the FIGURE 9-7: I2C SLAVE MODE BLOCK
Standard mode specifications, as well as 7-bit and 10- DIAGRAM
bit addressing. Internal
Data Bus
Two pins are used to transfer data. They are the SCL
pin (clock) and the SDA pin (data). The MSSP module Read Write
functions are enabled by setting SSP Enable bit
RB2/SCK/
SSPEN (SSPCON<5>). The SCL and SDA pins are SSPBUF reg
SCL
"glitch" filtered when operating as inputs. This filter
functions in both the 100 kHz and 400 kHz modes. Shift
When these pins operate as outputs in the 100 kHz Clock
mode, there is a slew rate control of the pin that is inde- SSPSR reg
pendent of device frequency. RB4/SDI/ MSb LSb
Before selecting any I2C mode, the SCL and SDA pins SDA
must be programmed as inputs by setting the appropri- Match detect Addr Match
ate TRIS bits. This allows the MSSP module to configure
and drive the I/O pins as required by the I2C protocol.
The MSSP module has six registers for I2C operation. SSPADD reg
They are listed below.
START and Set, RESET
• SSP Control Register (SSPCON) STOP bit detect S, P bits
• SSP Control Register2 (SSPCON2) (SSPSTAT reg)

• SSP STATUS Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF) 9.2.1 UPWARD COMPATIBILITY WITH
• SSP Shift Register (SSPSR) - Not directly accessible SSP MODULE
• SSP Address Register (SSPADD) The MSSP module includes three SSP modes of oper-
The SSPCON register allows for control of the I 2C ation to maintain upward compatibility with the SSP
operation. Four mode selection bits (SSPCON<3:0>) module. These modes are:
configure the MSSP as any one of the following I 2C • Firmware controlled Master mode (slave idle)
modes: • 7-bit Slave mode with START and STOP
• I 2C Slave mode (7-bit address) condition interrupts.
• I 2C Slave mode (10-bit address) • 10-bit Slave mode with START and STOP
• I 2C Master mode condition interrupts.
SCL Freq = FOSC / [4 • (SSPADD + 1)] The firmware controlled Master mode enables the
• I 2C Slave mode with START and STOP interrupts START and STOP condition interrupts but all other I2C
(7-bit address) functions are generated through firmware including:
• I 2C Slave mode with START and STOP interrupts • Generating the START and STOP conditions
(10-bit address) • Generating the SCL clock
• Firmware Controlled Master mode • Supplying the SDA bits in the proper time and
The SSPSTAT register gives the status of the data phase relationship to the SCL signal.
transfer. This information includes detection of a In firmware controlled Master mode, the SCL and SDA
START (S) or STOP (P) bit. It specifies whether the lines are manipulated by clearing and setting the corre-
received byte was data or address, if the next byte is sponding TRIS bits. The output level is always low irre-
the completion of 10-bit address, and if this will be a spective of the value(s) in the PORT register. A ‘1’ is
read or write data transfer. output by setting the TRIS bit and a ‘0’ is output by
SSPBUF is the register to which the transfer data is clearing the TRIS bit
written, and from which the transfer data is read. The The 7-bit and 10-bit Slave modes with START and
SSPSR register shifts the data in or out of the device. STOP condition interrupts operate identically to the
In receive operations, the SSPBUF and SSPSR create MSSP Slave modes except that START and STOP
a doubled, buffered receiver. This allows reception of conditions generate SSPIF interrupts.
the next byte to begin before reading the last byte of
received data. When the complete byte is received, it is

DS41120B-page 76 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
For more information about these SSP modes see Sec- 9.2.2.2 10-BIT ADDRESSING
tion 15 of the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023). In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
9.2.2 SLAVE MODE criteria for address match are more complex.

When an address is matched or the data transfer after Two address bytes need to be received by the slave.
an address match is received, the hardware automati- The five Most Significant bits (MSbs) of the first
cally will generate the Acknowledge (ACK) pulse. address byte specify that this is a 10-bit address. The
Then, it loads the SSPBUF register with the received LSb of the first received address byte is the R/W bit,
value currently in the SSPSR register. which must be zero, specifying a write so the slave
device will receive the second address byte. For a 10-
Any combination of the following conditions will cause bit address, the first byte equals ‘11110 A9 A8 0’,
the MSSP module to generate a NACK pulse in lieu of where A9 and A8 are the two MSbs of the address. The
the ACK pulse: sequence of events for a 10-bit address is as follows,
a) The buffer full bit BF (SSPSTAT<0>) is set with steps 7 through 9 applicable only to the slave-
before the transfer is received. transmitter:
b) The overflow bit SSPOV (SSPCON<6>) is set 1. Receive first (high) byte of Address (bits SSPIF,
before the transfer is received. BF, and bit UA (SSPSTAT<1>) are set).
If the BF bit is set, the SSPSR register value is not 2. Update the SSPADD register with second (low)
loaded into the SSPBUF. However, both the SSPIF and byte of Address (clears bit UA and releases the
SSPOV bits are set. Table 9-2 shows what happens SCL line).
when a data transfer byte is received, given the status 3. Read the SSPBUF register (clears bit BF) and
of bits BF and SSPOV. The shaded cells show the con- clear flag bit SSPIF.
dition where user software did not properly clear the 4. Receive second (low) byte of Address (bits
overflow condition. The BF flag bit is cleared by reading SSPIF, BF, and UA are set).
the SSPBUF register. The SSPOV flag bit is cleared
5. Update the SSPADD register with the first (high)
through software.
byte of Address. This will clear bit UA and
The SCL clock input must have a minimum high and release the SCL line.
low time for proper operation. The high and low times 6. Read the SSPBUF register (clears bit BF) and
of the I2C specification as well as the requirements of clear flag bit SSPIF.
the MSSP module are shown in timing parameters
7. Receive Repeated START condition.
#100 and #101 of the Electrical Specifications.
8. Receive first (high) byte of Address with R/W bit
9.2.2.1 7-BIT ADDRESSING set to 1 (bits SSPIF and BF are set). This also
puts the MSSP module in the Slave-transmit
Once the MSSP module has been enabled mode.
(SSPEN=1), the slave module waits for a START con- 9. Read the SSPBUF register (clears bit BF) and
dition to occur. Following the START condition, eight clear flag bit SSPIF.
bits are shifted into the SSPSR register. All incoming
bits are sampled on the rising edge of the clock (SCL) Note: Following the Repeated START condition
line. The received address (register SSPSR<7:1>) is (step 7) in 10-bit mode, the user only
compared to the stored address (register needs to match the first 7-bit address. The
SSPADD<7:1>). SSPSR<0> is the R/W bit and is not user does not update the SSPADD for the
considered in the comparison. Comparison is made on second half of the address.
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
a) The SSPSR register value is transferred to the
SSPBUF register on the falling edge of the
eighth SCL pulse.
b) The buffer full bit; BF is set on the falling edge of
the eighth SCL pulse.
c) An ACK pulse is generated during the ninth
clock cycle.
d) SSP interrupt flag bit; SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.

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PIC16C717/770/771
9.2.2.3 SLAVE RECEPTION An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
When the R/W bit of the address byte is clear ware. The SSPSTAT register is used to determine the
(SSPSR<0> = 0) and an address match occurs, the R/ status of the received byte.
W bit of the SSPSTAT register is cleared. The received
address is loaded into the SSPBUF register on the fall- Note: The SSPBUF will be loaded if the SSPOV
ing edge of the eighth SCL pulse. bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
When the address byte overflow condition exists, then
the user did not clear the state of the
no Acknowledge (ACK) pulse is given. An overflow
SSPOV bit before the next receive
condition is defined as either bit BF (SSPSTAT<0>) or
occurred, the ACK is not sent and the SSP-
bit SSPOV (SSPCON<6>) is set.
BUF is updated.

TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received Set bit SSPIF
Generate ACK (SSP Interrupt occurs
BF SSPOV SSPSR → SSPBUF Pulse if enabled)
0 0 Yes Yes Yes
1 0 No No Yes
1 1 No No Yes
0 1 Yes No Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

FIGURE 9-8: I 2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Receiving Address R/W=0 ACK Receiving Data ACK Receiving Data NACK
SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

SSPIF Bus Master

terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
NACK is sent because of overflow

DS41120B-page 78 Advance Information  2002 Microchip Technology Inc.

 FIGURE 9-9:

Bus Master
Clock is held low until terminates
update of SSPADD has transfer

 2002 Microchip Technology Inc.

taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte
R/W = 0

SDA ACK ACK

1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPIF
(PIR1<3>)
Cleared in software Cleared in software

BF (SSPSTAT<0>)
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF
contents of SSPSR to clear BF flag to clear BF flag Read of SSPBUF
clears BF flag

Advance Information
UA (SSPSTAT<1>)

UA is set indicating that Cleared by hardware when Cleared by hardware when

the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high
updated byte of address. byte of address.
UA is set indicating that
I2C SLAVE MODE FOR RECEPTION (10-BIT ADDRESS)

SSPADD needs to be
updated

DS41120B-page 79
PIC16C717/770/771
PIC16C717/770/771
9.2.2.4 SLAVE TRANSMISSION sending a NACK. If the SDA line is high (NACK), then
the data transfer is complete. When the NACK is
When the R/W bit of the incoming address byte is set latched by the slave, the slave logic is RESET which
and an address match occurs, the R/W bit of the SSP- also resets the R/W bit to ’0’. The slave module then
STAT register is set. The received address is loaded monitors for another occurrence of the START bit. The
into the SSPBUF register on the falling edge of the slave firmware knows not to load another byte into the
eighth SCL pulse. The ACK pulse will be sent on the SSPBUF register by sensing that the buffer is empty
ninth bit, and the SCL pin is held low. The slave module (BF = 0) and the R/W bit has gone low. If the SDA line
automatically stretches the clock by holding the SCL is low (ACK), the R/W bit remains high indicating that
line low so that the master will be unable to assert the next transmit data must be loaded into the SSPBUF
another clock pulse until the slave is finished preparing register.
the transmit data. The transmit data must be loaded
into the SSPBUF register, which also loads the SSPSR An MSSP interrupt (SSPIF flag) is generated for each
register. The CKP bit (SSPCON<4>) must then be set data transfer byte on the falling edge of the ninth clock
to release the SCL pin from the forced low condition. pulse. The SSPIF flag bit must be cleared in software.
The eight data bits are shifted out on the falling edges The SSPSTAT register is used to determine the status
of the SCL input. This ensures that the SDA signal is of the byte transfer.
valid during the SCL high time (Figure 9-10). For more information about the I2C Slave mode, refer
The ACK or NACK signal from the master-receiver is to Application Note AN734, “Using the PICmicro® SSP
latched on the rising edge of the ninth SCL input pulse. for Slave I2C™ Communication”.
The master-receiver terminates slave transmission by

FIGURE 9-10: I 2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

R/W ← 0
Receiving Address R/W = 1 Transmitting Data NACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled until SSPBUF Master terminates transmission
is written by responding with NACK
SSPIF

BF (SSPSTAT<0>)
cleared in software From SSP interrupt
SSPBUF is written in software service routine

CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)

DS41120B-page 80 Advance Information  2002 Microchip Technology Inc.

 FIGURE 9-11:

Master sends NACK

Transmit is complete

 2002 Microchip Technology Inc.

Clock is held low until
update of SSPADD has
taken place Restart condition

R/W←0
Receive First Byte of Address R/W=0 Receive Second Byte of Address Receive First Byte of Address R/W=1 Transmitting Data Byte NACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
CKP has to be set for clock to be released

SSPIF
(PIR1<3>)
Cleared in software Cleared in software Cleared in software Master releases
bus with STOP
condition
BF (SSPSTAT<0>)
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF
contents of SSPSR to clear BF flag Write of SSPBUF
to clear BF flag initiates transmit

Advance Information
UA (SSPSTAT<1>)

UA is set indicating that Cleared by hardware when Cleared by hardware when

the SSPADD needs to be SSPADD is updated. SSPADD is updated.
updated
UA is set indicating that
SSPADD needs to be
updated
I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (10-BIT ADDRESS)

DS41120B-page 81
PIC16C717/770/771
PIC16C717/770/771
9.2.3 GENERAL CALL ADDRESS into the SSPSR, and the address is compared against
SUPPORT SSPADD. It is also compared to the general call
address, fixed in hardware.
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter- If the general call address matches, the SSPSR is
mines which device will be the slave addressed by the transferred to the SSPBUF, the BF flag is set (eighth
master. The exception is the general call address, bit), and on the falling edge of the ninth bit (ACK bit),
which can address all devices. When this address is the SSPIF flag is set.
used, all devices should, in theory, respond with an When the interrupt is serviced, the source for the inter-
Acknowledge. rupt can be checked by reading the contents of the
The general call address is one of eight addresses SSPBUF to determine if the address was device spe-
reserved for specific purposes by the I2C protocol. It cific or a general call address.
consists of all 0’s with R/W = 0 If the general call address is sampled with GCEN set
The general call address is recognized when the Gen- and the slave configured in 10-bit Address mode, the
eral Call Enable bit (GCEN) is set (SSPCON2<7> is second half of the address is not necessary. The UA bit
set). Following a START bit detect, eight bits are shifted will not be set and the slave will begin receiving data
after the Acknowledge (Figure 9-12).

FIGURE 9-12: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7- OR 10-BIT MODE)

Address is compared to General Call Address

after ACK, set interrupt flag

Receiving data
R/W = 0
SDA General Call Address ACK D7 ACK
D6 D5 D4 D3 D2 D1 D0

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S

SSPIF

BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV ’0’
(SSPCON<6>)

GCEN ’1’
(SSPCON2<7>)

DS41120B-page 82 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
9.2.4 SLEEP OPERATION 9.2.6 MASTER MODE
While in SLEEP mode, the I2C slave module can Master mode operation supports interrupt generation
receive addresses or data. When an address match or on the detection of the START and STOP conditions.
complete byte transfer occurs, it wakes the processor The STOP (P) and START (S) bits are cleared from a
from SLEEP (if the SSP interrupt bit is enabled). RESET or when the MSSP module is disabled. Control
of the I 2C bus may be taken when the P bit is set or the
9.2.5 EFFECTS OF A RESET bus is idle with both the S and P bits clear.
A RESET disables the MSSP module and terminates In Master mode, the SCL and SDA lines are manipu-
the current transfer. lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit
(SSPIF) to be set (SSP Interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START

FIGURE 9-13: MSSP BLOCK DIAGRAM (I2C MASTER MODE)

Internal SSPM<3:0>,
Data Bus SSPADD<6:0>
Read Write

SSPBUF Baud
Rate
Generator
SDA Shift

clock arbitrate/WCOL detect

SDA in Clock
SSPSR

(hold off clock source)

MSb LSb
Receive Enable

START bit, STOP bit,

clock cntl

Acknowledge
Generate
SCL

START bit detect,

STOP bit detect
SCL in Write collision detect Set/RESET, S, P, WCOL (SSPSTAT)
Clock Arbitration Set SSPIF, BCLIF
Bus Collision State counter for RESET ACKSTAT, PEN (SSPCON2)
end of XMIT/RCV

 2002 Microchip Technology Inc. Advance Information DS41120B-page 83

PIC16C717/770/771
9.2.7 MULTI-MASTER OPERATION 9.2.9 BAUD RATE GENERATOR
In Multi-Master mode, the interrupt generation on the The baud rate generator used for SPI mode operation
detection of the START and STOP conditions allows is used in the I2C Master mode to set the SCL clock fre-
the determination of when the bus is free. The STOP quency. Standard SCL clock frequencies are 100 kHz,
(P) and START (S) bits are cleared from a RESET or 400 kHz, and 1 MHz. One of these frequencies can be
when the MSSP module is disabled. Control of the I 2C achieved by setting the SSPADD register to the appro-
bus may be taken when bit P (SSPSTAT<4>) is set, or priate number for the selected Fosc frequency. One
the bus is idle with both the S and P bits clear. When half of the SCL period is equal to
the bus is busy, enabling the SSP Interrupt will gener- [(SSPADD+1) •2]/Fosc.
ate the interrupt when the STOP condition occurs. The baud rate generator reload value is contained in
In multi-master operation, the SDA line must be moni- the lower seven bits of the SSPADD register (Figure 9-
tored for arbitration to see if the signal level is the 14). When the BRG is loaded with this value, the BRG
expected output level. This check is performed in hard- counts down to 0 and stops until another reload occurs.
ware, with the result placed in the BCLIF bit. The BRG count is decremented twice per instruction
The states where arbitration can be lost are: cycle (TCY) on the Q2 and Q4 clock.

• Address Transfer In I2C Master mode, the BRG is reloaded automatically

provided that the SCL line is sampled high. For exam-
• Data Transfer
ple, if Clock Arbitration is taking place, the BRG reload
• A START Condition will be suppressed until the SCL line is released by the
• A Repeated START Condition slave allowing the pin to float high (Figure 9-15).
• An Acknowledge Condition
Refer to Application Note AN578, "Use of the SSP FIGURE 9-14: BAUD RATE GENERATOR
Module in the I2C™ Multi-Master Environment." BLOCK DIAGRAM
SSPM<3:0> SSPADD<6:0>
9.2.8 I2C MASTER OPERATION
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the SSPM<3:0> Reload Reload
SSPEN bit. Once Master mode is enabled, the user
SCL Control
has six options.
1. Assert a START condition on SDA and SCL. Fosc/2
BRG CLKOUT BRG Down Counter
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
The master device generates all serial clock pulses and
the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START con-
dition. Since the Repeated START condition is also the
beginning of the next serial transfer, the I2C bus will not
be released.

Note: The MSSP Module, when configured in I2C

Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to, and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.

DS41120B-page 84 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 9-15: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA DX DX-1

SCL de-asserted but slave holds SCL allowed to transition high

SCL low (clock arbitration)
SCL

BRG decrements
(on Q2 and Q4 cycles)
BRG
03h 02h 01h 00h (hold off) 03h 02h
value

SCL is sampled high, reload takes

place, and BRG starts its count.
BRG
reload

9.2.10 I2C MASTER MODE START

CONDITION TIMING Note: If at the beginning of START condition, the
SDA and SCL pins are already sampled
To initiate a START condition, the user sets the START
low, or if during the START condition, the
condition enable bit, SEN (SSPCON2<0>). If the SDA
SCL line is sampled low before the SDA
and SCL pins are sampled high, indicating that the bus
line is driven low, a bus collision occurs.
is available, the baud rate generator is loaded with the
Thus, the Bus Collision Interrupt Flag
contents of SSPADD<6:0> and starts its count. If SCL
(BCLIF) is set, the START condition is
and SDA are both sampled high when the baud rate
aborted, and the I2C module is RESET into
generator times out (TBRG) indicating the bus is still
its IDLE state.
available, the SDA pin is driven low. The SDA transition
from high to low while SCL is high is the START condi- 9.2.10.1 WCOL STATUS FLAG
tion. This causes the S bit (SSPSTAT<3>) to be set.
When the S bit is set, the baud rate generator is If the user writes the SSPBUF when a START
reloaded with the contents of SSPADD<6:0> and sequence is in progress, the WCOL is set and the con-
resumes its count. When the baud rate generator times tents of the buffer are unchanged (the write doesn’t
out (TBRG) the START condition is complete, concur- occur).
rent with the following events:
Note: Because queueing of events is not
• The SEN bit (SSPCON2<0>) is automatically allowed, writing to the lower five bits of
cleared by hardware, SSPCON2 is disabled until the START
• The baud rate generator is suspended leaving the condition is complete.
SDA line held low.
• The SSPIF flag is set.

FIGURE 9-16: FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here.
SDA = 1,
At completion of START bit,
SCL = 1
Hardware clears SEN bit
and sets SSPIF bit
TBRG TBRG Write to SSPBUF occurs here

1st Bit 2nd Bit

SDA
TBRG

SCL
TBRG
S

 2002 Microchip Technology Inc. Advance Information DS41120B-page 85

PIC16C717/770/771
9.2.11 I2C MASTER MODE REPEATED Immediately following the SSPIF bit transition to true,
START CONDITION TIMING the user may write the SSPBUF with the 7-bit address
in 7-bit mode, or the default first address in 10-bit
A Repeated START condition occurs when the RSEN mode. After the first eight bits are transmitted and an
bit (SSPCON2<1>) is set high while the I2C module is ACK is received, the user may then perform one of the
in the idle state. When the RSEN bit is set, the SCL pin following:
is asserted low. When the SCL pin is sampled low, the
baud rate generator is loaded with the contents of • Transmit an additional eight bits of address (if the
SSPADD<6:0> and begins counting. The SDA pin is user transmitted the first half of a 10-bit address
released (brought high) for one baud rate generator with R/W = 0),
count (TBRG). When the baud rate generator times out, • Transmit eight bits of data (if the user transmitted
if SDA is sampled high, the SCL pin will be de-asserted a 7-bit address with R/W = 0), or
(brought high). When SCL is sampled high, the baud • Receive eight bits of data (if the user transmitted
rate generator is reloaded with the contents of either the first half of a 10-bit address or a 7-bit
SSPADD<6:0> and begins counting. SDA and SCL address with R/W = 1).
must be sampled high for one TBRG period. This action
is then followed by assertion of the SDA pin (SDA is 9.2.11.1 WCOL STATUS FLAG
low) for one TBRG period while SCL is high. As soon as
If the user writes the SSPBUF when a Repeated
a START condition is detected on the SDA and SCL
START sequence is in progress, then WCOL is set and
pins, the S bit (SSPSTAT<3>) will be set. Following
the contents of the buffer are unchanged (the write
this, the baud rate generator is reloaded with the con-
doesn’t occur).
tents of SSPAD<6:0> and begins counting. When the
BRG times out a third time, the RSEN bit in the Note: Because queueing of events is not
SSPCON2 register is automatically cleared and SCL is allowed, writing of the lower five bits of
pulled low. The SSPIF flag is set, which indicates the SSPCON2 is disabled until the Repeated
Restart sequence is complete. START condition is complete.

Note 1: If RSEN is set while another event is in

progress, it will not take effect. Queuing of
events is not allowed.
2: A bus collision during the Repeated
START condition occurs if either of the
following is true:
a) SDA is sampled low when SCL
goes from low to high.
b) SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data “1”.

FIGURE 9-17: REPEAT START CONDITION WAVEFORM

Set S (SSPSTAT<3>)
Write to SSPCON2 SDA = 1,
occurs here. At completion of START bit,
SCL = 1 hardware clears RSEN bit
SDA = 1,
SCL (no change) and sets SSPIF

TBRG TBRG TBRG

1st Bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here.
End of Xmit
TBRG

SCL TBRG
Sr = Repeated START

DS41120B-page 86 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
9.2.12 I2C MASTER MODE A typical transmit sequence would go as follows:
TRANSMISSION a) The user generates a START Condition by set-
In Master-transmitter mode, serial data is output ting the START enable bit (SEN) in SSPCON2.
through SDA, while SCL outputs the serial clock. The b) SSPIF is set at the completion of the START
first byte transmitted contains seven bits of address sequence.
data and the Read/Write (R/W) bit. In this case, the R/ c) The user resets the SSPIF bit and loads the
W bit will be logic ’0’. Subsequent serial data is trans- SSPBUF with seven bits of address plus R/W bit
mitted eight bits at a time. After each byte is transmit- to transmit.
ted, an Acknowledge bit is received. START and STOP d) Address and R/W is shifted out the SDA pin until
conditions are output to indicate the beginning and the all eight bits are transmitted.
end of a serial transfer. e) The MSSP Module shifts in the ACK bit from the
Transmission of a data byte, a 7-bit address, or either slave device, and writes its value into the
half of a 10-bit address is accomplished by simply writ- SSPCON2 register (SSPCON2<6>).
ing a value to the SSPBUF register. This action will set f) The module generates an interrupt at the end of
the buffer full flag (BF) and allow the baud rate genera- the ninth clock cycle by setting SSPIF.
tor to begin counting and start the next transmission. g) The user resets the SSPIF bit and loads the
Each bit of address/data will be shifted out onto the SSPBUF with eight bits of data.
SDA pin after the falling edge of SCL is asserted (see
h) DATA is shifted out the SDA pin until all eight bits
data hold time spec). SCL is held low for one baud rate
are transmitted.
generator roll over count (TBRG). Data should be valid
before SCL is released high (see data setup time i) The MSSP Module shifts in the ACK bit from the
spec). When the SCL pin is released high, it is held that slave device and writes its value into the
way for TBRG, the data on the SDA pin must remain sta- SSPCON2 register (SSPCON2<6>).
ble for that duration and some hold time after the next j) The MSSP module generates an interrupt at the
falling edge of SCL. After the eighth bit is shifted out end of the ninth clock cycle by setting the SSPIF
(the falling edge of the eighth clock), the BF flag is bit.
cleared and the master releases SDA. This allows the k) The user resets the SSPIF bit and generates a
slave device being addressed to respond with an ACK STOP condition by setting the STOP enable bit
bit during the ninth bit time. The status of ACK is read PEN in SSPCON2.
into the ACKDT on the rising edge of the ninth clock. If l) SSPIF is set when the STOP condition is complete.
the master receives an Acknowledge, the Acknowl-
edge status bit (ACKSTAT) is cleared. Otherwise, the 9.2.12.1 BF STATUS FLAG
bit is set. The SSPIF is set on the falling edge of the
ninth clock, and the master clock (baud rate generator) In Transmit mode, the BF bit (SSPSTAT<0>) is set
is suspended until the next data byte is loaded into the when the CPU writes to SSPBUF and is cleared when
SSPBUF leaving SCL low and SDA unchanged all eight bits are shifted out.
(Figure 9-18).
9.2.12.2 WCOL STATUS FLAG

If the user writes the SSPBUF when a transmit is

already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.

9.2.12.3 ACKSTAT STATUS FLAG

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.

 2002 Microchip Technology Inc. Advance Information DS41120B-page 87

 FIGURE 9-18:

DS41120B-page 88
Write SSPCON2<0> SEN = 1 ACK from slave clears ACKSTAT bit (SSPCON2<6>)
START condition begins NACK from slave sets ACKSTAT bit (SSPCON2<6>)
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit Address NACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

SSPBUF written with 7-bit address and R/W

start transmit
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
PIC16C717/770/771

SCL held low

until SSPBUF is
written.
SSPIF
cleared in software service routine
cleared in software From SSP interrupt
Cleared in software

BF (SSPSTAT<0>)

SSPBUF written SSPBUF is written in software

Advance Information
SEN

After START condition SEN cleared by hardware.

PEN

PEN is set to initiate STOP condition

I 2C MASTER MODE WAVEFORMS FOR TRANSMISSION (7 OR 10-BIT ADDRESS)

 2002 Microchip Technology Inc.

 PIC16C717/770/771
9.2.13 I2C MASTER MODE RECEPTION A typical receive sequence would go as follows:
In Master-receive mode, the first byte transmitted con- a) The user generates a START Condition by set-
tains seven bits of address data and the R/W bit. In this ting the START enable bit (SEN) in SSPCON2.
case, the R/W bit will be logic ’1’. Thus, the first byte b) SSPIF is set at the completion of the START
transmitted is a 7-bit slave address followed by a ’1’ to sequence.
indicate receive. Serial data is received via SDA, while c) The user resets the SSPIF bit and loads the
SCL outputs the serial clock. Serial data is received SSPBUF with seven bits of address in the MSbs
eight bits at a time. After each byte is received, an and the LSb (R/W bit) set to '1' for receive.
Acknowledge bit is transmitted. The START condition d) Address and R/W is shifted out the SDA pin until
indicates the beginning of a transmission. The master- all eight bits are transmitted.
receiver terminates slave transmission by responding
e) The MSSP Module shifts in the ACK bit from the
to the last byte with a NACK Acknowledge and follows
slave device, and writes its value into the
this with a STOP condition to indicate to other masters
SSPCON2 register (SSPCON2<6>).
that the bus is free.
f) The module generates an interrupt at the end of
Master mode reception is enabled by setting the the ninth clock cycle by setting SSPIF.
receive enable bit, RCEN (SSPCON2<3>), immedi-
g) The user resets the SSPIF bit and sets the
ately following the Acknowledge sequence.
RCEN bit to enable reception.
Note: The MSSP Module must be in an IDLE h) DATA is shifted into the SDA pin until all eight
STATE before the RCEN bit is set or the bits are received.
RCEN bit will be disregarded. i) The MSSP module sets the SSPIF bit and clears
The baud rate generator begins counting, and on each the RCEN bit at the falling edge of the eighth
rollover, the state of the SCL pin changes (high to low/ clock.
low to high) and data is shifted into the SSPSR. After j) The user resets the SSPIF bit and sets the
the falling edge of the eighth clock, the following events ACKDT bit to '0' (ACK), if another byte is antici-
occur: pated. Otherwise, the ACKDT bit is set to '1'
• The receive enable bit is automatically cleared. (NACK) to terminate reception. The user sets
ADKEN to start the Acknowledge sequence.
• The contents of the SSPSR are loaded into the
SSPBUF. k) The MSSP module sets the SSPIF bit at the
completion of the Acknowledge.
• The BF flag is set.
l) If a NACK was sent in step ( j), then the user pro-
• The SSPIF is set.
ceeds with step ( m). Otherwise, reception con-
• The baud rate generator is suspended from tinues by repeating steps ( g) through ( j).
counting, holding SCL low.
m) The user generates a STOP condition by setting
The SSP is now in IDLE state, awaiting the next com- the STOP enable bit PEN in SSPCON2.
mand. When the buffer is read by the CPU, the BF flag n) SSPIF is set when the STOP condition is complete.
is automatically cleared. The user can then send an
Acknowledge bit at the end of reception by clearing the 9.2.13.1 BF STATUS FLAG
ACKDT bit (SSPCON2<5>) and setting the Acknowl-
edge sequence enable bit, ACKEN (SSPCON2<4>). In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
by hardware when SSPBUF is read.

9.2.13.2 SSPOV STATUS FLAG

In receive operation, SSPOV is set when eight bits are

received into the SSPSR and the BF flag is already set
from a previous reception.

9.2.13.3 WCOL STATUS FLAG

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).

 2002 Microchip Technology Inc. Advance Information DS41120B-page 89

 FIGURE 9-19:

DS41120B-page 90
Set ACKDT (SSPCON2<5>) = 0 Set ACKDT (SSPCON2<5>) = 1
and set ACKEN (SSPCON2<4>) = 1 and set ACKEN (SSPCON2<4>) = 1
to start ACK Acknowledge sequence to start NACK Acknowledge sequence
Write to SSPCON2<0>, (SEN = 1)
Begin START Condition ACK from Master
Master configured as a receiver SDA = ACKDT = 0
SEN = 0 by programming SSPCON2<3>, (RCEN = 1)
PEN bit = 1
Write to SSPBUF ACK from Slave RCEN cleared RCEN = 1 to start RCEN cleared
automatically next receive automatically written here
starts transmit
Transmit Address to Slave R/W = 1 Receiving Data from Slave Receiving Data from Slave NACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

Master sends NACK to

Bus Master
terminate slave transmission
terminates
transfer
PIC16C717/770/771

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK SSPIF occurs at
end of receive SSPIF occurs
SSPIF occurs SSPIF occurs at end of Acknow-
at end of receive at end of Acknowledge ledge sequence
SSPIF sequence

Cleared in software SSPIF occurs at end

SSPIF occurs at end of transmit SSPBUF is read of STOP sequence
SSPIF occurs at end of Start
clearing BF flag

Advance Information
BF
(SSPSTAT<0>)
Last bit is shifted into SSPSR and
Writing SSPBUF causes BF clears automatically contents are unloaded into SSPBUF
BF to go high when the last bit is shifted out.

ACKEN
ACKEN bit is set to initiate ACKEN is cleared by hardware
Acknowledge sequence
I 2C MASTER WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

 2002 Microchip Technology Inc.

 PIC16C717/770/771
9.2.14 ACKNOWLEDGE SEQUENCE arbitration), the baud rate generator is reloaded and
TIMING counts for another TBRG. At the completion of the TBRG
period, the following events occur (see Figure 9-20):
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN • The SCL pin is pulled low.
(SSPCON2<4>). When this bit is set, the SCL pin is • The ACKEN bit is automatically cleared.
pulled low and the contents of the Acknowledge data bit • The baud rate generator is turned off.
ACKDT (SSPCON2<5>) is presented on the SDA pin. • The MSSP module goes into IDLE mode.
If the user wishes to generate an Acknowledge (ACK),
then the ACKDT bit should be cleared. Otherwise, the 9.2.14.1 WCOL STATUS FLAG
user should set the ACKDT bit (NACK) before starting
an Acknowledge sequence. The baud rate generator is If the user writes the SSPBUF when an Acknowledge
then loaded from SSPADD<6:0> and counts for one sequence is in progress, the WCOL is set and the con-
rollover period (TBRG). The SCL pin is then de-asserted tents of the buffer are unchanged (the write doesn’t
(pulled high). When the SCL pin is sampled high (clock occur).

FIGURE 9-20: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,
Write to SSPCON2 ACKEN automatically cleared
ACKEN = 1, ACKDT = 0

TBRG TBRG
SDA D0 ACK

SCL 8 9

SSPIF

SSPIF occurs at the Cleared in Cleared in

end of receive software software
SSPIF occurs at the end
of Acknowledge sequence

Note: TBRG = one baud rate generator period.

 2002 Microchip Technology Inc. Advance Information DS41120B-page 91

PIC16C717/770/771
9.2.15 STOP CONDITION TIMING times out (TBRG) the STOP condition is complete and
the PEN bit is cleared and the SSPIF bit is set
The master asserts a STOP condition on the SDA and (Figure 9-21).
SCL pins at the end of a receive/transmit by setting the
Stop Sequence Enable bit PEN (SSPCON2<2>). At the Whenever the firmware decides to take control of the
end of a receive/transmit plus Acknowledge, the SCL bus, it should first determine if the bus is busy by check-
line is held low immediately following the falling edge of ing the S and P bits in the SSPSTAT register. When the
the ninth SCL pulse. When the PEN bit is set, the mas- MSSP module detects a START or STOP condition the
ter will assert the SDA line low. When the SDA line is SSPIF flag is set. If the bus is busy (S bit is set), then
sampled low, the baud rate generator is loaded from the CPU can be configured to be interrupted when
SSPADD<6:0> and counts down to 0. When the baud when the bus is free by enabling the SSPIF interrupt to
rate generator times out, the SCL pin is brought high, detect the STOP bit.
the BRG is reloaded and one TBRG (baud rate genera-
9.2.15.1 WCOL STATUS FLAG
tor rollover count) later, the SDA pin is de-asserted.
The SDA pin transition from low to high while SCL is If the user writes the SSPBUF when a STOP sequence
high is the STOP condition and causes the P bit (SSP- is in progress, then WCOL is set and the contents of the
STAT<4>) to be set. Following this the baud rage gen- buffer are unchanged (the write doesn’t occur).
erator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the baud rate generator

FIGURE 9-21: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSPCON2
P bit (SSPSTAT<4>) is set
Set PEN

Falling edge of PEN bit (SSPCON2<2>) is cleared by

9th clock hardware and the SSPIF bit is set
TBRG
SCL

SDA NACK
P
TBRG TBRG TBRG
SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup STOP condition.

Note: TBRG = one baud rate generator period.

DS41120B-page 92 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
9.2.16 CLOCK ARBITRATION SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
Clock arbitration occurs when the master, during any the contents of SSPADD<6:0> and begins counting.
receive, transmit or repeated START/STOP condition, This ensures that the SCL high time will always be at
de-asserts the SCL pin (SCL allowed to float high). least one BRG rollover count in the event that the clock
When the SCL pin is allowed to float high, the baud rate is held low by an external device (Figure 9-22).
generator (BRG) is suspended from counting until the

FIGURE 9-22: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count BRG overflow occurs,
to measure high time interval Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.

SCL

SCL line sampled once every machine cycle (Tosc • 4).

Hold off BRG until SCL is sampled high.

SDA

TBRG TBRG TBRG

 2002 Microchip Technology Inc. Advance Information DS41120B-page 93

PIC16C717/770/771
9.2.17 MULTI -MASTER A bus collision during a START, Repeated START,
COMMUNICATION, BUS STOP or Acknowledge condition results in the following
COLLISION, AND BUS events:
ARBITRATION • The condition is aborted.
• The SDA and SCL lines are de-asserted.
Multi-master mode support is achieved by bus arbitra-
• The respective control bits in the SSPCON2 regis-
tion. When the master outputs address/data bits onto
ter are cleared.
the SDA pin, bus arbitration is initiated when one mas-
ter outputs a ’1’ on SDA (by letting SDA float high) and When the user services the bus collision interrupt ser-
another master asserts a ’0’. If the expected data on vice routine, and if the I2C bus is free, the user can
SDA is a ’1’ and the data sampled on the SDA pin = ’0’, resume communication by asserting a START condi-
then a bus collision has taken place. The master that tion.
expected a ‘1’ will set the Bus Collision Interrupt Flag, The Master will continue to monitor the SDA and SCL
BCLIF, and reset the I2C port to its IDLE state. pins, and if a STOP condition occurs, the SSPIF bit will
(Figure 9-23). be set.
A bus collision during transmit results in the following A write to the SSPBUF will start the transmission of
events: data at the first data bit, regardless of where the trans-
• The transmission is halted. mitter left off when bus collision occurred.
• The BF flag is cleared In Multi-Master mode, the interrupt generation on the
• The SDA and SCL lines are de-asserted detection of START and STOP conditions allows the
• The restriction on writing to the SSPBUF during determination of when the bus is free. Control of the I2C
transmission is lifted. bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
When the user services the bus collision interrupt ser- cleared.
vice routine, and if the I2C bus is free, the user can
resume communication by asserting a START condi-
tion.

FIGURE 9-23: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA line pulled low Sample SDA. While SCL is high

Data changes by another source data doesn’t match what is driven
while SCL = 0 by the master.
Bus collision has occurred.
SDA released
by master

SDA

SCL
Set bus collision
interrupt.

BCLIF

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 PIC16C717/770/771
9.2.17.1 BUS COLLISION DURING A START while SDA is high, a bus collision occurs, because it is
CONDITION assumed that another master is attempting to drive a
data ’1’ during the START condition.
During a START condition, a bus collision occurs if:
If the SDA pin is sampled low during this count, the
a) SDA or SCL are sampled low at the beginning of BRG is reset and the SDA line is asserted early
the START condition (Figure 9-24). (Figure 9-26). If however a ’1’ is sampled on the SDA
b) SCL is sampled low before SDA is asserted low. pin, the SDA pin is asserted low at the end of the BRG
(Figure 9-25). count. The baud rate generator is then reloaded and
During a START condition both the SDA and the SCL counts down to 0, and during this time, if the SCL pin is
pins are monitored. sampled as ’0’, a bus collision does not occur. At the
end of the BRG count the SCL pin is asserted low.
If:
Note: The reason that bus collision is not a factor
the SDA pin is already low
during a START condition is that no two
or the SCL pin is already low,
bus masters can assert a START condition
then: at the exact same time. Therefore, one
the START condition is aborted, master will always assert SDA before the
and the BCLIF flag is set, other. This condition does not cause a bus
and the SSP module is reset to its IDLE state collision, because the two masters must be
(Figure 9-24). allowed to arbitrate the first address follow-
ing the START condition. If the address is
The START condition begins with the SDA and SCL
the same, arbitration must be allowed to
pins de-asserted. When the SDA pin is sampled high,
continue into the data portion, REPEATED
the baud rate generator is loaded from SSPADD<6:0>
START or STOP conditions.
and counts down to 0. If the SCL pin is sampled low

FIGURE 9-24: BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1

SDA

SCL
Set SEN, enable START SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL=1 SSP module reset into IDLE state.
SEN
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1
SSPIF and BCLIF are
cleared in software.

SSPIF

SSPIF and BCLIF are

cleared in software.

 2002 Microchip Technology Inc. Advance Information DS41120B-page 95

PIC16C717/770/771
FIGURE 9-25: BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG TBRG
SDA

SCL Set SEN, enable START

sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
SEN
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF.
BCLIF
Interrupts cleared
in software.
S ’0’ ’0’

SSPIF ’0’ ’0’

FIGURE 9-26: BRG RESET DUE TO SDA COLLISION DURING START CONDITION

SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SDA SDA pulled low by other master.
Reset BRG and assert SDA

SCL s
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
BCLIF ’0’

SSPIF
SDA = 0, SCL = 1 Interrupts cleared
Set SSPIF in software.

DS41120B-page 96 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
9.2.17.2 BUS COLLISION DURING A REPEATED ’0’). If however SDA is sampled high, then the BRG is
START CONDITION reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs,
During a Repeated START condition, a bus collision because no two masters can assert SDA at exactly the
occurs if: same time.
a) A low level is sampled on SDA when SCL goes If, however, SCL goes from high to low before the BRG
from low level to high level. times out and SDA has not already been asserted, then
b) SCL goes low before SDA is asserted low, indi- a bus collision occurs. In this case, another master is
cating that another master is attempting to trans- attempting to transmit a data ’1’ during the Repeated
mit a data ’1’. START condition.
When the master module de-asserts SDA and the pin If at the end of the BRG time-out both SCL and SDA are
is allowed to float high, the BRG is loaded with still high, the SDA pin is driven low, the BRG is
SSPADD<6:0>, and counts down to ‘0’. The SCL pin is reloaded, and begins counting. At the end of the count,
then de-asserted, and when sampled high, the SDA pin regardless of the status of the SCL pin, the SCL pin is
is sampled. If SDA is low, a bus collision has occurred driven low and the Repeated START condition is com-
(i.e., another master is attempting to transmit a data plete (Figure 9-27).

FIGURE 9-27: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL

RSEN

BCLIF

Cleared in software
S ’0’ ’0’

SSPIF ’0’ ’0’

FIGURE 9-28: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF Set BCLIF. Release SDA and SCL
Interrupt cleared
in software
RSEN

S ’0’ ’0’

SSPIF ’0’ ’0’

 2002 Microchip Technology Inc. Advance Information DS41120B-page 97

PIC16C717/770/771
9.2.17.3 BUS COLLISION DURING A STOP The STOP condition begins with SDA asserted low.
CONDITION When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a STOP condition if: the baud rate generator is loaded with SSPADD<6:0>
a) After the SDA pin has been de-asserted and and counts down to ‘0’. After the BRG times out SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out. occurred. This is due to another master attempting to
b) After the SCL pin is de-asserted, SCL is sam- drive a data '0' (Figure 9-29). If the SCL pin is sampled
pled low before SDA goes high. low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempt-
ing to drive a data '0' (Figure 9-30).

FIGURE 9-29: BUS COLLISION DURING A STOP CONDITION (CASE 1)

TBRG TBRG TBRG SDA sampled

low after TBRG,
Set BCLIF
SDA

SDA asserted low

SCL

PEN

BCLIF

P ’0’ ’0’

SSPIF ’0’ ’0’

FIGURE 9-30: BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG TBRG TBRG

SDA

Assert SDA SCL goes low before SDA goes high

Set BCLIF
SCL

PEN

BCLIF

P ’0’

SSPIF ’0’

DS41120B-page 98 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
9.2.18 CONNECTION CONSIDERATIONS example, with a supply voltage of VDD = 5V+10% and
FOR I2C BUS VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 kΩ. VDD as a function of Rp is shown in Figure 9-31.
For Standard mode I2C bus devices, the values of The desired noise margin of 0.1VDD for the low level
resistors Rp and Rs in Figure 9-31 depends on the fol- limits the maximum value of Rs. Series resistors are
lowing parameters optional and used to improve ESD susceptibility.
• Supply voltage The bus capacitance is the total capacitance of wire,
• Bus capacitance connections, and pins. This capacitance limits the max-
• Number of connected devices (input current + imum value of Rp due to the specified rise time
leakage current). (Figure 9-31).
The supply voltage limits the minimum value of resistor The SMP bit is the slew rate control enabled bit. This bit
Rp due to the specified minimum sink current of 3 mA is in the SSPSTAT register, and controls the slew rate
at VOL max = 0.4V for the specified output stages. For of the I/O pins when in I2C mode (master or slave).

FIGURE 9-31: SAMPLE DEVICE CONFIGURATION FOR I2C BUS

VDD + 10%

DEVICE
Rp Rp

Rs Rs

SDA

SCL

Cb=10 pF to 400 pF

Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also
connected.

TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT

0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Dh PIR2 LVDIF — — — BCLIF — — CCP2IF 0--- 0--0 0--- 0--0
8Dh PIE2 LVDIE — — — BCLIE — — CCP2IE 0--- 0--0 0--- 0--0
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
93h SSPADD Synchronous Serial Port (I2C Mode) Address Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the MSSP in I2C mode.

 2002 Microchip Technology Inc. Advance Information DS41120B-page 99

PIC16C717/770/771
NOTES:

DS41120B-page 100 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
10.0 VOLTAGE REFERENCE The source for the reference voltages comes from the
bandgap reference circuit. The bandgap circuit is ener-
MODULE AND LOW-VOLTAGE gized anytime the reference voltage is required by the
DETECT other sub-modules, and is powered down when not in
The Voltage Reference module provides reference use. The control registers for this module are LVDCON
voltages for the Brown-out Reset circuitry, the Low-volt- and REFCON, as shown in Register 10-1 and
age Detect circuitry and the A/D converter. Figure 10-2.

REGISTER 10-1: LOW-VOLTAGE DETECT CONTROL REGISTER (LVDCON: 9Ch)

U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
— — BGST LVDEN LV3 LV2 LV1 LV0
bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5 BGST: Bandgap Stable Status Flag bit
1 = Indicates that the bandgap voltage is stable, and LVD interrupt is reliable
0 = Indicates that the bandgap voltage is not stable, and LVD interrupt should not be enabled
bit 4 LVDEN: Low-voltage Detect Power Enable bit
1 = Enables LVD, powers up bandgap circuit and reference generator
0 = Disables LVD, powers down bandgap circuit if unused by BOR or VRH/VRL
bit 3-0 LV<3:0>: Low Voltage Detection Limit bits(1)
1111 = External analog input is used
1110 = 4.5V
1101 = 4.2V
1100 = 4.0V
1011 = 3.8V
1010 = 3.6V
1001 = 3.5V
1000 = 3.3V
0111 = 3.0V
0110 = 2.8V
0101 = 2.7V
0100 = 2.5V
0011 = Reserved. Do not use.
0010 = Reserved. Do not use.
0001 = Reserved. Do not use.
0000 = Reserved. Do not use.

Note: These are the minimum trip points for the LVD. See Table 15-8 for the trip point tol-
erances. Selection of reserved setting may result in an inadvertent interrupt.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc. DS41120B-page 101

PIC16C717/770/771
REGISTER 10-2: VOLTAGE REFERENCE CONTROL REGISTER (REFCON: 9BH)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
VRHEN VRLEN VRHOEN VRLOEN — — — —
bit 7 bit 0

bit 7 VRHEN: Voltage Reference High Enable bit (VRH = 4.096V nominal)
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL
bit 6 VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V nominal)
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRH
bit 5 VRHOEN: High Voltage Reference Output Enable bit(1)
1 = Enabled, VRH analog reference is output on RA3 if enabled (VRHEN = 1)
0 = Disabled, analog reference is used internally only(1)
bit 4 VRLOEN: Low Voltage Reference Output Enable bit
1 = Enabled, VRL analog reference is output on RA2 if enabled (VRLEN = 1)
0 = Disabled, analog reference is used internally only
bit 3-0 Unimplemented: Read as '0’

Note 1: RA2 and RA3 must be configured as analog inputs when the VREF output functions
are enabled (See ANSEL on page 25).

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 102  2002 Microchip Technology Inc.

 PIC16C717/770/771
10.1 Bandgap Voltage Reference The VRL reference is enabled by setting control bit
VRLEN (REFCON<6>). When this bit is set, the gain
The bandgap module generates a stable voltage refer- amplifier is enabled. After a specified start-up time a
ence of over a range of temperatures and device sup- stable reference of 2.048V nominal is generated and
ply voltages. This module is enabled anytime any of the can be used by the A/D converter as a reference input.
following are enabled:
Each voltage reference is available for external use via
• Brown-out Reset VRL and VRH pins.
• Low-voltage Detect
Each reference, if enabled, can be output on an exter-
• Either of the internal analog references (VRH, nal pin by setting the VRHOEN (high reference output
VRL) enable) or VRLOEN (low reference output enable) con-
Whenever the above are all disabled, the bandgap trol bit. If the reference is not enabled, the VRHOEN
module is disabled and draws no current. and VRLOEN bits will have no effect on the corre-
sponding pin. The device specific pin can then be used
10.2 Internal VREF for A/D Converter as general purpose I/O.
The bandgap output voltage is used to generate two Note: If VRH or VRL is enabled and the other ref-
stable references for the A/D converter module. These erence (VRL or VRH), the BOR, and the
references are enabled in software to provide the user LVD modules are not enabled, the band-
with the means to turn them on and off in order to min- gap will require a start-up time before the
imize current consumption. Each reference can be indi- bandgap reference is stable. Before using
vidually enabled. the internal VRH or VRL reference, ensure
that the bandgap reference voltage is sta-
The VRH reference is enabled with control bit VRHEN
ble by monitoring the BGST bit in the LVD-
(REFCON<7>). When this bit is set, the gain amplifier
CON register. The voltage references will
is enabled. After a specified start-up time a stable ref-
not be reliable until the bandgap is stable
erence of 4.096V nominal is generated and can be
as shown by BGST being set.
used by the A/D converter as a reference input.

FIGURE 10-1: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT

LVDCON REFCON
VDD
LVDEN
VRHEN + VRLEN

generates
16 to 1 MUX

RA1/AN1/LVDIN LVDIF

VRH
BODEN

BGAP VRL
LVDEN

 2002 Microchip Technology Inc. DS41120B-page 103

PIC16C717/770/771
10.3 Low Voltage Detect (LVD) Once the LV bits have been programmed for the spec-
ified trip voltage, the low-voltage detect circuitry is then
This module is used to generate an interrupt when the enabled by setting the LVDEN (LVDCON<4>) bit.
supply voltage falls below a specified “trip” voltage.
This module operates completely under software If the bandgap reference voltage is previously unused
control. This allows a user to power the module on by either the brown-out circuitry or the voltage refer-
and off to periodically monitor the supply voltage, and ence circuitry, then the bandgap circuit requires a time
thus minimize total current consumption. to start-up and become stable before a low voltage con-
dition can be reliably detected. The low-voltage inter-
The LVD module is enabled by setting the LVDEN bit in rupt flag is prevented from being set until the bandgap
the LVDCON register. The “trip point” voltage is the has reached a stable reference voltage.
minimum supply voltage level at which the device can
operate before the LVD module asserts an interrupt. When the bandgap is stable the BGST (LVDCON<5>)
When the supply voltage is equal to or less than the trip bit is set indicating that the low-voltage interrupt flag bit
point, the module will generate an interrupt signal set- is released to be set if VDD is equal to or less than the
ting interrupt flag bit LVDIF. If interrupt enable bit LVDIE LVD trip point.
was set, then an interrupt is generated. The LVD inter- 10.3.1 EXTERNAL ANALOG VOLTAGE INPUT
rupt can wake the device from SLEEP. The "trip point"
voltage is software programmable to any one of 16 val- The LVD module has an additional feature that allows
ues, five of which are reserved (See Figure 10-1). The the user to supply the trip voltage to the module from
trip point is selected by programming the LV<3:0> bits an external source. This mode is enabled when
(LVDCON<3:0>). LV<3:0> = 1111. When these bits are set the compar-
ator input is multiplexed from an external input pin
Note: The LVDIF bit can not be cleared until the
(RA1/AN1/LVDIN).
supply voltage rises above the LVD trip
point. If interrupts are enabled, clear the
LVDIE bit once the first LVD interrupt
occurs to prevent reentering the interrupt
service routine immediately after exiting
the ISR.

DS41120B-page 104  2002 Microchip Technology Inc.

 PIC16C717/770/771
11.0 ANALOG-TO-DIGITAL The A/D module has four registers. These registers
are:
CONVERTER (A/D) MODULE
• A/D Result Register Low ADRESL
The analog-to-digital (A/D) converter module has six
• A/D Result Register High ADRESH
inputs for the PIC16C717/770/771.
• A/D Control Register 0 (ADCON0)
The PIC16C717 analog-to-digital converter (A/D)
• A/D Control Register 1 (ADCON1)
allows conversion of an analog input signal to a corre-
sponding 10-bit digital value, while the A/D converter A device RESET forces all registers to their RESET
in the PIC16C770/771 allows conversion to a corre- state. This forces the A/D module to be turned off and
sponding 12-bit digital value. The A/D module has up any conversion is aborted.
to 6 analog inputs, which are multiplexed into one
sample and hold. The output of the sample and hold is 11.1 Control Registers
the input into the converter, which generates the result The ADCON0 register, shown in Register 11-1, con-
via successive approximation. The analog reference trols the operation of the A/D module. The ADCON1
voltages are software selectable to either the device’s register, shown in Register 11-2, configures the func-
analog positive and negative supply voltages (AVDD/ tions of the port pins, the voltage reference configura-
AVSS), the voltage level on the VREF+ and VREF- pins, tion and the result format. The ANSEL register, shown
or internal voltage references if enabled (VRH, VRL). in Register 3-1, selects between the Analog or Digital
The A/D converter can be triggered by setting the GO/ Port Pin modes. The port pins can be configured as
DONE bit, or by the special event Compare mode of analog inputs or as digital I/O.
the ECCP module. When conversion is complete, the The combination of the ADRESH and ADRESL regis-
GO/DONE bit returns to ’0’, the ADIF bit in the PIR1 ters contain the result of the A/D conversion. The reg-
register is set, and an A/D interrupt will occur, if ister pair is referred to as the ADRES register. When
enabled. the A/D conversion is complete, the result is loaded
The A/D converter has a unique feature of being able into ADRES, the GO/DONE bit (ADCON0<2>) is
to operate while the device is in SLEEP mode. To oper- cleared, and the A/D interrupt flag ADIF is set. The
ate in SLEEP, the A/D conversion clock must be block diagram of the A/D module is shown in
derived from the A/D’s internal RC oscillator. Figure 11-3.

 2002 Microchip Technology Inc. DS41120B-page 105

PIC16C717/770/771
REGISTER 11-1: A/D CONTROL REGISTER 0 (ADCON0: 1Fh).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON
bit 7 bit 0

bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits

If internal VRL and/or VRH are not used for A/D reference (VCFG<2:0> = 000, 001, 011
or 101):
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from a dedicated RC oscillator)
If internal VRL and/or VRH are used for A/D reference (VCFG<2:0> = 010, 100, 110 or 111):
00 = FOSC/16
01 = FOSC/64
10 = FOSC/256
11 = FRC/8
bit 5-3,1 CHS:<3:0>: Analog Channel Select bits
0000 = channel 00 (AN0)
0001 = channel 01 (AN1)
0010 = channel 02 (AN2)
0011 = channel 03 (AN3)
0100 = channel 04 (AN4)
0101 = channel 05 (AN5)
0110 = reserved, do not select
0111 = reserved, do not select
1000 = reserved, do not select
1001 = reserved, do not select
1010 = reserved, do not select
1011 = reserved, do not select
1100 = reserved, do not select
1101 = reserved, do not select
1110 = reserved, do not select
1111 = reserved, do not select
bit 2 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter is shutoff and consumes no operating current

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

DS41120B-page 106  2002 Microchip Technology Inc.

 PIC16C717/770/771
REGISTER 11-2: A/D CONTROL REGISTER 1 (ADCON1: 9Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG2 VCFG1 VCFG0 Reserved Reserved Reserved Reserved
bit 7 bit 0

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified
0 = Left justified
bit 6-4 VCFG<2:0>: Voltage Reference Configuration bits

A/D VREF+ A/D VREF-

000 AVDD(1) AVSS(2)

001 External VREF+ External VREF-

010 Internal VRH Internal VRL

011 External VREF+ AVSS(2)

100 Internal VRH AVSS(2)

101 AVDD(1) External VREF-

110 AVDD(1) Internal VRL

111 Internal VRL AVSS

bit 3-0 Reserved: Do not use.

Note 1: This parameter is VDD for the PIC16C717.

2: This parameter is VSS for the PIC16C717.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

The value that is in the ADRESH and ADRESL regis- The A/D conversion results can be left justified (ADFM
ters are not modified for a Power-on Reset. The bit cleared), or right justified (ADFM bit set).
ADRESH and ADRESL registers will contain unknown Figure 11-1 through Figure 11-2 show the A/D result
data after a Power-on Reset. data format of the PIC16C717/770/771.

FIGURE 11-1: PIC16C770/771 12-BIT A/D RESULT FORMATS

ADRESH (1Eh) ADRESL (9Eh)
Left Justified
MSB LSB
(ADFM = 0)
bit7 bit7

12-bit A/D Result Unused

Right Justified
MSB LSB
(ADFM = 1)
bit7 bit7

Unused 12-bit A/D Result

 2002 Microchip Technology Inc. DS41120B-page 107

PIC16C717/770/771
FIGURE 11-2: PIC16C717 10-BIT A/D RESULT FORMAT

(ADFM = 0) MSB LSB

bit7 bit7

10-bit A/D Result Unused

(ADFM = 1) MSB LSB

bit7 bit7

Unused 10-bit A/D Result Unused

After the A/D module has been configured as desired, 11.2.2 CONFIGURING THE REFERENCE
the selected channel must be acquired before the con- VOLTAGES
version is started. The analog input channels must
have their corresponding TRIS and ANSEL bits The VCFG bits in the ADCON1 register configure the
selected as an input. To determine acquisition time, see A/D module reference inputs. The reference high input
Section 11.6. After this acquisition time has elapsed, can come from an internal reference (VRH) or (VRL),
the A/D conversion can be started. The following steps an external reference (VREF+), or AVDD. The low refer-
should be followed for doing an A/D conversion: ence input can come from an internal reference (VRL),
an external reference (VREF-), or AVSS. If an external
11.2 Configuring the A/D Module reference is chosen for the reference high or reference
low inputs, the port pin that multiplexes the incoming
11.2.1 CONFIGURING ANALOG PORT external references is configured as an analog input,
PINS regardless of the values contained in the A/D port con-
figuration bits (PCFG<3:0>).
The ANSEL and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bit
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted. The proper
ANSEL bits must be set (analog input) to disable the
digital input buffer.
The A/D operation is independent of the state of the
TRIS bits and the ANSEL bits.
Note 1: When reading the PORTA register, all pins
configured as analog input channels will
read as ’0’.
2: When reading the PORTB register, all
pins configured as analog pins on
PORTB will be read as ’1’.
3: Analog levels on any pin that is defined as
a digital input, including the ANx pins, may
cause the input buffer to consume current
that is out of the devices specification.

DS41120B-page 108  2002 Microchip Technology Inc.

 PIC16C717/770/771
After the A/D module has been configured as desired 4. Wait the required acquisition time.
and the analog input channels have their correspond- 5. START conversion
ing TRIS bits selected for port inputs, the selected • Set GO/DONE bit (ADCON0)
channel must be acquired before conversion is
6. Wait 13TAD until A/D conversion is complete, by
started. The A/D conversion cycle can be initiated by
either:
setting the GO/DONE bit. The A/D conversion begins
and lasts for 13TAD. The following steps should be fol- • Polling for the GO/DONE bit to be cleared
lowed for performing an A/D conversion: OR
1. Configure port pins: • Waiting for the A/D interrupt
• Configure Analog Input mode (ANSEL) 7. Read A/D Result registers (ADRESH and
• Configure pin as input (TRISA or TRISB) ADRESL), clear ADIF if required.
2. Configure the A/D module 8. For next conversion, go to step 1, step 2 or step
• Configure A/D Result Format / voltage refer- 3 as required.
ence (ADCON1) Clearing the GO/DONE bit during a conversion will
• Select A/D input channel (ADCON0) abort the current conversion. The ADRESH and
• Select A/D conversion clock (ADCON0) ADRESL registers will be updated with the partially
completed A/D conversion value. That is, the
• Turn on A/D module (ADCON0)
ADRESH and ADRESL registers will contain the value
3. Configure A/D interrupt (if required) of the current incomplete conversion.
• Clear ADIF bit
Note: Do not set the ADON bit and the GO/
• Set ADIE bit
DONE bit in the same instruction. Doing so
• Set PEIE bit will cause the GO/DONE bit to be automat-
• Set GIE bit ically cleared.

FIGURE 11-3: A/D BLOCK DIAGRAM

CHS<3:0>

VAIN RB1/AN5/SS
(INPUT VOLTAGE) RB0/AN4/INT
RA3/AN3/VREF+/VRH

RA2/AN2/VREF-/VRL

RA1/AN1
AVDD
RA0/AN0

VREF+ VRH
(REFERENCE VRL
VOLTAGE +)

A/D VCFG<2:0>
CONVERTER

VREF-
VRL
(REFERENCE
VOLTAGE -)
AVSS
VCFG<2:0>

 2002 Microchip Technology Inc. DS41120B-page 109

PIC16C717/770/771
11.3 Selecting the A/D Conversion If the VRH or VRL are used for the A/D converter refer-
Clock ence, then the TAD requirement is automatically
increased by a factor of 8.
The A/D conversion cycle requires 13TAD: 1 TAD for set-
For correct A/D conversions, the A/D conversion clock
tling time, and 12 TAD for conversion. The source of the
(TAD) must be selected to ensure a minimum TAD time
A/D conversion clock is software selected. If neither the
of 1.6 µs. Table 11-1 shows the resultant TAD times
internal VRH nor VRL are used for the A/D converter,
derived from the device operating frequencies and the
the four possible options for TAD are:
A/D clock source selected.
• 2 TOSC
The ADIF bit is set on the rising edge of the 14th TAD.
• 8 TOSC The GO/DONE bit is cleared on the falling edge of the
• 32 TOSC 14th TAD.
• A/D RC oscillator

TABLE 11-1: TAD vs. DEVICE OPERATING FREQUENCIES

A/D Reference
A/D Clock Source (TAD) Device Frequency
Source
Operation ADCS<1:0> 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 00 100 ns(2) 400 ns(2) 500 ns(2) 1.6 µs
External VREF or
8 TOSC 01 400 ns(2) 1.6 µs 2.0 µs 6.4 µs
Analog Supply
32 TOSC 10 1.6 µs 6.4 µs(3) 8.0 µs(3) 25.6 µs(3)
A/D RC 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4)
Internal VRH or 16 TOSC 00 800 ns(2) 3.2 µs(2) 4 µs(2) 12.8 µs
VRL 64 TOSC 01 3.2 µs(2) 12.8 µs 16 µs 51.2 µs(3)
256 TOSC 10 12.8 µs 51.2 µs(3) 64 µs(3) 204.8 µs(3)
A/D RC 11 16 - 48 µs(4,5) 16 - 48 µs(4,5) 16 - 48 µs(4,5) 16 - 48 µs(4,5)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be
performed during SLEEP.
5: A/D RC clock source has a typical TAD time of 32 µs for VDD > 3.0V.

DS41120B-page 110  2002 Microchip Technology Inc.

 PIC16C717/770/771
11.4 A/D Conversions
Example 11-1 shows an example that performs an A/D
conversion. The port pins are configured as analog
inputs. The analog reference VREF+ is the device AVDD
and the analog reference VREF- is the device AVSS.
The A/D interrupt is enabled and the A/D conversion
clock is TRC. The conversion is performed on the AN0
channel.

EXAMPLE 11-1: PERFORMING AN A/D CONVERSION

BSF STATUS, RP0 ;Select Bank 1
CLRF ADCON1 ;Configure A/D Voltage Reference
MOVLW 0x01
MOVWF ANSEL ;disable AN0 digital input buffer
MOVWF TRISA ;RA0 is input mode
BSF PIE1, ADIE ;Enable A/D interrupt
BCF STATUS, RP0 ;Select Bank 0
MOVLW 0xC1 ;RC clock, A/D is on,
;Ch 0 is selected
MOVWF ADCON0 ;
BCF PIR1, ADIF ;Clear A/D Int Flag
BSF INTCON, PEIE ;Enable Peripheral
BSF INTCON, GIE ;Enable All Interrupts
;
; Ensure that the required sampling time for the
; selected input channel has lapsed. Then the
; conversion may be started.
BSF ADCON0, GO ;Start A/D Conversion
: ;The ADIF bit will be
;set and the GO/DONE bit
: ;cleared upon completion-
;of the A/D conversion.
; Wait for A/D completion and read ADRESH:ADRESL for result.

 2002 Microchip Technology Inc. DS41120B-page 111

PIC16C717/770/771
11.5 A/D Converter Module Operation
Figure 11-4 shows the flowchart of the A/D converter
module.

FIGURE 11-4: FLOW CHART OF A/D OPERATION

ADON = 0

Yes
ADON = 0?

No

Sample
Selected Channel

Yes
GO = 0?

No

A/D Clock
Yes Start of A/D SLEEP Yes Finish Conversion
Conversion Delayed Instruction? GO = 0
= RC? 1 Instruction Cycle ADIF = 1
No No

SLEEP Yes Abort Conversion Finish Conversion Wake-up Yes

Instruction? GO = 0 GO = 0 From SLEEP?
ADIF = 0 ADIF = 1
No No

Finish Conversion SLEEP Stay in SLEEP

GO = 0 Power-down A/D Power-down A/D
ADIF = 1

DS41120B-page 112  2002 Microchip Technology Inc.

 PIC16C717/770/771
11.6 A/D Sample Requirements EXAMPLE 11-2: A/D SAMPLING TIME
EQUATION
11.6.1 RECOMMENDED SOURCE VREF
V H OL D = V R E F – ----------------
IMPEDANCE 16384

  ------------------------------------------------------------------
–T C
- 
The maximum recommended impedance for ana- V R EF   C H O LD ( R I C + R S S + R S ) 
log sources is 2.5 kΩ. This value is calculated based V R EF – ---------------- = ( V R E F )  1 – e 
16384  
on the maximum leakage current of the input pin. The  
leakage current is 100 nA max., and the analog input
  ------------------------------------------------------------------
–T C
- 
voltage cannot be varied by more than 1/4 LSb or   C H O LD ( R I C + R SS + R S ) 
 1 
V R EF 1 – ---------------- = ( V R E F )  1 – e 
250 µV due to leakage. This places a requirement on  16384  
the input impedance of 250 µV/100 nA = 2.5 kΩ.  

Solving for TC:

11.6.2 SAMPLING TIME CALCULATION
T C = – C H O LD ( 1k + R S S + R S ) ln  ----------------
1
16384
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed Figure 11-3 shows the calculation of the minimum time
to fully charge to the input channel voltage level. The required to charge CHOLD. This calculation is based on
analog input model is shown in Figure 11-5. The source the following system assumptions:
impedance (RS) and the internal sampling switch (RSS)
CHOLD = 25 pF
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS) RS = 2.5 kΩ
impedance varies over the device voltage (VDD), see 1/4 LSb error
Figure 11-5. The maximum recommended imped-
VDD = 5V → RSS = 10 kΩ (worst case)
ance for analog sources is 2.5 kΩ. After the analog
input channel is selected (changed) this sampling must Temp (system Max.) = 50°C
be done before the conversion can be started.
To calculate the minimum sampling time, Equation 11-
Note 1: The reference voltage (VREF) has no
2 may be used. This equation assumes that 1/4 LSb
effect on the equation, since it cancels
error is used (16384 steps for the A/D). The 1/4 LSb
itself out.
error is the maximum error allowed for the A/D to meet
its specified resolution. 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
The CHOLD is assumed to be 25 pF for the 12-bit
A/D. 3: The maximum recommended impedance
for analog sources is 2.5 kΩ. This is
required to meet the pin leakage specifi-
cation.

 2002 Microchip Technology Inc. DS41120B-page 113

PIC16C717/770/771
EXAMPLE 11-3: CALCULATING THE
MINIMUM
REQUIRED SAMPLE TIME
TACQ = Amplifier Settling Time
+ Holding Capacitor Charging Time
+Temperature offset †
TACQ = 5 µs
+ TC
+ [(Temp - 25°C)(0.05 µs/°C)] †

TC = Holding Capacitor Charging Time

TC = (CHOLD) (RIC + RSS + RS) In (1/16384)
TC = -25 pF (1 kΩ +10 kΩ + 2.5 kΩ) In (1/16384)
TC = -25 pF (13.5 kΩ) In (1/16384)
TC = -0.338 (-9.704)µs
TC = 3.3 µs

TACQ = 5 µs
+ 3.3 µs
+ [(50°C - 25°C)(0.05 µs / °C)]

TACQ = 8.3 µs + 1.25 µs

TACQ = 9.55 µs

† The temperature coefficient is only required for

temperatures > 25°C.

FIGURE 11-5: ANALOG INPUT MODEL

VDD
Sampling
Switch
Vt = 0.6V
RS Port Pin RIC ~ 1k SS RSS

VA CPIN ILEAKAGE CHOLD = 25 pF

5 pF VT = 0.6V ± 100 nA

VSS

Legend CPIN = input capacitance

6V
VT = threshold voltage 5V
ILEAKAGE = leakage current at the pin due to VDD 4V
various junctions 3V
RIC = interconnect resistance 2V
SS = sampling switch
CHOLD = sample/hold capacitance 5 6 7 8 9 10 11
Sampling Switch (RSS)
( kΩ )

DS41120B-page 114  2002 Microchip Technology Inc.

 PIC16C717/770/771
11.7 Use of the ECCP Trigger 11.9 Faster Conversion - Lower
An A/D conversion can be started by the “special
Resolution Trade-off
event trigger” of the CCP module. This requires that Not all applications require a result with 12 bits of reso-
the CCP1M<3:0> bits be programmed as 1011b and lution, but may instead require a faster conversion
that the A/D module is enabled (ADON is set). When time. The A/D module allows users to make the trade-
the trigger occurs, the GO/DONE bit will be set on Q2 off of conversion speed to resolution. Regardless of
to start the A/D conversion and the Timer1 counter will the resolution required, the acquisition time is the
be reset to zero. Timer1 is RESET to automatically same. To speed up the conversion, the A/D module
repeat the A/D conversion cycle, with minimal soft- may be halted by clearing the GO/DONE bit after the
ware overhead (moving the ADRESH and ADRESL to desired number of bits in the result have been con-
the desired location). The appropriate analog input verted. Once the GO/DONE bit has been cleared, all
channel must be selected before the “special event of the remaining A/D result bits are ‘0’. The equation
trigger” sets the GO/DONE bit (starts a conversion to determine the time before the GO/DONE bit can be
cycle). switched is as follows:
If the A/D module is not enabled (ADON is cleared), Conversion time = (N+1)TAD
then the “special event trigger” will be ignored by the
Where: N = number of bits of resolution required,
A/D module, but will still RESET the Timer1 counter.
and 1TAD is the amplifier settling time.
11.8 Effects of a RESET Since TAD is based from the device oscillator, the user
must use some method (a timer, software loop, etc.) to
A device RESET forces all registers to their RESET determine when the A/D GO/DONE bit may be
state. This forces the A/D module to be turned off, and cleared. Table 11-4 shows a comparison of time
any conversion is aborted. The value that is in the required for a conversion with 4 bits of resolution, ver-
ADRESH and ADRESL registers are not modified. sus the normal 12-bit resolution conversion. The
The ADRESH and ADRESL registers will contain example is for devices operating at 20 MHz. The A/D
unknown data after a Power-on Reset. clock is programmed for 32 TOSC.

EXAMPLE 11-4: 4-BIT vs. 12-BIT

CONVERSION TIME
Example
4-Bit Example:
Conversion Time = (N + 1) TAD
= (4 + 1) TAD
= (5)(1.6 µS)
= 8 µS
12-Bit Example:
Conversion Time = (N + 1) TAD
= (12 + 1) TAD
= (13)(1.6 µS)
= 20.8 µS

 2002 Microchip Technology Inc. DS41120B-page 115

PIC16C717/770/771
11.10 A/D Operation During SLEEP Turning off the A/D places the A/D module in its lowest
current consumption state.
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be configured for RC Note: For the A/D module to operate in SLEEP,
(ADCS<1:0> = 11b). With the RC clock source the A/D clock source must be configured to
selected, when the GO/DONE bit is set the A/D module RC (ADCS<1:0> = 11).
waits one instruction cycle before starting the conver-
sion cycle. This allows the SLEEP instruction to be exe- 11.11 Connection Considerations
cuted, which eliminates all digital switching noise Since the analog inputs employ ESD protection, they
during the sample and conversion. When the conver- have diodes to VDD and VSS. This requires that the
sion cycle is completed the GO/DONE bit is cleared, analog input must be between VDD and VSS. If the input
and the result loaded into the ADRESH and ADRESL voltage exceeds this range by greater than 0.3V (either
registers. If the A/D interrupt is enabled, the device will direction), one of the diodes becomes forward biased
wake-up from SLEEP. If the A/D interrupt is not and it may damage the device if the input current spec-
enabled, the A/D module will then be turned off, ification is exceeded.
although the ADON bit will remain set.
An external RC filter is sometimes added for anti-alias-
When the A/D clock source is another clock option (not ing of the input signal. The R component should be
RC), a SLEEP instruction causes the present conver- selected to ensure that the total source impedance is
sion to be aborted and the A/D module is turned off, kept under the 2.5 kΩ recommended specification. It is
though the ADON bit will remain set. recommended that any external components con-
nected to an analog input pin (capacitor, zener diode,
etc.) have very little leakage current.
TABLE 11-2: SUMMARY OF A/D REGISTERS

Value on: Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
0Bh,8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ----
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 0000 ----
05h PORTA PORTA Data Latch when written: PORTA pins when read 000x 0000 000u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx11 uuuu uu11
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
17h CCP1CON — — — — 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used for A/D conversion.

DS41120B-page 116  2002 Microchip Technology Inc.

 PIC16C717/770/771
12.0 SPECIAL FEATURES OF THE 12.1 Configuration Bits
CPU The configuration bits can be programmed (read as '0')
These devices have a host of features intended to max- or left unprogrammed (read as '1') to select various
imize system reliability, minimize cost through elimina- device configurations. These bits are mapped in pro-
tion of external components, provide power saving gram memory location 2007h.
operating modes and offer code protection. These are: The user will note that address 2007h is beyond the
• Oscillator Selection user program memory space.
• RESET Some of the core features provided may not be neces-
- Power-on Reset (POR) sary to each application that a device may be used for.
- Power-up Timer (PWRT) The configuration word bits allow these features to be
configured/enabled/disabled as necessary. These fea-
- Oscillator Start-up Timer (OST)
tures include code protection, Brown-out Reset and its
- Brown-out Reset (BOR) trip point, the Power-up Timer, the watchdog timer and
• Interrupts the devices Oscillator mode. As can be seen in
• Watchdog Timer (WDT) Register 12-1, some additional configuration word bits
• Low-voltage detection have been provided for Brown-out Reset trip point
selection.
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming (ICSP)
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up
type RESETS only (POR, BOR), designed to keep the
part in RESET while the power supply stabilizes. With
these two timers on-chip, most applications need no
external RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up, or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The INTRC and ER oscillator options
save system cost while the LP crystal option saves
power. A set of configuration bits are used to select var-
ious options.
Additional information on special features is available
in the PICmicro™ Mid-Range MCU Family Reference
Manual, (DS33023).

 2002 Microchip Technology Inc. DS41120B-page 117

PIC16C717/770/771
REGISTER 12-1: CONFIGURATION WORD FOR 16C717/770/771 DEVICE

CP CP BORV1 BORV0 CP CP — BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

bit13 bit0

bit 13-12, CP: Program Memory Code Protection

9-8 1 = Code protection off
0 = All program memory is protected(2)
bit 11-10: BORV<1:0>: Brown-out Reset Voltage bits
00 = VBOR set to 4.5V
01 = VBOR set to 4.2V
10 = VBOR set to 2.7V
11 = VBOR set to 2.5V
bit 7: Unimplemented: Read as '1'
bit 6: BODEN: Brown-out Detect Reset Enable bit(1)
1 = Brown-out Detect Reset enabled
0 = Brown-out Detect Reset disabled
bit 5: MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4: PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0: FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator: Crystal/Resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/Resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
010 = HS oscillator: Crystal/Resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN function on RA7/OSC1/CLKIN
100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
110 = ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP bits must be given the same value to enable code protection.

Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

DS41120B-page 118  2002 Microchip Technology Inc.

 PIC16C717/770/771
12.2 Oscillator Configurations TABLE 12-1: CERAMIC RESONATORS

12.2.1 OSCILLATOR TYPES Ranges Tested:

The PIC16C717/770/771 can be operated in eight dif- Mode Freq OSC1 OSC2
ferent Oscillator modes. The user can program three XT 455 kHz 68 - 100 pF 68 - 100 pF
configuration bits (FOSC<2:0>) to select one of these 2.0 MHz 15 - 68 pF 15 - 68 pF
eight modes: 4.0 MHz 15 - 68 pF 15 - 68 pF
• LP Low Power Crystal HS 8.0 MHz 10 - 68 pF 10 - 68 pF
• XT Crystal/Resonator 16.0 MHz 10 - 22 pF 10 - 22 pF
• HS High Speed Crystal/Resonator These values are for design guidance only. See
notes at bottom of page.
• ER External Resistor (with and without
CLKOUT) All resonators used did not have built-in capacitors.

• INTRC Internal 4 MHz (with and without

CLKOUT) TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
• EC External Clock
Crystal Cap. Range Cap. Range
12.2.2 LP, XT AND HS MODES Osc Type
Freq C1 C2
In LP, XT or HS modes, a crystal or ceramic resonator LP 32 kHz 33 pF 33 pF
is connected to the OSC1/CLKIN and OSC2/CLKOUT 200 kHz 15 pF 15 pF
pins to establish oscillation (Figure 12-1). The
XT 200 kHz 47-68 pF 47-68 pF
PIC16C717/770/771 oscillator design requires the use
of a parallel cut crystal. Use of a series cut crystal may 1 MHz 15 pF 15 pF
give a frequency out of the crystal manufacturers spec- 4 MHz 15 pF 15 pF
ifications. HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
FIGURE 12-1: CRYSTAL/CERAMIC 20 MHz 15-33 pF 15-33 pF
RESONATOR OPERATION These values are for design guidance only. See
(HS, XT OR LP notes at bottom of page.
OSC CONFIGURATION)
C1(1) OSC1
Note 1: Since each resonator/crystal has its own
To characteristics, the user should consult the
internal resonator/crystal manufacturer for appropri-
XTAL logic
RF(3) ate values of external components.
OSC2 2: Higher capacitance increases the stability of
SLEEP
RS(2) oscillator but also increases the start-up
C2(1) PIC16C717/770/771 time.

Note1: See Table 12-1 and Table 12-2 for recom- 12.2.3 EC MODE
mended values of C1 and C2.
In applications where the clock source is external, the
2: A series resistor (RS) may be required for
PIC16C717/770/771 should be programmed to select
AT strip cut crystals.
the EC (External Clock) mode. In this mode, the RA6/
3: RF varies with the Crystal mode chosen.
OSC2/CLKOUT pin is available as an I/O pin. See
Figure 12-2 for illustration.

FIGURE 12-2: EXTERNAL CLOCK INPUT

OPERATION (EC OSC
CONFIGURATION)

Clock from OSC1

ext. system PIC16C717/770/771
I/O RA6

 2002 Microchip Technology Inc. DS41120B-page 119

PIC16C717/770/771
12.2.4 ER MODE 12.2.6 CLKOUT

For timing insensitive applications, the ER (External In the INTRC and ER modes, the PIC16C717/770/771
Resistor) Clock mode offers additional cost savings. can be configured to provide a clock out signal by pro-
Only one external component, a resistor connected to gramming the configuration word. The oscillator fre-
the OSC1 pin and VSS, is needed to set the operating quency, divided by 4, can be used for test purposes or
frequency of the internal oscillator. The resistor draws to synchronize other logic.
a DC bias current which controls the oscillation fre-
In the INTRC and ER modes, if the CLKOUT output is
quency. In addition to the resistance value, the oscilla-
enabled, CLKOUT is held low during RESET.
tor frequency will vary from unit to unit, and as a
function of supply voltage and temperature. Since the 12.2.7 DUAL SPEED OPERATION FOR ER
controlling parameter is a DC current and not a capac-
AND INTRC MODES
itance, the particular package type and lead frame will
not have a significant effect on the resultant frequency. A software programmable dual speed oscillator is avail-
Figure 12-3 shows how the controlling resistor is con- able in either ER or INTRC Oscillator modes. This fea-
nected to the PIC16C717/770/771. For REXT values ture allows the applications to dynamically toggle the
below 38 kΩ, the oscillator operation may become oscillator speed between normal and slow frequencies.
unstable, or stop completely. For very high REXT values The nominal slow frequency is 37 kHz. In ER mode, the
(e.g. 1M), the oscillator becomes sensitive to noise, slow speed operation is fixed and does not vary with
humidity and leakage. Thus, we recommend keeping resistor size. Applications that require low current
REXT between 38 kΩ and 1 MΩ. power savings, but cannot tolerate putting the part into
SLEEP, may use this mode.
FIGURE 12-3: EXTERNAL RESISTOR The OSCF bit in the PCON register is used to control
Dual Speed mode. See the PCON Register,
Register 2-8, for details.
PIC16C717/770/771
When changing the INTRC or ER internal oscillator
RA6/OSC2/CLKOUT speed, there is a period of time when the processor is
inactive. When the speed changes from fast to slow,
the processor inactive period is in the range of 100 µS
RA7/OSC1/CLKIN to 300 µS. For speed change from slow to fast, the pro-
cessor is in active for 1.25 µS to 3.25 µS.
REXT

The Electrical Specification section shows the relation-

ship between the REXT resistance value and the oper-
ating frequency as well as frequency variations due to
operating temperature for given REXT and VDD values.
The ER Oscillator mode has two options that control
the OSC2 pin. The first allows it to be used as a general
purpose I/O port. The other configures the pin as CLK-
OUT. The ER oscillator does not run during RESET.

12.2.5 INTRC MODE

The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C, see “Electri-
cal Specifications” section for information on variation
over voltage and temperature. The INTRC oscillator
does not run during RESET.

DS41120B-page 120  2002 Microchip Technology Inc.

 PIC16C717/770/771
12.3 RESET Some registers are not affected in any RESET condi-
tion. Their status is unknown on a Power-up Reset and
The PIC16C717/770/771 devices have several differ- unchanged in any other RESET. Most other registers
ent RESETS. These RESETS are grouped into two are placed into an initialized state upon RESET, how-
classifications; power-up and non-power-up. The ever they are not affected by a WDT Reset during
power-up type RESETS are the Power-on and Brown- SLEEP, because this is considered a WDT Wake-up,
out Resets which assume the device VDD was below its which is viewed as the resumption of normal operation.
normal operating range for the device’s configuration.
The non power-up type RESETS assume normal oper- Several status bits have been provided to indicate
ating limits were maintained before/during and after the which RESET occurred (see Table 12-4). See
RESET. Table 12-6 for a full description of RESET states of all
registers.
• Power-on Reset (POR)
A simplified block diagram of the On-Chip Reset circuit
• Programmable Brown-out Reset (PBOR)
is shown in Figure 12-4.
• MCLR Reset during normal operation
These devices have a MCLR noise filter in the MCLR
• MCLR Reset during SLEEP
Reset path. The filter will detect and ignore small
• WDT Reset (during normal operation) pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.

FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External
RESET

MCLR
SLEEP
WDT Time-out
Module

VDD rise Power-on Reset

detect
VDD
Programmable
BODEN S
Brown-out

OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q

OSC1

PWRT
Dedicated
Oscillator 10-bit Ripple counter

Enable PWRT

Enable OST

 2002 Microchip Technology Inc. DS41120B-page 121

PIC16C717/770/771
12.4 Power-On Reset (POR) 12.5 Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when a The Power-up Timer provides a fixed TPWRT time-out
VDD rise is detected (in the range of 1.5V - 2.1V). on power-up type RESETS only. For a POR, the PWRT
Enable the internal MCLR feature to eliminate external is invoked when the POR pulse is generated. For a
RC components usually needed to create a Power-on BOR, the PWRT is invoked when the device exits the
Reset. A maximum rise time for VDD is specified. See RESET condition (VDD rises above BOR trip point).
Electrical Specifications for details. For a long rise time, The Power-up Timer operates on an internal RC oscil-
enable external MCLR function and use circuit as lator. The chip is kept in RESET as long as the PWRT
shown in Figure 12-5. is active. The PWRT’s time delay is designed to allow
Two delay timers, (PWRT on OST), have been pro- VDD to rise to an acceptable level. A configuration bit is
vided which hold the device in RESET after a POR provided to enable/disable the PWRT for the POR only.
(dependent upon device configuration) so that all oper- For a BOR the PWRT is always available regardless of
ational parameters have been met prior to releasing the the configuration bit setting.
device to resume/begin normal operation. The power-up time delay will vary from chip-to-chip due
When the device starts normal operation (exits the to VDD, temperature and process variation. See DC
RESET condition), device operating parameters (volt- parameters for details.
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
12.6 Oscillator Start-up Timer (OST)
must be held in RESET until the operating conditions The Oscillator Start-up Timer (OST) provides 1024
are met. Brown-out Reset may be used to meet the oscillator cycle (from OSC1 input) delay after the
start-up conditions, or if necessary an external POR cir- PWRT delay is over. This ensures that the crystal oscil-
cuit may be implemented to delay end of RESET for as lator or resonator has started and stabilized.
long as needed.
The OST time-out is invoked only for XT, LP and HS
modes and only on a power-up type RESET or a wake-
FIGURE 12-5: EXTERNAL POWER-ON up from SLEEP.
RESET CIRCUIT (FOR
SLOW VDD RAMP) 12.7 Programmable Brown-Out Reset
(PBOR)
VDD VDD
The Programmable Brown-out Reset module is used to
generate a RESET when the supply voltage falls below
D R a specified trip voltage. The trip voltage is configurable
R1 to any one of four voltages provided by the BORV<1:0>
MCLR
configuration word bits.
C PIC16C717/770/771
Configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below the specified trip point for
Note 1: External Power-on Reset circuit is longer than TBOR, (parameter #35), the brown-out situ-
required only if VDD power-up slope is too ation will RESET the chip. A RESET may not occur if
slow. The diode D helps discharge the VDD falls below the trip point for less than TBOR. The
capacitor quickly when VDD powers down. chip will remain in Brown-out Reset until VDD rises
2: R < 40 kΩ is recommended to make sure above VBOR. The Power-up Timer will be invoked at
that voltage drop across R does not violate that point and will keep the chip in RESET an additional
the device’s electrical specification. TPWRT. If VDD drops below VBOR while the Power-up
Timer is running, the chip will go back into a Brown-out
3: R1 = 100Ω to 1 kΩ will limit any current
Reset and the Power-up Timer will be re-initialized.
flowing into MCLR from external capacitor
Once VDD rises above VBOR, the Power-up Timer will
C in the event of MCLR/VPP pin break-
again begin a TPWRT time delay. Even though the
down due to Electrostatic Discharge
PWRT is always enabled when brown-out is enabled,
(ESD) or Electrical Overstress (EOS).
the PWRT configuration word bit should be cleared
4: External MCLR must be enabled
(enabled) when brown-out is enabled.
(MCLRE = 1).

DS41120B-page 122  2002 Microchip Technology Inc.

 PIC16C717/770/771
12.8 Time-out Sequence Table 12-5 shows the RESET conditions for some spe-
cial function registers, while Table 12-6 shows the
On power-up, the time-out sequence is as follows: RESET conditions for all the registers.
First PWRT time-out is invoked by the POR pulse.
When the PWRT delay expires, the Oscillator Start-up 12.9 Power Control/STATUS Register
Timer is activated. The total time-out will vary based on (PCON)
oscillator configuration and the status of the PWRT.
For example, in RC mode with the PWRT disabled, The Power Control/STATUS Register, PCON, has two
there will be no time-out at all. Figure 12-6, Figure 12- status bits that provide indication of which power-up
7, Figure 12-8 and Figure 12-9 depict time-out type RESET occurred.
sequences on power-up. Bit0 is Brown-out Reset Status bit, BOR. The BOR bit
Since the time-outs occur from the POR pulse, if MCLR is unknown upon a POR. BOR must be set by the user
is kept low long enough, the time-outs will expire. Then and checked on subsequent RESETS to see if bit BOR
bringing MCLR high will begin execution immediately cleared, indicating a BOR occurred.
(Figure 12-8). This is useful for testing purposes or to Bit1 is POR (Power-on Reset Status bit). It is cleared on
synchronize more than one PICmicro® microcontroller a Power-on Reset and unaffected otherwise. The user
operating in parallel. must set this bit following a Power-on Reset.

TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS

Power-up Wake-up from
Oscillator Configuration Brown-out SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP TPWRT + 1024TOSC 1024TOSC TPWRT + 1024TOSC 1024TOSC
EC, ER, INTRC TPWRT — TPWRT —

TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE

POR BOR TO PD
0 x 1 1 Power-on Reset
0 x 0 x Illegal, TO is set on POR
0 x x 0 Illegal, PD is set on POR
1 0 1 1 Brown-out Reset
1 1 0 1 WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP

TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS

Condition Program STATUS PCON

Counter Register Register
Power-on Reset 000h 0001 1xxx ---- 1-0x
MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- 1-uu
WDT Reset 000h 0000 1uuu ---- 1-uu
WDT Wake-up PC + 1 uuu0 0uuu ---- u-uu
Brown-out Reset 000h 0001 1uuu ---- 1-u0
Interrupt wake-up from SLEEP, GIE = 0 PC + 1 uuu1 0uuu ---- u-uu
Interrupt wake-up from SLEEP, GIE = 1 0004h uuu1 0uuu ---- u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.

 2002 Microchip Technology Inc. DS41120B-page 123

PIC16C717/770/771
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Power-on Reset or MCLR Reset or Wake-up via WDT or
Brown-out Reset WDT Reset Interrupt
W xxxx xxxx uuuu uuuu uuuu uuuu
INDF 0000 0000 uuuu uuuu uuuu uuuu
TMR0 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 0000h 0000h PC + 1(1)
STATUS 0001 1xxx 000q quuu(2) uuuq quuu(2)
FSR xxxx xxxx uuuu uuuu uuuu uuuu
PORTA xxxx 0000 uuuu 0000 uuuu uuuu
PORTB xxxx xx11 uuuu uu11 uuuu uuuu
PCLATH ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000x 0000 000u uuuu uuqq
PIR1 -0-- 0000 -0-- 0000 -0-- uuuu
PIR2 0--- 0--- 0--- 0--- q--- q---
TMR1L xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H xxxx xxxx uuuu uuuu uuuu uuuu
T1CON --00 0000 --uu uuuu --uu uuuu
TMR2 0000 0000 0000 0000 uuuu uuuu
T2CON -000 0000 -000 0000 -uuu uuuu
SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 0000 0000 0000 0000 uuuu uuuu
CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 0000 0000 0000 0000 uuuu uuuu
ADRESH xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 0000 0000 0000 0000 uuuu uuuu
OPTION_REG 1111 1111 1111 1111 uuuu uuuu
TRISA 1111 1111 1111 1111 uuuu uuuu
TRISB 1111 1111 1111 1111 uuuu uuuu
PIE1 -0-- 0000 -0-- 0000 -u-- uuuu
PIE2 0--- 0--- 0--- 0--- u--- u---
PCON ---- 1-qq ---- 1-uu ---- u-uu
PR2 1111 1111 1111 1111 1111 1111
SSPADD 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 0000 0000 0000 0000 uuuu uuuu
WPUB 1111 1111 1111 1111 uuuu uuuu
IOCB 1111 0000 1111 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2: See Table 12-5 for RESET value for specific condition.

DS41120B-page 124  2002 Microchip Technology Inc.

 PIC16C717/770/771
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Power-on Reset or MCLR Reset or Wake-up via WDT or
Brown-out Reset WDT Reset Interrupt
P1DEL 0000 0000 0000 0000 uuuu uuuu
REFCON 0000 ---- 0000 ---- uuuu ----
LVDCON --00 0101 --00 0101 --uu uuuu
ANSEL --11 1111 --11 1111 --uu uuuu
ADRESL xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 0000 0000 0000 0000 uuuu uuuu
PMDATL xxxx xxxx uuuu uuuu uuuu uuuu
PMADRL xxxx xxxx uuuu uuuu uuuu uuuu
PMDATH --xx xxxx --uu uuuu --uu uuuu
PMADRH ---- xxxx ---- uuuu ---- uuuu
PMCON1 1--- ---0 1--- ---0 1--- ---0
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2: See Table 12-5 for RESET value for specific condition.

FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST

OST TIME-OUT

INTERNAL RESET

 2002 Microchip Technology Inc. DS41120B-page 125

PIC16C717/770/771
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 12-9: SLOW VDD RISE TIME (MCLR TIED TO VDD)

5V
VDD 0V

MCLR

INTERNAL POR

TPWRT (1)

PWRT TIME-OUT
TOST

OST TIME-OUT

INTERNAL RESET

Note 1: Time dependent on oscillator circuit

DS41120B-page 126  2002 Microchip Technology Inc.

 PIC16C717/770/771
12.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
The devices have up to 11 sources of interrupt. The the INTCON register.
interrupt control register (INTCON) records individual
interrupt requests in flag bits. It also has individual and The peripheral interrupt flags are contained in the spe-
global interrupt enable bits. cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
Note: Individual interrupt flag bits are set regard- function registers PIE1 and PIE2, and the peripheral
less of the status of their corresponding interrupt enable bit is contained in special function reg-
mask bit or the GIE bit. ister INTCON.
A Global Interrupt Enable bit, GIE (INTCON<7>), When an interrupt is responded to, the GIE bit is
enables (if set) all un-masked interrupts or disables (if cleared to disable any further interrupt, the return
cleared) all interrupts. When bit GIE is enabled and an address is pushed onto the stack and the PC is loaded
interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the interrupt service routine the
vector immediately. Individual interrupts can be dis- source(s) of the interrupt can be determined by polling
abled through their corresponding enable bits in vari- the interrupt flag bits. The interrupt flag bit(s) must be
ous registers. Individual interrupt bits are set, cleared in software before re-enabling interrupts to
regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts.
cleared on RESET.
For external interrupt events, such as the INT pin or
The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be
the interrupt routine as well as sets the GIE bit, which three or four instruction cycles. The exact latency
re-enables interrupts. depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit

FIGURE 12-10: INTERRUPT LOGIC

LVDIF
LVDIE

Wake-up (If in SLEEP mode)

ADIF T0IF
ADIE T0IE
INTF
INTE Interrupt to CPU
RBIF
RBIE
SSPIF
SSPIE PEIE
CCP1IF
CCP1IE GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE

BCLIF
BCLIE

 2002 Microchip Technology Inc. DS41120B-page 127

PIC16C717/770/771
12.10.1 INT INTERRUPT 12.11 Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered: During an interrupt, only the PC is saved on the stack.
either rising if bit INTEDG (OPTION_REG<6>) is set, At the very least, W and STATUS should be saved to
or falling, if the INTEDG bit is clear. When a valid edge preserve the context for the interrupted program. All
appears on the RB0/INT pin, flag bit INTF registers that may be corrupted by the ISR, such as
(INTCON<1>) is set. This interrupt can be disabled by PCLATH or FSR, should be saved.
clearing enable bit INTE (INTCON<4>). Flag bit INTF
Example 12-1 stores and restores the STATUS, W and
must be cleared in software in the interrupt service rou-
PCLATH registers. The register, W_TEMP, is defined in
tine before re-enabling this interrupt. The INT interrupt
Common RAM, the last 16 bytes of each bank that may
can wake-up the processor from SLEEP, if bit INTE was
be accessed from any bank. The STATUS_TEMP and
set prior to going into SLEEP. The status of global inter-
PCLATH_TEMP are defined in bank 0.
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up. The example:
See Section 12.13 for details on SLEEP mode. a) Stores the W register.
b) Stores the STATUS register in bank 0.
12.10.2 TMR0 INTERRUPT
c) Stores the PCLATH register in bank 0.
An overflow (FFh → 00h) in the TMR0 register will set d) Executes the ISR code.
flag bit T0IF (INTCON<2>). The interrupt can be
e) Restores the PCLATH register.
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 2.2.2.3) f) Restores the STATUS register
g) Restores W.
12.10.3 PORTB INTCON CHANGE Note that W_TEMP, STATUS_TEMP and
An input change on PORTB<7:0> sets flag bit RBIF PCLATH_TEMP are defined in the common RAM area
(INTCON<0>). The PORTB pin(s) which can individu- (70h - 7Fh) to avoid register bank switching during con-
ally generate interrupt is selectable in the IOCB regis- text save and restore.
ter. The interrupt can be enabled/disabled by setting/
clearing enable bit RBIE (INTCON<4>).
(Section 2.2.2.3)

EXAMPLE 12-1: Saving STATUS, W, and PCLATH Registers in RAM

#define W_TEMP 0x70
#define STATUS_TEMP 0x71
#define PCLATH_TEMP 0x72
org 0x04 ; start at Interrupt Vector
MOVWF W_TEMP ; Save W register
MOVF STATUS,w
MOVWF STATUS_TEMP ; save STATUS
MOVF PCLATH,w
MOVWF PCLATH_TEMP ; save PCLATH
:
(Interrupt Service Routine)
:
MOVF PCLATH_TEMP,w
MOVWF PCLATH
MOVF STATUS_TEMP,w
MOVWF STATUS
SWAPF W_TEMP,f ;
SWAPF W_TEMP,w ; swapf loads W without affecting STATUS flags
RETFIE

DS41120B-page 128  2002 Microchip Technology Inc.

 PIC16C717/770/771
12.12 Watchdog Timer (WDT) wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
The Watchdog Timer is a free running on-chip RC oscil- ter will be cleared upon a Watchdog Timer time-out.
lator, which does not require any external components.
This oscillator is independent from the processor clock. The WDT can be permanently disabled by program-
If enabled, the WDT will run even if the main clock of ming the configuration bit WDTE to ’0’ (Section 12.1).
the device has been stopped, for example, by execu- WDT time-out period values may be found in Table 15-
tion of a SLEEP instruction. 4. Values for the WDT prescaler may be assigned using
During normal operation, a WDT time-out generates a the OPTION_REG register.
device RESET (Watchdog Timer Reset). If the device is Note: The SLEEP instruction clears the WDT and
in SLEEP mode, a WDT time-out causes the device to the postscaler, if assigned to the WDT,
restarting the WDT period.

FIGURE 12-11: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source
(Figure 5-2)

0
M Postscaler
1 U
WDT Timer X
8

8 - to - 1 MUX PS<2:0>(1)
PSA
WDT
Enable Bit(2)
To TMR0 (Figure 5-2)

0 1

MUX PSA(1)

WDT
Note 1: PSA and PS<2:0> are bits in the OPTION_REG register. Time-out
2: WDTE bit in the configuration word.

TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Config. bits(1) — BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for the full description of the configuration word bits.

 2002 Microchip Technology Inc. DS41120B-page 129

PIC16C717/770/771
12.13 Power-down Mode (SLEEP) clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
Power-down mode is entered by executing a SLEEP set (enabled), the device executes the instruction after
instruction. the SLEEP instruction and then branches to the inter-
If enabled, the Watchdog Timer will be cleared but rupt address (0004h). In cases where the execution of
keeps running, the PD bit (STATUS<3>) is cleared, the the instruction following SLEEP is not desirable, the
TO (STATUS<4>) bit is set, and the oscillator driver is user should have a NOP after the SLEEP instruction.
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving 12.13.2 WAKE-UP USING INTERRUPTS
high, low, or hi-impedance). When global interrupts are disabled (GIE cleared) and
For lowest current consumption in this mode, place all any interrupt source has both its interrupt enable bit
I/O pins at either VDD, or VSS, ensure no external cir- and interrupt flag bit set, one of the following will occur:
cuitry is drawing current from the I/O pin, power-down • If the interrupt occurs before the execution of a
the A/D, disable external clocks. Pull all I/O pins, that SLEEP instruction, the SLEEP instruction will com-
are hi-impedance inputs, high or low externally to avoid plete as a NOP. Therefore, the WDT and WDT
switching currents caused by floating inputs. The postscaler will not be cleared, the TO bit will not
T0CKI input should also be at VDD or VSS for lowest be set and PD bits will not be cleared.
current consumption. The contribution from on-chip
• If the interrupt occurs during or after the execu-
pull-ups on PORTB should be considered.
tion of a SLEEP instruction, the device will imme-
12.13.1 WAKE-UP FROM SLEEP diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
The device can wake-up from SLEEP through one of wake-up. Therefore, the WDT and WDT
the following events: postscaler will be cleared, the TO bit will be set
1. External RESET input on MCLR pin. and the PD bit will be cleared.
2. Watchdog Timer Wake-up (if WDT was Even if the flag bits were checked before executing a
enabled). SLEEP instruction, it may be possible for flag bits to
3. Interrupt from INT pin, RB port change, or some become set before the SLEEP instruction completes. To
Peripheral Interrupts. determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
External MCLR Reset will cause a device RESET. All was executed as a NOP.
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits If a peripheral can wake the device from SLEEP, then
in the STATUS register can be used to determine the to ensure that the WDT is cleared, a CLRWDT instruc-
cause of device RESET. The PD bit, which is set on tion should be executed before a SLEEP instruction.
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. CCP Capture mode interrupt.
3. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
4. SSP (START/STOP) bit detect interrupt.
5. SSP transmit or receive in Slave mode
(SPI/I2C).
6. A/D conversion (when A/D clock source is RC).
7. Low Voltage detect.
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is

DS41120B-page 130  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 12-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1

CLKOUT(3) TOST(1)

INT pin
INTF flag
(INTCON<1>)

GIE bit Interrupt Latency(2)

Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction
fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Instruction SLEEP Inst(PC + 1) Dummy cycle Dummy cycle
Inst(PC - 1) Inst(0004h)
executed

Note 1: TOST = 1024TOSC (drawing not to scale) This delay applies to LP, XT and HS modes only.
2: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
3: CLKOUT is not available in these osc modes, but shown here for timing reference.

12.14 Program Verification/Code 12.16 In-Circuit Serial Programming

Protection (ICSP™)
If the code protection bit(s) have not been pro- PIC16CXXX microcontrollers can be serially pro-
grammed, the on-chip program memory can be read grammed while in the end application circuit. This is
out for verification purposes. simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
Note: Microchip does not recommend code pro-
voltage. This allows customers to manufacture boards
tecting windowed devices. Code protected
with unprogrammed devices, and then program the
devices are not reprogrammable.
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
12.15 ID Locations
ware to be programmed.
Four memory locations (2000h - 2003h) are designated For complete details of serial programming, please
as ID locations where the user can store checksum or refer to the In-Circuit Serial Programming (ICSP™)
other code-identification numbers. These locations are Guide, (DS30277).
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.

 2002 Microchip Technology Inc. DS41120B-page 131

PIC16C717/770/771
NOTES:

DS41120B-page 132  2002 Microchip Technology Inc.

 PIC16C717/770/771
13.0 INSTRUCTION SET SUMMARY Table 13-2 lists the instructions recognized by the
MPASM™ assembler.
Each PIC16CXXX instruction is a 14-bit word divided
Figure 13-1 shows the general formats that the instruc-
into an OPCODE which specifies the instruction type
tions can have.
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction Note: To maintain upward compatibility with
set summary in Table 13-2 lists byte-oriented, bit-ori- future PIC16CXXX products, do not use
ented, and literal and control operations. Table 13-1 the OPTION and TRIS instructions.
shows the opcode field descriptions.
All examples use the following format to represent a
For byte-oriented instructions, ’f’ represents a file reg- hexadecimal number:
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file 0xhh
register is to be used by the instruction. where h signifies a hexadecimal digit.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is FIGURE 13-1: GENERAL FORMAT FOR
placed in the W register. If ’d’ is one, the result is placed INSTRUCTIONS
in the file register specified in the instruction. Byte-oriented file register operations
For bit-oriented instructions, ’b’ represents a bit field 13 8 7 6 0
designator which selects the number of the bit affected OPCODE d f (FILE #)
by the operation, while ’f’ represents the number of the d = 0 for destination W
file in which the bit is located. d = 1 for destination f
f = 7-bit file register address
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
Bit-oriented file register operations
13 10 9 7 6 0
TABLE 13-1: OPCODE FIELD OPCODE b (BIT #) f (FILE #)
DESCRIPTIONS
b = 3-bit bit address
Field Description f = 7-bit file register address
f Register file address (0x00 to 0x7F)
W Working register (accumulator) Literal and control operations
b Bit address within an 8-bit file register
General
k Literal field, constant data or label
13 8 7 0
x Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the OPCODE k (literal)
recommended form of use for compatibility with all k = 8-bit immediate value
Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f. CALL and GOTO instructions only
Default is d = 1 13 11 10 0
PC Program Counter OPCODE k (literal)
TO Time-out bit
k = 11-bit immediate value
PD Power-down bit

The instruction set is highly orthogonal and is grouped A description of each instruction is available in the
into three basic categories: PICmicro™ Mid-Range MCU Family Reference Man-
• Byte-oriented operations ual, (DS33023).
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.

 2002 Microchip Technology Inc. DS41120B-page 133

PIC16C717/770/771
TABLE 13-2: PIC16CXXX INSTRUCTION SET
Mnemonic, Description Cycles 14-Bit Opcode Status Notes
Operands Affected
MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW - Clear W 1 00 0001 0000 0011 Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP - No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nybbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE - Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN - Return from Subroutine 2 00 0000 0000 1000
SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.

DS41120B-page 134  2002 Microchip Technology Inc.

 PIC16C717/770/771
13.1 Instruction Descriptions
ADDLW Add Literal and W ANDWF AND W with f
Syntax: [label] ADDLW k Syntax: [label] ANDWF f,d
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: (W) + k → (W) d ∈ [0,1]

Status Affected: C, DC, Z Operation: (W) .AND. (f) → (destination)

Description: The contents of the W register Status Affected: Z

are added to the eight bit literal ’k’ Description: AND the W register with register
and the result is placed in the W 'f'. If 'd' is 0, the result is stored in
register. the W register. If 'd' is 1, the result
is stored back in register 'f'.

ADDWF Add W and f BCF Bit Clear f

Syntax: [label] ADDWF f,d Syntax: [label] BCF f,b
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] 0≤b≤7
Operation: (W) + (f) → (destination) Operation: 0 → (f<b>)
Status Affected: C, DC, Z Status Affected: None
Description: Add the contents of the W register Description: Bit 'b' in register 'f' is cleared.
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.

ANDLW AND Literal with W BSF Bit Set f

Syntax: [label] ANDLW k Syntax: [label] BSF f,b
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: (W) .AND. (k) → (W) 0≤b≤7

Status Affected: Z Operation: 1 → (f<b>)

Description: The contents of W register are Status Affected: None

AND’ed with the eight bit literal Description: Bit 'b' in register 'f' is set.
'k'. The result is placed in the W
register.

 2002 Microchip Technology Inc. DS41120B-page 135

PIC16C717/770/771
BTFSS Bit Test f, Skip if Set CLRF Clear f
Syntax: [label] BTFSS f,b Syntax: [label] CLRF f
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
0≤b<7 Operation: 00h → (f)
Operation: skip if (f<b>) = 1 1→Z
Status Affected: None Status Affected: Z
Description: If bit ’b’ in register ’f’ is ’0’, the next Description: The contents of register ’f’ are
instruction is executed. cleared and the Z bit is set.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOP is exe-
cuted instead making this a 2TCY
instruction.

BTFSC Bit Test, Skip if Clear CLRW Clear W

Syntax: [label] BTFSC f,b Syntax: [ label ] CLRW
Operands: 0 ≤ f ≤ 127 Operands: None
0≤b≤7 Operation: 00h → (W)
Operation: skip if (f<b>) = 0 1→Z
Status Affected: None Status Affected: Z
Description: If bit ’b’ in register ’f’ is ’1’, the next Description: W register is cleared. Zero bit (Z)
instruction is executed. is set.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.

CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0 ≤ k ≤ 2047 Operands: None
Operation: (PC)+ 1→ TOS, Operation: 00h → WDT
k → PC<10:0>, 0 → WDT prescaler,
(PCLATH<4:3>) → PC<12:11> 1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Description: Call Subroutine. First, return
address (PC+1) is pushed onto Description: CLRWDT instruction resets the
the stack. The eleven bit immedi- Watchdog Timer. It also resets the
ate address is loaded into PC bits prescaler of the WDT. Status bits
<10:0>. The upper bits of the PC TO and PD are set.
are loaded from PCLATH. CALL is
a two cycle instruction.

DS41120B-page 136  2002 Microchip Technology Inc.

 PIC16C717/770/771
COMF Complement f GOTO Unconditional Branch
Syntax: [ label ] COMF f,d Syntax: [ label ] GOTO k
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 2047
d ∈ [0,1] Operation: k → PC<10:0>
Operation: (f) → (destination) PCLATH<4:3> → PC<12:11>
Status Affected: Z Status Affected: None
Description: The contents of register ’f’ are Description: GOTO is an unconditional branch.
complemented. If ’d’ is 0, the The eleven bit immediate value is
result is stored in W. If ’d’ is 1, the loaded into PC bits <10:0>. The
result is stored back in register ’f’. upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two
cycle instruction.

DECF Decrement f INCF Increment f

Syntax: [label] DECF f,d Syntax: [ label ] INCF f,d
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] d ∈ [0,1]
Operation: (f) - 1 → (destination) Operation: (f) + 1 → (destination)
Status Affected: Z Status Affected: Z
Description: Decrement register ’f’. If ’d’ is 0, Description: The contents of register ’f’ are
the result is stored in the W regis- incremented. If ’d’ is 0, the result
ter. If ’d’ is 1, the result is stored is placed in the W register. If ’d’ is
back in register ’f’. 1, the result is placed back in reg-
ister ’f’.

DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] d ∈ [0,1]
Operation: (f) - 1 → (destination); Operation: (f) + 1 → (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ’f’ are Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result incremented. If ’d’ is 0, the result is
is placed in the W register. If ’d’ is placed in the W register. If ’d’ is 1,
1, the result is placed back in reg- the result is placed back in regis-
ister ’f’. ter ’f’.
If the result is 1, the next instruc- If the result is 1, the next instruc-
tion is executed. If the result is 0, tion is executed. If the result is 0,
then a NOP is executed instead a NOP is executed instead making
making it a 2TCY instruction. it a 2TCY instruction.

 2002 Microchip Technology Inc. DS41120B-page 137

PIC16C717/770/771
IORLW Inclusive OR Literal with W MOVLW Move Literal to W
Syntax: [ label ] IORLW k Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W) Operation: k → (W)
Status Affected: Z Status Affected: None
Description: The contents of the W register are Description: The eight bit literal 'k' is loaded
OR’ed with the eight bit literal 'k'. into W register. The don’t cares
The result is placed in the W reg- will assemble as 0’s.
ister.

IORWF Inclusive OR W with f MOVWF Move W to f

Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) → (f)
Operation: (W) .OR. (f) → (destination)
Status Affected: None
Status Affected: Z
Description: Move data from W register to reg-
Description: Inclusive OR the W register with ister 'f'.
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.

MOVF Move f NOP No Operation

Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP
Operands: 0 ≤ f ≤ 127 Operands: None
d ∈ [0,1] Operation: No operation
Operation: (f) → (destination) Status Affected: None
Status Affected: Z Description: No operation.
Description: The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.

DS41120B-page 138  2002 Microchip Technology Inc.

 PIC16C717/770/771
RETFIE Return from Interrupt RLF Rotate Left f through Carry
Syntax: [ label ] RETFIE Syntax: [ label ] RLF f,d
Operands: None Operands: 0 ≤ f ≤ 127
Operation: TOS → PC, d ∈ [0,1]
1 → GIE Operation: See description below
Status Affected: None Status Affected: C
Description: The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
C Register f

RETLW Return with Literal in W RRF Rotate Right f through Carry

Syntax: [ label ] RETLW k Syntax: [ label ] RRF f,d
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: k → (W); d ∈ [0,1]
TOS → PC Operation: See description below
Status Affected: None Status Affected: C
Description: The W register is loaded with the Description: The contents of register ’f’ are
eight bit literal ’k’. The program rotated one bit to the right through
counter is loaded from the top of the Carry Flag. If ’d’ is 0, the result
the stack (the return address). is placed in the W register. If ’d’ is
This is a two cycle instruction. 1, the result is placed back in reg-
ister ’f’.
C Register f

RETURN Return from Subroutine SLEEP

Syntax: [ label ] RETURN Syntax: [ label SLEEP
Operands: None ]

Operation: TOS → PC Operands: None

Status Affected: None Operation: 00h → WDT,

0 → WDT prescaler,
Description: Return from subroutine. The stack 1 → TO,
is POPed and the top of the stack 0 → PD
(TOS) is loaded into the program
counter. This is a two cycle Status Affected: TO, PD
instruction. Description: The power-down status bit, PD
is cleared. Time-out status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 12.8 for more
details.

 2002 Microchip Technology Inc. DS41120B-page 139

PIC16C717/770/771
SUBLW Subtract W from Literal XORLW Exclusive OR Literal with W
Syntax: [ label ] SUBLW k Syntax: [label] XORLW k
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W) Operation: (W) .XOR. k → (W)
Status Affected: C, DC, Z Status Affected: Z
Description: The W register is subtracted (2’s Description: The contents of the W register
complement method) from the are XOR’ed with the eight bit lit-
eight bit literal 'k'. The result is eral 'k'. The result is placed in
placed in the W register. the W register.

SUBWF Subtract W from f XORWF Exclusive OR W with f

Syntax: [ label ] SUBWF f,d Syntax: [label] XORWF f,d
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] d ∈ [0,1]
Operation: (f) - (W) → (destination) Operation: (W) .XOR. (f) → (destination)
Status Affected: C, DC, Z Status Affected: Z
Description: Subtract (2’s complement method) Description: Exclusive OR the contents of the
W register from register 'f'. If 'd' is 0, W register with register 'f'. If 'd' is
the result is stored in the W regis- 0, the result is stored in the W
ter. If 'd' is 1, the result is stored register. If 'd' is 1, the result is
back in register 'f'. stored back in register 'f'.

SWAPF Swap Nybbles in f

Syntax: [ label ] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description: The upper and lower nybbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is placed in
register 'f'.

DS41120B-page 140  2002 Microchip Technology Inc.

 PIC16C717/770/771
14.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to:
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools: • One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
• Integrated Development Environment matically updates all project information)
- MPLAB® IDE Software • Debug using:
• Assemblers/Compilers/Linkers - source files
- MPASMTM Assembler - absolute listing file
- MPLAB C17 and MPLAB C18 C Compilers - machine code
- MPLINKTM Object Linker/
The ability to use MPLAB IDE with multiple debugging
MPLIBTM Object Librarian
tools allows users to easily switch from the cost-
• Simulators effective simulator to a full-featured emulator with
- MPLAB SIM Software Simulator minimal retraining.
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator 14.2 MPASM Assembler
- ICEPIC™ In-Circuit Emulator The MPASM assembler is a full-featured universal
• In-Circuit Debugger macro assembler for all PICmicro MCU’s.
- MPLAB ICD The MPASM assembler has a command line interface
• Device Programmers and a Windows shell. It can be used as a stand-alone
- PRO MATE® II Universal Device Programmer application on a Windows 3.x or greater system, or it
- PICSTART® Plus Entry-Level Development can be used through MPLAB IDE. The MPASM assem-
Programmer bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
• Low Cost Demonstration Boards
detail memory usage and symbol reference, an abso-
- PICDEMTM 1 Demonstration Board lute LST file that contains source lines and generated
- PICDEM 2 Demonstration Board machine code, and a COD file for debugging.
- PICDEM 3 Demonstration Board The MPASM assembler features include:
- PICDEM 17 Demonstration Board
• Integration into MPLAB IDE projects.
- KEELOQ® Demonstration Board
• User-defined macros to streamline assembly
code.
14.1 MPLAB Integrated Development
• Conditional assembly for multi-purpose source
Environment Software
files.
The MPLAB IDE software brings an ease of software • Directives that allow complete control over the
development previously unseen in the 8-bit microcon- assembly process.
troller market. The MPLAB IDE is a Windows®-based
application that contains: 14.3 MPLAB C17 and MPLAB C18
• An interface to debugging tools C Compilers
- simulator The MPLAB C17 and MPLAB C18 Code Development
- programmer (sold separately) Systems are complete ANSI ‘C’ compilers for
- emulator (sold separately) Microchip’s PIC17CXXX and PIC18CXXX family of
- in-circuit debugger (sold separately) microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
• A full-featured editor
found with other compilers.
• A project manager
For easier source level debugging, the compilers pro-
• Customizable toolbar and key mapping
vide symbol information that is compatible with the
• A status bar MPLAB IDE memory display.
• On-line help

 2002 Microchip Technology Inc. DS41120B-page 141

PIC16C717/770/771
14.4 MPLINK Object Linker/ 14.6 MPLAB ICE High Performance
MPLIB Object Librarian Universal In-Circuit Emulator with
The MPLINK object linker combines relocatable
MPLAB IDE
objects created by the MPASM assembler and the The MPLAB ICE universal in-circuit emulator is intended
MPLAB C17 and MPLAB C18 C compilers. It can also to provide the product development engineer with a
link relocatable objects from pre-compiled libraries, complete microcontroller design tool set for PICmicro
using directives from a linker script. microcontrollers (MCUs). Software control of the
The MPLIB object librarian is a librarian for pre- MPLAB ICE in-circuit emulator is provided by the
compiled code to be used with the MPLINK object MPLAB Integrated Development Environment (IDE),
linker. When a routine from a library is called from which allows editing, building, downloading and source
another source file, only the modules that contain that debugging from a single environment.
routine will be linked in with the application. This allows The MPLAB ICE 2000 is a full-featured emulator sys-
large libraries to be used efficiently in many different tem with enhanced trace, trigger and data monitoring
applications. The MPLIB object librarian manages the features. Interchangeable processor modules allow the
creation and modification of library files. system to be easily reconfigured for emulation of differ-
The MPLINK object linker features include: ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
• Integration with MPASM assembler and MPLAB
support new PICmicro microcontrollers.
C17 and MPLAB C18 C compilers.
• Allows all memory areas to be defined as sections The MPLAB ICE in-circuit emulator system has been
to provide link-time flexibility. designed as a real-time emulation system, with
advanced features that are generally found on more
The MPLIB object librarian features include: expensive development tools. The PC platform and
• Easier linking because single libraries can be Microsoft® Windows environment were chosen to best
included instead of many smaller files. make these features available to you, the end user.
• Helps keep code maintainable by grouping
related modules together. 14.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be The ICEPIC low cost, in-circuit emulator is a solution
added, listed, replaced, deleted or extracted. for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
14.5 MPLAB SIM Software Simulator Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
The MPLAB SIM software simulator allows code devel-
or PIC16CXXX products through the use of inter-
opment in a PC-hosted environment by simulating the
changeable personality modules, or daughter boards.
PICmicro series microcontrollers on an instruction
The emulator is capable of emulating without target
level. On any given instruction, the data areas can be
application circuitry being present.
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.

DS41120B-page 142  2002 Microchip Technology Inc.

 PIC16C717/770/771
14.8 MPLAB ICD In-Circuit Debugger 14.11 PICDEM 1 Low Cost PICmicro
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
Demonstration Board
erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board
based on the FLASH PICmicro MCUs and can be used which demonstrates the capabilities of several of
to develop for this and other PICmicro microcontrollers. Microchip’s microcontrollers. The microcontrollers sup-
The MPLAB ICD utilizes the in-circuit debugging capa- ported are: PIC16C5X (PIC16C54 to PIC16C58A),
bility built into the FLASH devices. This feature, along PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
with Microchip’s In-Circuit Serial ProgrammingTM proto- PIC17C42, PIC17C43 and PIC17C44. All necessary
col, offers cost-effective in-circuit FLASH debugging hardware and software is included to run basic demo
from the graphical user interface of the MPLAB programs. The user can program the sample microcon-
Integrated Development Environment. This enables a trollers provided with the PICDEM 1 demonstration
designer to develop and debug source code by watch- board on a PRO MATE II device programmer, or a
ing variables, single-stepping and setting break points. PICSTART Plus development programmer, and easily
Running at full speed enables testing hardware in real- test firmware. The user can also connect the
time. PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
14.9 PRO MATE II Universal Device lator for testing. A prototype area is available for the
Programmer user to build some additional hardware and connect it
The PRO MATE II universal device programmer is a to the microcontroller socket(s). Some of the features
full-featured programmer, capable of operating in include an RS-232 interface, a potentiometer for simu-
Stand-alone mode, as well as PC-hosted mode. The lated analog input, push button switches and eight
PRO MATE II device programmer is CE compliant. LEDs connected to PORTB.

The PRO MATE II device programmer has program- 14.12 PICDEM 2 Low Cost PIC16CXX
mable VDD and VPP supplies, which allow it to verify Demonstration Board
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem-
and error messages, keys to enter commands and a onstration board that supports the PIC16C62,
modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74
package types. In Stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft-
device programmer can read, verify, or program ware is included to run the basic demonstration pro-
PICmicro devices. It can also set code protection in this grams. The user can program the sample
mode. microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
14.10 PICSTART Plus Entry Level or a PICSTART Plus development programmer, and
Development Programmer easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
The PICSTART Plus development programmer is an board to test firmware. A prototype area has been pro-
easy-to-use, low cost, prototype programmer. It con- vided to the user for adding additional hardware and
nects to the PC via a COM (RS-232) port. MPLAB connecting it to the microcontroller socket(s). Some of
Integrated Development Environment software makes the features include a RS-232 interface, push button
using the programmer simple and efficient. switches, a potentiometer for simulated analog input, a
The PICSTART Plus development programmer sup- serial EEPROM to demonstrate usage of the I2CTM bus
ports all PICmicro devices with up to 40 pins. Larger pin and separate headers for connection to an LCD
count devices, such as the PIC16C92X and module and a keypad.
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.

 2002 Microchip Technology Inc. DS41120B-page 143

PIC16C717/770/771
14.13 PICDEM 3 Low Cost PIC16CXXX 14.14 PICDEM 17 Demonstration Board
Demonstration Board The PICDEM 17 demonstration board is an evaluation
The PICDEM 3 demonstration board is a simple dem- board that demonstrates the capabilities of several
onstration board that supports the PIC16C923 and Microchip microcontrollers, including PIC17C752,
PIC16C924 in the PLCC package. It will also support PIC17C756A, PIC17C762 and PIC17C766. All neces-
future 44-pin PLCC microcontrollers with an LCD Mod- sary hardware is included to run basic demo programs,
ule. All the necessary hardware and software is which are supplied on a 3.5-inch disk. A programmed
included to run the basic demonstration programs. The sample is included and the user may erase it and
user can program the sample microcontrollers pro- program it with the other sample programs using the
vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or the PICSTART
PRO MATE II device programmer, or a PICSTART Plus Plus development programmer, and easily debug and
development programmer with an adapter socket, and test the sample code. In addition, the PICDEM 17 dem-
easily test firmware. The MPLAB ICE in-circuit emula- onstration board supports downloading of programs to
tor may also be used with the PICDEM 3 demonstration and executing out of external FLASH memory on board.
board to test firmware. A prototype area has been pro- The PICDEM 17 demonstration board is also usable
vided to the user for adding hardware and connecting it with the MPLAB ICE in-circuit emulator, or the
to the microcontroller socket(s). Some of the features PICMASTER emulator and all of the sample programs
include a RS-232 interface, push button switches, a can be run and modified using either emulator. Addition-
potentiometer for simulated analog input, a thermistor ally, a generous prototype area is available for user
and separate headers for connection to an external hardware.
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4 14.15 KEELOQ Evaluation and
commons and 12 segments, that is capable of display- Programming Tools
ing time, temperature and day of the week. The
KEELOQ evaluation and programming tools support
PICDEM 3 demonstration board provides an additional
Microchip’s HCS Secure Data Products. The HCS eval-
RS-232 interface and Windows software for showing
uation kit includes a LCD display to show changing
the demultiplexed LCD signals on a PC. A simple serial
codes, a decoder to decode transmissions and a pro-
interface allows the user to construct a hardware
gramming interface to program test transmitters.
demultiplexer for the LCD signals.

DS41120B-page 144  2002 Microchip Technology Inc.

 93CXX

24CXX/
25CXX/
HCSXXX

PIC14000
MCP2510

PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
MCRFXXX

PIC16F62X
PIC16F8XX

PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC18FXXX

PIC12CXXX
PIC16CXXX
MPLAB® Integrated
TABLE 14-1:

Development Environment

9
9
9
9
9
9
9
9
9
9
9
9
9
MPLAB® C17 C Compiler

9 9
9 9
MPLAB® C18 C Compiler
MPASMTM Assembler/

Software Tools
MPLINKTM Object Linker
9
9

MPLAB® ICE In-Circuit Emulator

 2002 Microchip Technology Inc.

**

9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9 9
9 9 9
ICEPICTM In-Circuit Emulator

9
9
9
9
9
9
9
9
MPLAB® ICD In-Circuit
* *
Debugger

9
9
9
9

PICSTART® Plus Entry Level

Development Programmer **

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

PRO MATE® II
Universal Device Programmer **

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

Programmers Debugger Emulators

PICDEMTM 1 Demonstration †
Board

9
9
9
9
9

PICDEMTM 2 Demonstration † †
Board

9
9
9
9
DEVELOPMENT TOOLS FROM MICROCHIP

PICDEMTM 3 Demonstration
Board
9

PICDEMTM 14A Demonstration

Board

9
PICDEMTM 17 Demonstration
Board
9

KEELOQ® Evaluation Kit

KEELOQ® Transponder Kit
9 9

microIDTM Programmer’s Kit

125 kHz microIDTM

Demo Boards and Eval Kits

Developer’s Kit
9 9

125 kHz Anticollision microIDTM

Developer’s Kit
9

13.56 MHz Anticollision

microIDTM Developer’s Kit
9

MCP2510 CAN Developer’s Kit

9

* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.

DS41120B-page 145
PIC16C717/770/771

† Development tool is available on select devices.

PIC16C717/770/771
NOTES:

DS41120B-page 146  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................ .-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Maximum voltage between AVDD and VDD pins................................................................................................................. ± 0.3V
Maximum voltage between AVSS and VSS pins ................................................................................................................. ± 0.3V
Voltage on MCLR with respect to VSS........................................................................................................ -0.3V to +8.5V
Voltage on RA4 with respect to Vss ......................................................................................................... -0.3V to +10.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined) ...........................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

 2002 Microchip Technology Inc. DS41120B-page 147

PIC16C717/770/771
FIGURE 15-1: PIC16C717/770/771 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C

6.0

5.5

5.0

4.5
VDD
(Volts)
4.0

3.5

3.0

2.5

0 4 10 20 25
Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

FIGURE 15-2: PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C

6.0

5.5

5.0

4.5
VDD
(Volts)
4.0

3.5

3.0

2.5

0 4 10 20 25
Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

DS41120B-page 148  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 15-3: PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ 0°C, +70°C ≤ TA ≤ +85°C

6.0

5.5

5.0

4.5
VDD
(Volts)
4.0

3.5

3.0

2.5

0 4 10 20 25
Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

 2002 Microchip Technology Inc. DS41120B-page 149

PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16LC717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16C717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
D001 VDD Supply Voltage 2.5 — 5.5 V
D001 VDD Supply Voltage 4.0 — 5.5 V
D002* VDR RAM Data Retention — 1.5 — V
Voltage(1)
D002* VDR RAM Data Retention — 1.5 — V
Voltage(1)
D003* VPOR VDD start voltage to — VSS — V See section on Power-on Reset for details
ensure internal Power-
on Reset signal
D003* VPOR VDD start voltage to — VSS — V See section on Power-on Reset for details
ensure internal Power-
on Reset signal
D004* SVDD VDD rise rate to ensure 0.05 — — V/ms See section on Power-on Reset for details.
internal Power-on Reset PWRT enabled
signal
D004* SVDD VDD rise rate to ensure 0.05 — — V/ms See section on Power-on Reset for details.
internal Power-on Reset PWRT enabled
signal
*These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.

DS41120B-page 150  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
(Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16LC717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16C717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
IDD Supply Current(2)
D010D PIC16LC7XX 1.0 2.0 mA FOSC = 10 MHz, VDD = 3V, -40°C to 85°C
D010E 3.0 FOSC = 10 MHz, VDD = 3V, -40°C to 125°C

D010G 0.36 1.0 mA FOSC = 4 MHz, VDD = 2.5V, -40°C to 125°C

D010K 11 45 µA FOSC = 32 kHz, VDD = 2.5V, -40°C to 125°C

IDD Supply Current(2)
D010 PIC16C7XX 4.0 7.5 mA FOSC = 20 MHz, VDD = 5.5V, -40°C to 85°C
D010A 12.0 FOSC = 20 MHz, VDD = 5.5V, -40°C to 125°C

D010B 2.5 5.0 mA FOSC = 20 MHz, VDD = 4V, -40°C to 85°C

D010C 6.0 FOSC = 20 MHz, VDD = 4V, -40°C to 125°C

D010F 0.55 1.5 mA FOSC = 4 MHz, VDD = 4V, -40°C to 125°C

D010H 30 80 µA FOSC = 32 kHz, VDD = 4V, -40°C to 85°C

D010J 95 FOSC = 32 kHz, VDD = 4V, -40°C to 125°C
*These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.

 2002 Microchip Technology Inc. DS41120B-page 151

PIC16C717/770/771
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16LC717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16C717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
IPD Power-down Current(3)
D020D PIC16LC7XX 0.3 2.0 µA VDD = 3V, -40°C to 85°C
D020E 5.0 VDD = 3V, -40°C to 125°C

D020F 0.1 1.5 µA VDD = 2.5V, -40°C to 85°C

D020G 3.0 VDD = 2.5V, -40°C to 125°C
D020 PIC16C7XX 1.4 4.0 µA VDD = 5.5V, -40°C to 85°C
D020A 8.0 VDD = 5.5V, -40°C to 125°C

D020B 1.0 3.5 µA VDD = 4V, -40°C to 85°C

D020C 6.0 VDD = 4V, -40°C to 125°C
*These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

DS41120B-page 152  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
(Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16LC717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16C717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
Base plus Module current
D021A IWDT Watchdog Timer 2 10 µA VDD = 3V, -40°C to 125°C
D021 IWDT Watchdog Timer 5 20 µA VDD = 4V, -40°C to 125°C
D021 IWDT Watchdog Timer 5 20 µA VDD = 4V, -40°C to 125°C
D025 IT1OSC Timer1 Oscillator 3 9 µA VDD = 3V, -40°C to 125°C
D025 IT1OSC Timer1 Oscillator 4 12 µA VDD = 4V, -40°C to 125°C
D025 IT1OSC Timer1 Oscillator 4 12 µA VDD = 4V, -40°C to 125°C
D026* IAD ADC Converter 300 µA VDD = 5.5V, A/D on, not converting
D026* IAD ADC Converter 300 µA VDD = 5.5V, A/D on, not converting
D027 IPLVD Programmable Low 55 125 µA VDD = 4V, -40°C to 85°C
D027A Voltage Detect 150 VDD = 4V, -40°C to 125°C
D027 IPLVD Programmable Low 55 125 µA VDD = 4V, -40°C to 85°C
D027A Voltage Detect 150 VDD = 4V, -40°C to 125°C
D028 IPBOR Programmable Brown- 55 125 µA VDD = 5V, -40°C to 85°C
D028A out Reset 150 VDD = 5V, -40°C to 125°C
D028 IPBOR Programmable Brown- 55 125 µA VDD = 5V, -40°C to 85°C
D028A out Reset 150 VDD = 5V, -40°C to 125°C
D029 IVRH Voltage reference High 200 750 µA VDD = 5V, -40°C to 85°C
D029A 1.0 mA VDD = 5V, -40°C to 125°C
D029 IVRH Voltage reference High 200 750 µA VDD = 5V, -40°C to 85°C
D029A 1.0 mA VDD = 5V, -40°C to 125°C
D030 IVRL Voltage reference Low 200 750 µA VDD = 4V, -40°C to 85°C
D030A 1.0 mA VDD = 4V, -40°C to 125°C
D030 IVRL Voltage reference Low 200 750 µA VDD = 4V, -40°C to 85°C
D030A 1.0 mA VDD = 4V, -40°C to 125°C
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.

 2002 Microchip Technology Inc. DS41120B-page 153

PIC16C717/770/771
15.2 DC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771 (Commercial,
Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in Section 15.1 and
Section 15.2.
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
Input Low Voltage
VIL I/O ports
D030 with TTL buffer VSS — 0.15VDD V For entire VDD range
D030A VSS — 0.8V V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS — 0.2VDD V For entire VDD range
D032 MCLR VSS — 0.2VDD V
D033 OSC1 (in XT, HS, LP and EC) VSS — 0.3VDD V
Input High Voltage
VIH I/O ports —
with TTL buffer
D040 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V
D040A (0.25VDD — VDD V For entire VDD range
+ 0.8V)
D041 with Schmitt Trigger buffer 0.8VDD — VDD V For entire VDD range
D042 MCLR 0.8VDD — VDD V
D042A OSC1 (XT, HS, LP and EC) 0.7VDD — VDD V
D070 IPURB PORTB weak pull-up current 50 250 400 µA VDD = 5V, VPIN = VSS
per pin
Input Leakage Current (1,2)
D060 IIL I/O ports (with digital functions) — — ±1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
D060A IIL I/O ports (with analog func- — — ±100 nA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
tions)
D061 RA5/MCLR/VPP — — ±5 µA Vss ≤ VPIN ≤ VDD
D063 OSC1 — — ±5 µA Vss ≤ VPIN ≤ VDD, XT, HS, LP and EC
osc configuration
Output Low Voltage
D080 VOL I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V
Output High Voltage
D090 VOH I/O ports(2) VDD - 0.7 — — V IOH = -3.0 mA, VDD = 4.5V
D150* VOD Open Drain High Voltage — — 10.5 V RA4 pin
Capacitive Loading Specs on
Output Pins*
D100 COS OSC2 pin — — 15 pF In XT, HS and LP modes when exter-
C2 nal clock is used to drive OSC1.
D101 CIO All I/O pins and OSC2 (in RC — — 50 pF
D102 CB mode) SCL, SDA in I2C mode — — 400 pF
CVRH VRH pin — — 200 pF VRH output enabled
CVRL VRL pin — — 200 pF VRL output enabled
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as current sourced by the pin.

DS41120B-page 154  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.3 AC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771
(Commercial, Industrial, Extended)
15.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C (I2C specifications only)
AA output access
BUF Bus free
High High
Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition

 2002 Microchip Technology Inc. DS41120B-page 155

PIC16C717/770/771
FIGURE 15-4: LOAD CONDITIONS
Load condition 1 Load condition 2

VDD/2

RL

CL CL
Pin Pin

VSS VSS

RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output

DS41120B-page 156  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.3.2 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 15-5: CLKOUT AND I/O TIMING

Q4 Q1 Q2 Q3

OSC1

CLKOUT(1)

13 12
19 18
14 16

I/O Pin
(input)

17 15

I/O Pin old value new value

(output)

20, 21

Note: Refer to Figure 15-4 for load conditions.

TABLE 15-1: CLKOUT AND I/O TIMING REQUIREMENTS

Param. Sym Characteristic Min Typ† Max Unit Conditions
No. s
12* TckR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ↑ 0.25TCY + 25 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to — 50 150 ns
Port out valid
18* TosH2ioI OSC1↑ (Q2 cycle) to PIC16C717/770/771 100 — — ns
Port input invalid (I/O in PIC16LC717/770/771 200 — — ns
hold time)
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time PIC16C717/770/771 — 10 25 ns
PIC16LC717/770/771 — — 60 ns
21* TioF Port output fall time PIC16C717/770/771 — 10 25 ns
PIC16LC717/770/771 — — 60 ns
22††* Tinp INT pin high or low time TCY — — ns
23††* Trbp RB<7:0> change INT high or low time TCY — — ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken ER or INTRC w/CLKOUT mode where CLKOUT output is 4 x TOSC.

 2002 Microchip Technology Inc. DS41120B-page 157

PIC16C717/770/771
FIGURE 15-6: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1

OSC1
1 3 3 4 4
2

TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS

Param No. Sym Characteristic Min Typ† Max Units Conditions
1A FOSC External CLKIN Frequency DC — 4 MHz XT mode
(Note 1) DC — 20 MHz EC mode
DC — 20 MHz HS mode
DC — 200 kHz LP mode
Oscillator Frequency 0.1* — 4 MHz XT mode
(Note 1) 4* — 20 MHz HS mode
5* — 200 kHz LP mode
1 TOSC External CLKIN Period 250 — — ns XT mode
(Note 1) 50 — — ns EC mode
50 — — ns HS mode
5 — — µs LP mode
Oscillator Period 250 — 10,000* ns XT mode
(Note 1) 50 — 250* ns HS mode
5 — — µs LP mode
2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC
3* TosL, External Clock in (OSC1) High or Low 100 — — ns XT mode
TosH Time 2.5 — — µs LP mode
15 — — ns HS mode
EC mode
4* TosR, External Clock in (OSC1) Rise or Fall — — 25 ns XT mode
TosF Time — — 50 ns LP mode
— — 15 ns HS mode
EC mode
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "Max. Frequency" values with a square wave applied to the OSC1/CLKIN
pin.
When an external clock input is used, the "Min." frequency (or Max. TCY) limit is "DC" (no clock) for all devices.

DS41120B-page 158  2002 Microchip Technology Inc.

 PIC16C717/770/771
TABLE 15-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC16C717/770/771 AND
PIC16LC717/770/771

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating Voltage VDD range is described in Section and Section

Parameter
No.
Sym Characteristic Min Typ(1)* Max Units Conditions

Internal Calibrated RC Frequency 3.65 4.00 4.28 MHz VDD = 5.0V

FIRC
Internal RC Frequency* 3.55 4.00 4.31 MHz VDD = 2.5V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.

FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING

VDD

MCLR

30
Internal
POR

33
PWRT
Time-out
32

OSC
Time-out

Internal
RESET

Watchdog
Timer
RESET
31
34
34

I/O Pins

Note: Refer to Figure 15-4 for load conditions.

FIGURE 15-8: BROWN-OUT RESET TIMING

VDD VBOR

35

 2002 Microchip Technology Inc. DS41120B-page 159

PIC16C717/770/771
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30* TMCL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40°C to +85°C
31* TWDT Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C
(No Prescaler)
32* TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
33* TPWRT Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34* TIOZ I/O Hi-impedance from MCLR Low — — 2.1 µs
or Watchdog Timer Reset
35* TBOR Brown-out Reset pulse width 100 — — µs VDD ≤ VBOR (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

FIGURE 15-9: BROWN-OUT RESET CHARACTERISTICS

VDD

VBOR (device not in Brown-out Reset)

(device in Brown-out Reset)

RESET (due to BOR) 72 ms time-out

FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

RA4/T0CKI

40 41

42

RB6/T1OSO/T1CKI/PIC

45 46

47 48
TMR0 or
TMR1

Note: Refer to Figure 15-4 for load conditions.

DS41120B-page 160  2002 Microchip Technology Inc.

 PIC16C717/770/771
TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
With Prescaler 10 — — ns parameter 42
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
With Prescaler 10 — — ns parameter 42
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of: — — ns N = prescale value
20 or TCY + 40 (2, 4, ..., 256)
N
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
Synchronous, PIC16C717/770/771 15 — — ns parameter 47
Prescaler = PIC16LC717/770/771 25 — — ns
2,4,8
Asynchronous PIC16C717/770/771 30 — — ns
PIC16LC717/770/771 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
Synchronous, PIC16C717/770/771 15 — — ns parameter 47
Prescaler = PIC16LC717/770/771 25 — — ns
2,4,8
Asynchronous PIC16C717/770/771 30 — — ns
PIC16LC717/770/771 50 — — ns
47* Tt1P T1CKI input period Synchronous PIC16C717/770/771 Greater of: — — ns N = prescale value
30 OR TCY + 40 (1, 2, 4, 8)
N
PIC16LC717/770/771 Greater of: — — ns N = prescale value
50 OR TCY + 40 (1, 2, 4, 8)
N
Asynchronous PIC16C717/770/771 60 — — ns
PIC16LC717/770/771 100 — — ns
Ft1 Timer1 oscillator input frequency range DC — 50 kHz
(oscillator enabled by setting bit T1OSCEN)
48 Tcke2tmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

FIGURE 15-11: ENHANCED CAPTURE/COMPARE/PWM TIMINGS (ECCP)

RB3/CCP1/P1A
(Capture Mode)

50 51

52

RB3/CCP1/P1A
(Compare or PWM Mode)

53 54

Note: Refer to Figure 15-4 for load conditions.

 2002 Microchip Technology Inc. DS41120B-page 161

PIC16C717/770/771
TABLE 15-6: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
50* TccL CCP1 input low No Prescaler 0.5TCY + 20 — — ns
time PIC16C717/770/771 10 — — ns
With Prescaler PIC16LC717/770/771
20 — — ns
51* TccH CCP1 input high No Prescaler 0.5TCY + 20 — — ns
time PIC16C717/770/771 10 — — ns
With Prescaler PIC16LC717/770/771
20 — — ns
52* TccP CCP1 input period 3TCY + 40 — — ns N = prescale value
N (1, 4 or 16)
53* TccR CCP1 output fall time PIC16C717/770/771 — 10 25 ns
PIC16LC717/770/771 — 25 45 ns
54* TccF CCP1 output fall time PIC16C717/770/771 — 10 25 ns
PIC16LC717/770/771 — 25 45 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

DS41120B-page 162  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.4 Analog Peripherals Characteristics: PIC16C717/770/771 & PIC16LC717/770/771
(Commercial, Industrial, Extended)
15.4.1 BANDGAP MODULE

FIGURE 15-12: BANDGAP START-UP TIME

VBGAP VBGAP = 1.2V

(internal use only)

Enable Bandgap

TBGAP
Bandgap stable

TABLE 15-7: BANDGAP START-UP TIME

Param. Sym Characteristic Min Typ† Max Units Conditions
No.
36* TBGAP Bandgap start-up time — 19 33 µS Defined as the time between the
instant that the bandgap is
enabled and the moment that
the bandgap reference voltage
is stable.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

 2002 Microchip Technology Inc. DS41120B-page 163

PIC16C717/770/771
15.4.2 LOW VOLTAGE DETECT MODULE (LVD)

FIGURE 15-13: LOW VOLTAGE DETECT CHARACTERISTICS

VDD

VLVD

(LVDIF set by hardware)

LVDIF

(LVDIF can be cleared in software anytime during

the gray area)

TABLE 15-8: ELECTRICAL CHARACTERISTICS: LVD

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
DC CHARACTERISTICS
0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in DC Characteristics Section 15.1.
Param.
Characteristic Symbol Min Typ† Max Units Conditions
No.
D420* LVD Voltage LVV = 0100 2.5 2.58 2.66 V
LVV = 0101 2.7 2.78 2.86 V
LVV = 0110 2.8 2.89 2.98 V
LVV = 0111 3.0 3.1 3.2 V
LVV = 1000 3.3 3.41 3.52 V
LVV = 1001 VLVD 3.5 3.61 3.72 V
LVV = 1010 3.6 3.72 3.84 V
LVV = 1011 3.8 3.92 4.04 V
LVV = 1100 4.0 4.13 4.26 V
LVV = 1101 4.2 4.33 4.46 V
LVV = 1110 4.5 4.64 4.78 V
* These parameters are characterized but not tested.
Note 1: Production tested at Tamb = 25°C. Specifications over temperature limits ensured by characterization.

DS41120B-page 164  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.4.3 PROGRAMMABLE BROWN-OUT RESET MODULE (PBOR)

TABLE 15-9: DC CHARACTERISTICS: PBOR

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Characteristics Section 15.1.
Param.
Characteristic Symbol Min Typ Max Units Conditions
No.
D005 BOR Voltage BORV<1:0> = 11 2.5 2.58 2.66
BORV<1:0> = 10 2.7 2.78 2.86
VBOR V
BORV<1:0> = 01 4.2 4.33 4.46
BORV<1:0> = 00 4.5 4.64 4.78

15.4.4 VREF MODULE

TABLE 15-10: DC CHARACTERISTICS: VREF

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Characteristics
Section 15.1.
Param. Symbol
Characteristic Min Typ† Max Units Conditions
No.
D400 VRL Output Voltage 2.0 2.048 2.1 V VDD ≥ 2.7V, -40°C ≤ TA ≤ +85°C
VRH 4.0 4.096 4.2 V VDD ≥ 4.5V, -40°C ≤ TA ≤ +85°C
D400A VRL Output Voltage 1.9 2.048 2.2 V VDD ≥ 2.7V, -40°C ≤ TA ≤ +125°C
VRH 4.0 4.096 4.3 V VDD ≥ 4.5V, -40°C ≤ TA ≤ +125°C
D404* IVREFSO External Load Source — — 5 mA
D405* IVREFSI External Load Sink — — -5 mA
* CL External Capacitor Load — — 200 pF
D406* ∆Vout/ VRH Load Regulation — 0.6 1 mV/mA VDD ≥ 5V ISOURCE = 0 mA to 5 mA
∆Iout — 1 4 ISINK = 0 mA to 5 mA
VRL Load Regulation — 0.6 1 VDD ≥ 3V ISOURCE = 0 mA to 5 mA
— 2 4 ISINK = 0 mA to 5 mA
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are
for design guidance only and are not tested.

 2002 Microchip Technology Inc. DS41120B-page 165

PIC16C717/770/771
15.4.5 A/D CONVERTER MODULE

TABLE 15-11: PIC16C770/771 AND PIC16LC770/771 A/D CONVERTER CHARACTERISTICS:

Param. Sym Characteristic Min Typ† Max Units Conditions
No.
A01 NR Resolution — — 12 bits bit Min. resolution for A/D is 1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A03 EIL Integral error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A04 EDL Differential error — — +2 LSb No missing codes to 12 bits
VREF+ = AVDD = 4.096V,
-1
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A06 EOFF Offset error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A07 EGN Gain Error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A10 — Monotonicity — Note 3 — — AVSS ≤ VAIN ≤ VREF+
A20* VREF Reference voltage 4.096 — VDD V Absolute minimum electrical spec to
(VREF+ - VREF-) +0.3V ensure 12-bit accuracy.
A21* VREF+ Reference V High VREF- — AVDD V Min. resolution for A/D is 1 mV
(AVDD or VREF+)
A22* VREF- Reference V Low AVSS — VREF+ V Min. resolution for A/D is 1 mV
(AVSS or VREF-)
A25* VAIN Analog input volt- VREFL — VREFH V
age
A30* ZAIN Recommended — — 2.5 kΩ
impedance of ana-
log voltage source
A50* IREF VREF input current — — 10 µA During VAIN acquisition.
(Note 2) Based on differential of VHOLD to
VAIN.
To charge CHOLD see Section 11.0.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
2: VREF input current is from External VREF+, or VREF-, or AVSS, or AVDD pin, whichever is selected as refer-
ence input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

DS41120B-page 166  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 15-14: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION TIMING (NORMAL
MODE)

BSF ADCON0, GO
1/2 TCY
134
131
Q4
130

A/D CLK

A/D DATA 11 10 9 8 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF

GO DONE
SAMPLING STOPPED
SAMPLE 132

Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.

 2002 Microchip Technology Inc. DS41120B-page 167

PIC16C717/770/771
TABLE 15-12: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENTS
(NORMAL MODE)
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.

130*(3) TAD A/D clock period 1.6 — — µs Tosc based, VREF ≥ 2.5V

3.0 — — µs Tosc based, VREF full range

ADCS<1:0> = 11
(A/D RC mode)
3.0 6.0 9.0 µs At VDD = 2.5V
2.0 4.0 6.0 µs At VDD = 5.0V
131* TCNV Conversion time — 13TAD — TAD
(not including
acquisition time)
(Note 1)
132* TACQ Acquisition Time Note 2 11.5 — µs

5* — — µs The minimum time is the ampli-

fier settling time. This may be
used if the “new” input voltage
has not changed by more than
1LSb (i.e., 1mV @ 4.096V) from
the last sampled voltage (as
stated on CHOLD).
134* TGO Q4 to A/D clock — TOSC/2 — —
start
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.

DS41120B-page 168  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 15-15: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO
134
131
Q4
130

A/D CLK

A/D DATA 11 10 9 8 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF

GO DONE

SAMPLING STOPPED
SAMPLE 132

Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.

TABLE 15-13: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENT

(SLEEP MODE)
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.

130*(3) TAD A/D Internal RC ADCS<1:0> = 11 (RC mode)

oscillator period 3.0 6.0 9.0 µs At VDD= 3.0V
2.0 4.0 6.0 µs At VDD = 5.0V
131* TCNV Conversion time (not — 13TAD — —
including acquisition
time) (Note 1)
132* TACQ Acquisition Time (Note 2) 11.5 — µs

5* — — µs The minimum time is the amplifier

settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D clock start — TOSC/2 + TCY — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.

 2002 Microchip Technology Inc. DS41120B-page 169

PIC16C717/770/771
TABLE 15-14: PIC16C717 AND PIC16LC717 A/D CONVERTER CHARACTERISTICS:
Param. Sym Characteristic Min Typ† Max Units Conditions
No.
A01 NR Resolution — — 10 bits bit Min. resolution for A/D is 4.1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A03 EIL Integral error — — ±1 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A04 EDL Differential error — — ±1 LSb No missing codes to 10 bits
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A06 EOFF Offset error — — ±2 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A07 EGN Gain Error — — ±1 LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A10 — Monotonicity — Note 3 — — AVSS ≤ VAIN ≤ VREF+
A20* VREF Reference voltage 4.096 — VDD +0.3V V Absolute minimum electrical spec to
(VREF+ - VREF-) ensure 10-bit accuracy.
A21* VREF+ Reference V High VREF- — AVDD V Min. resolution for A/D is 4.1 mV
(AVDD or VREF+)
A22* VREF- Reference V Low AVSS — VREF+ V Min. resolution for A/D is 4.1 mV
(AVSS or VREF-)
A25* VAIN Analog input voltage VREFL — VREFH V
A30* ZAIN Recommended — — 2.5 kΩ
impedance of analog
voltage source
A50* IREF VREF input current — — 10 µA During VAIN acquisition.
(Note 2) Based on differential of VHOLD to VAIN.
To charge CHOLD see Section 11.0.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such
leakage from the A/D module.
2: VREF current is from External VREF+, or VREF-, or AVSS, or AVDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

DS41120B-page 170  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 15-16: PIC16C717 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO
1/2 TCY
134
131
Q4
130

A/D CLK

A/D DATA 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF

GO DONE
SAMPLING STOPPED
SAMPLE 132

Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.

TABLE 15-15: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (NORMAL MODE)
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.

130*(3) TAD A/D clock period 1.6 — — µs Tosc based, VREF ≥ 2.5V

3.0 — — µs Tosc based, VREF full range

ADCS<1:0> = 11 (A/D RC mode)
3.0 6.0 9.0 µs At VDD = 2.5V
2.0 4.0 6.0 µs At VDD = 5.0V
131* TCNV Conversion time (not — 11TAD — TAD
including
acquisition time)
(Note 1)
132* TACQ Acquisition Time (Note 2) 11.5 — µs

5* — — µs The minimum time is the amplifier

settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D clock start — TOSC/2 — —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.

 2002 Microchip Technology Inc. DS41120B-page 171

PIC16C717/770/771
FIGURE 15-17: PIC16C717 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO
134
131
Q4
130

A/D CLK

A/D DATA 9 8 7 6 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF

GO DONE
SAMPLING STOPPED
SAMPLE 132

Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.

TABLE 15-16: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (SLEEP MODE)
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.

130*(3) TAD A/D clock period 3.0 6.0 9.0 µs ADCS<1:0> = 11 (A/D RC mode)
At VDD = 3.0V
2.0 4.0 6.0 µs At VDD = 5.0V
131* TCNV Conversion time (not — 11TAD — —
including acquisition
time) (Note 1)
132* TACQ Acquisition Time (Note 2) 11.5 — µs

5* — — µs The minimum time is the amplifier

settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D clock start — TOSC/2 + TCY — — If the A/D RC clock source is
selected, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.

DS41120B-page 172  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.5 Master SSP SPI Mode Timing Waveforms and Requirements

FIGURE 15-18: SPI MASTER MODE TIMING (CKE = 0)

SS
70
SCK
(CKP = 0)

71 72
78 79

SCK
(CKP = 1)

79 78
80

SDO MSb BIT6 - - - - - -1 LSb

75, 76

SDI MSb IN BIT6 - - - -1 LSb IN

74
73
Note: Refer to Figure 15-4 for load conditions.

TABLE 15-17: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.
Symbol Characteristic Min Typ† Max Units Conditions
No.
70* TssL2scH,
SS↓ to SCK↓ or SCK↑ input TCY — — ns
TssL2scL
71* TscH SCK input high time Continuous 1.25TCY + 30 — — ns
71A* (Slave mode) Single Byte 40 — — ns Note 1
72* TscL SCK input low time Continuous 1.25TCY + 30 — — ns
72A* (Slave mode) Single Byte 40 — — ns Note 1
73* TdiV2scH,
Setup time of SDI data input to SCK edge 100 — — ns
TdiV2scL
73A* TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1
edge of Byte2
74* TscH2diL,
Hold time of SDI data input to SCK edge 100 — — ns
TscL2diL
75* TdoR SDO data output rise time PIC16CXXX — 10 25 ns
PIC16LCXXX — 20 45 ns
76* TdoF SDO data output fall time — 10 25 ns
78* TscR SCK output rise time PIC16CXXX — 10 25 ns
(Master mode) PIC16LCXXX — 20 45 ns
79* TscF SCK output fall time (Master mode) — 10 25 ns
80* TscH2doV, SDO data output valid PIC16CXXX — — 50 ns
TscL2doV after SCK edge PIC16LCXXX — — 100 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.

 2002 Microchip Technology Inc. DS41120B-page 173

PIC16C717/770/771
FIGURE 15-19: SPI MASTER MODE TIMING (CKE = 1)

SS
81
SCK
(CKP = 0)

71 72
79
73
SCK
(CKP = 1)
80
78

SDO MSb BIT6 - - - - - -1 LSb

75, 76

SDI MSb IN BIT6 - - - -1 LSb IN

74

Note: Refer to Figure 15-4 for load conditions.

TABLE 15-18: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.
Symbol Characteristic Min Typ† Max Units Conditions
No.
71* TscH SCK input high time Continuous 1.25TCY + 30 — — ns
71A* (Slave mode) Single Byte 40 — — ns Note 1
72* TscL SCK input low time Continuous 1.25TCY + 30 — — ns
72A* (Slave mode) Single Byte 40 — — ns Note 1
73* TdiV2scH, Setup time of SDI data input to SCK 100 — — ns
TdiV2scL edge
73A* TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1
edge of Byte2
74* TscH2diL,
Hold time of SDI data input to SCK edge 100 — — ns
TscL2diL
75* TdoR SDO data output rise PIC16CXXX — 10 25 ns
time PIC16LCXXX 20 45 ns
76* TdoF SDO data output fall time — 10 25 ns
78* TscR SCK output rise time PIC16CXXX — 10 25 ns
(Master mode) PIC16LCXXX 20 45 ns
79* TscF SCK output fall time (Master mode) — 10 25 ns
80* TscH2doV, SDO data output valid PIC16CXXX — — 50 ns
TscL2doV after SCK edge PIC16LCXXX — 100 ns
81* TdoV2scH,
SDO data output setup to SCK edge TCY — — ns
TdoV2scL
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.

DS41120B-page 174  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 15-20: SPI SLAVE MODE TIMING (CKE = 0)

SS

70
SCK
(CKP = 0) 83

71 72
78 79

SCK
(CKP = 1)

79 78
80

SDO MSb BIT6 - - - - - -1 LSb

75, 76 77

SDI MSb IN BIT6 - - - -1 LSb IN

74
73
Note: Refer to Figure 15-4 for load conditions.

TABLE 15-19: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)

Param.
Symbol Characteristic Min Typ† Max Units Conditions
No.
70* TssL2scH,
SS↓ to SCK↓ or SCK↑ input TCY — — ns
TssL2scL
71* TscH SCK input high time Continuous 1.25TCY + 30 — — ns
71A* (Slave mode) Single Byte 40 — — ns Note 1
72* TscL SCK input low time Continuous 1.25TCY + 30 — — ns
72A* (Slave mode) Single Byte 40 — — ns Note 1
73* TdiV2scH,
Setup time of SDI data input to SCK edge 100 — — ns
TdiV2scL
73A* TB2B Last clock edge of Byte1 to the 1st clock edge 1.5TCY + 40 — — ns Note 1
of Byte2
74* TscH2diL,
Hold time of SDI data input to SCK edge 100 — — ns
TscL2diL
75* TdoR SDO data output rise time PIC16CXXX — 10 25 ns
PIC16LCXXX 20 45 ns
76* TdoF SDO data output fall time — 10 25 ns
77* TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78* TscR SCK output rise time (Master PIC16CXXX — 10 25 ns
mode) PIC16LCXXX 20 45 ns
79* TscF SCK output fall time (Master mode) — 10 25 ns
80* TscH2doV, SDO data output valid after PIC16CXXX — — 50 ns
TscL2doV SCK edge PIC16LCXXX — 100 ns
83* TscH2ssH, SS ↑ after SCK edge 1.5TCY + 40 — — ns
TscL2ssH
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.

 2002 Microchip Technology Inc. DS41120B-page 175

PIC16C717/770/771
FIGURE 15-21: SPI SLAVE MODE TIMING (CKE = 1)
82
SS

70
SCK
83
(CKP = 0)

71 72

SCK
(CKP = 1)
80

SDO MSb BIT6 - - - - - -1 LSb

75, 76 77

SDI
MSb IN BIT6 - - - -1 LSb IN

74
Note: Refer to Figure 15-4 for load conditions.

TABLE 15-20: SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param.
Symbol Characteristic Min Typ† Max Units Conditions
No.
70* TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — — ns
TssL2scL
71* TscH SCK input high time Continuous 1.25TCY + 30 — — ns
71A* (Slave mode) Single Byte 40 — — ns Note 1
72* TscL SCK input low time Continuous 1.25TCY + 30 — — ns
72A* (Slave mode) Single Byte 40 — — ns Note 1
73A* TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1
edge of Byte2
74* TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns
TscL2diL
75* TdoR SDO data output rise time PIC16CXXX — 10 25 ns
PIC16LCXXX 20 45 ns
76* TdoF SDO data output fall time — 10 25 ns
77* TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78* TscR SCK output rise time (Mas- PIC16CXXX — 10 25 ns
ter mode) PIC16LCXXX — 20 45 ns
79* TscF SCK output fall time (Master mode) — 10 25 ns
80* TscH2doV, SDO data output valid after PIC16CXXX — — 50 ns
TscL2doV SCK edge PIC16LCXXX — — 100 ns
82* TssL2doV SDO data output valid after PIC16CXXX — — 50 ns
SS↓ edge PIC16LCXXX — — 100 ns
83* TscH2ssH, SS ↑ after SCK edge 1.5TCY + 40 — — ns
TscL2ssH
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.

DS41120B-page 176  2002 Microchip Technology Inc.

 PIC16C717/770/771
15.6 Master SSP I2C Mode Timing Waveforms and Requirements

FIGURE 15-22: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS

SCL
91 93
90 92

SDA

START STOP
Condition Condition

Note: Refer to Figure 15-4 for load conditions.

TABLE 15-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS

Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
90* TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — — Only relevant for a Repeated
Setup time 400 kHz mode 2(TOSC)(BRG + 1) — — ns START
condition
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
91* THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — — After this period the first clock
Hold time 400 kHz mode 2(TOSC)(BRG + 1) — — ns pulse is generated

1 MHz mode(1) 2(TOSC)(BRG + 1) — —

92* TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — —
Setup time 400 kHz mode 2(TOSC)(BRG + 1) — — ns
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
93* THD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — —
Hold time 400 kHz mode 2(TOSC)(BRG + 1) — — ns
1 MHz mode(1) 2(TOSC)(BRG + 1) — —

* These parameters are characterized but not tested. For the value required by the I2C specification, please refer to the PICmi-
croTM Mid-Range MCU Family Reference Manual (DS33023).
Maximum pin capacitance = 10 pF for all I2C pins.

FIGURE 15-23: MASTER SSP I2C BUS DATA TIMING

103 100 102
101
SCL
90 106
91 107 92
SDA
In
109 109 110

SDA
Out
Note: Refer to Figure 15-4 for load conditions.

 2002 Microchip Technology Inc. DS41120B-page 177

PIC16C717/770/771
TABLE 15-22: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol Characteristic Min Max Units Conditions
No.
100* THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
101* TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
102* TR SDA and SCL 100 kHz mode — 1000 ns Cb is specified to be from
rise time 400 kHz mode 20 + 0.1Cb 300 ns 10 to 400 pF
1 MHz mode(1) — 300 ns
103* TF SDA and SCL 100 kHz mode — 300 ns Cb is specified to be from
fall time 400 kHz mode 20 + 0.1Cb 300 ns 10 to 400 pF
1 MHz mode(1) — 100 ns
90* TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Repeated
setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms START
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms condition
91* THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period the first clock
hold time 400 kHz mode 2(TOSC)(BRG + 1) — ms pulse is generated
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
106* THD:DAT Data input 100 kHz mode 0 — ns
hold time 400 kHz mode 0 0.9 ms
1 MHz mode(1) TBD — ns
107* TSU:DAT Data input 100 kHz mode 250 — ns Note 2
setup time 400 kHz mode 100 — ns
1 MHz mode(1) TBD — ns
92* TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ms
setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
109* TAA Output valid from 100 kHz mode — 3500 ns
clock 400 kHz mode — 1000 ns
1 MHz mode(1) — — ns
110 TBUF Bus free time 100 kHz mode 4.7 ‡ — ms Time the bus must be free
400 kHz mode 1.3 ‡ — ms before a new transmission
1 MHz mode(1) TBD‡ — ms can start
D102 ‡ Cb Bus capacitive loading — 400 pF
* These parameters are characterized but not tested. For the value required by the I2C specification, please refer to the
PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
‡ These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but (TSU:DAT) ≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
[(TR) + (TSU:DAT) = 1000 + 250 = 1250 ns], for 100 kHz mode, before the SCL line is released.

DS41120B-page 178  2002 Microchip Technology Inc.

 PIC16C717/770/771
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not tested or
guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside
specified power supply range) and therefore outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ ) or
(mean - 3σ) respectively, where σ is a standard deviation, over the whole temperature range.
The FOSC IDD was determined using an external sinusoidal clock source with a peak amplitude ranging from VSS to VDD.

FIGURE 16-1: MAXIMUM IDD VS. FOSC OVER VDD (HS MODE)
6.0

5.0

4.0
5.5V

5.0V
IDD (mA)

3.0
4.5V

4.0V

2.0 3.5V

3.0V

2.5V
1.0

0.0
4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)

 2002 Microchip Technology Inc. DS41120B-page 179

PIC16C717/770/771
FIGURE 16-2: TYPICAL IDD VS. FOSC OVER VDD (HS MODE)
6.0

5.0

4.0

5.5V
IDD (mA)

5.0V
3.0
4.5V

4.0V

2.0 3.5V

3.0V

2.5V
1.0

0.0
4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)

FIGURE 16-3: MAXIMUM IDD VS. FOSC OVER VDD (XT MODE)
1.6

1.4

1.2

1.0
5.5V
IDD (mA)

5.0V
0.8

4.5V

0.6
4.0V

3.5V
0.4
3.0V

2.5V
0.2

0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FOSC (MHz)

DS41120B-page 180  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-4: TYPICAL IDD VS. FOSC OVER VDD (XT MODE)
1.4

1.2

1.0

5.5V
0.8
IDD (mA)

5.0V

4.5V
0.6

4.0V

0.4 3.5V

3.0V

2.5V
0.2

0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FOSC (MHz)

FIGURE 16-5: MAXIMUM IDD VS. FOSC OVER VDD (LP MODE)
0.140

0.120
5.5V

0.100
5.0V

0.080 4.5V
IDD (mA)

4.0V
0.060

3.5V

0.040
3.0V

2.5V

0.020

0.000
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
FOSC (MHz)

 2002 Microchip Technology Inc. DS41120B-page 181

PIC16C717/770/771
FIGURE 16-6: TYPICAL IDD VS. FOSC OVER VDD (LP MODE)
0.120

5.5V
0.100

5.0V

0.080

4.5V
IDD (mA)

0.060 4.0V

3.5V

0.040 3.0V

2.5V
0.020

0.000
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
FOSC (MHz)

FIGURE 16-7: MAXIMUM IDD VS. FOSC OVER VDD (EC MODE)
5.0

4.5

4.0

3.5

3.0
5.5V
IDD (mA)

2.5 5.0V

4.5V
2.0
4.0V

1.5 3.5V

3.0V
1.0 2.5V

0.5

0.0
0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)

DS41120B-page 182  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-8: TYPICAL IDD VS. FOSC OVER VDD (EC MODE)
4.5

4.0

3.5

3.0

2.5 5.5V
IDD (mA)

5.0V
2.0
4.5V

4.0V
1.5
3.5V
3.0V
1.0
2.5V

0.5

0.0
0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00
FOSC (MHz)

FIGURE 16-9: MAXIMUM IDD VS. FOSC OVER VDD (ER MODE)
1.6

1.4

1.2

R = 38.3 kΩ
R = 38.3 KΩ
1.0
IDD (mA)

0.8

0.6 R == 100
R kΩ
100KΩ

0.4 R == 200
R kΩ
200KΩ

R == 499 kΩ
499KΩ
R = 1 MΩ
0.2

0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

 2002 Microchip Technology Inc. DS41120B-page 183

PIC16C717/770/771
FIGURE 16-10: TYPICAL IDD VS. FOSC OVER VDD (ER MODE)

1.4

1.2

1.0
R
R == 38.3 kΩ
38.3KΩ

0.8
IDD (mA)

0.6

RR==100 kΩ
100KΩ

0.4
R
R==200
200KΩ
kΩ

R = 499 kΩ
499KΩ
0.2
R = 1 MΩ

0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

FIGURE 16-11: TYPICAL FOSC VS. VDD (ER MODE)

10.0

R = 38.3 kΩ
38.3KΩ

R = 100 kΩ
100 KΩ
Frequency (MHz)

1.0
R = 200 kΩ
200 KΩ

R = 499 kΩ
499 KΩ

R = 1 MΩ

0.1
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VVdd (V)
DD (V)

DS41120B-page 184  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-12: MAXIMUM IDD VS. VDD (INTRC 37 kHZ MODE)
1.00

0.90

0.80

0.70

0.60
IDD (mA)

0.50

0.40

0.30

0.20 Max (-40 °C)

0.10
Typ (25 °C)

0.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)

FIGURE 16-13: TYPICAL IDD VS. VDD (INTRC 37 kHZ MODE)

0.14

0.12

-40 °C

0.10

0.08
IDD (mA)

25 °C

0.06 85 °C

125 °C

0.04

0.02

0.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

 2002 Microchip Technology Inc. DS41120B-page 185

PIC16C717/770/771
FIGURE 16-14: INTERNAL RC FOSC VS. VDD OVER TEMPERATURE (37 kHZ)

0.060

0.055

0.050

0.045
FOSC (MHz)

Max (125 °C)

0.040

0.035 Typ (25 °C)

0.030

0.025 Min(-40° C)

0.020
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

FIGURE 16-15: MAXIMUM AND TYPICAL IDD VS. VDD (INTRC 4 MHz MODE)
1.6

1.4

1.2

Max (-40 °C)

IDD (mA)

1.0

Typ (25 °C)

0.8

0.6

0.4
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)

DS41120B-page 186  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-16: TYPICAL IDD VS. VDD (INTRC 4 MHz MODE)
1.4

1.3

1.2

1.1
125 °C

1.0
25 °C
85 °C
IDD (mA)

0.9

0.8

0.7

-40 °C
0.6

0.5

0.4
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (Volts)

FIGURE 16-17: INTERNAL RC FOSC VS. VDD OVER TEMPERATURE (4 MHz)

4.15

4.10

Max (125 °C)

4.05

Typ (25 °C)

4.00
FOSC (MHz)

3.95

3.90

Min (-40 °C)

3.85

3.80
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

 2002 Microchip Technology Inc. DS41120B-page 187

PIC16C717/770/771
FIGURE 16-18: MAXIMUM IPD VS. VDD (-40°C TO +125°C)

10

+125°C
1
IPD ( A)

P
+85°C

+25°C -40°C

0.1

0.01
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

DS41120B-page 188  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-19: TYPICAL AND MAXIMUM ∆IWDT VS. VDD (-40°C TO +125°C)

16.0

14.0

12.0

10.0 Max (-40°C)

IWDT ( A)

P Typ (25°C)
8.0

'
6.0

4.0

2.0

0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

 2002 Microchip Technology Inc. DS41120B-page 189

PIC16C717/770/771
FIGURE 16-20: TYPICAL AND MAXIMUM ∆ITMR1 VS. VDD (32 KHZ, -40°C TO +125°C)

150.0

130.0

110.0

Max (-40°C)
90.0
ITMR1 ( A)

P
Typ (25°C)

' 70.0

50.0

30.0

10.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

FIGURE 16-21: TYPICAL AND MAXIMUM ∆IVRL VS. VDD (-40°C TO +125°C)

350.0

330.0
Max (125°C)

310.0

290.0 Max (85°C)

270.0
IVRL ( A)

P
250.0

'
230.0

210.0
Typ (25°C)
190.0

170.0

150.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

DS41120B-page 190  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-22: TYPICAL AND MAXIMUM ∆IVRH VS. VDD (-40°C TO +125°C)

380.0

360.0

Max (125°C)
340.0

320.0
Max (85°C)
IVRH ( A)

300.0
P

' 280.0

260.0

240.0

220.0
Typ (25°C)

200.0
4.5 5.0 5.5
VDD (V)

FIGURE 16-23: TYPICAL AND MAXIMUM ∆ILVD VS. VDD (-40°C TO +125°C) (LVD TRIP = 3.0V)

75.0

70.0

65.0 Max (125°C)

60.0
Max (85°C)
ILVD ( A)

55.0
P

'50.0

45.0 Typ (25°C)

40.0

35.0

30.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

 2002 Microchip Technology Inc. DS41120B-page 191

PIC16C717/770/771
FIGURE 16-24: TYPICAL AND MAXIMUM ∆ILVD VS. VDD (-40°C TO +125°C) (LVD TRIP = 4.5V)

75.0

70.0

65.0 Max (125°C)

60.0

Max (85°C)

55.0
ILVD ( A)

' 50.0

45.0 Typ (25°C)

40.0

35.0

30.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

FIGURE 16-25: TYPICAL AND MAXIMUM ∆IBOR VS. VDD (-40°C TO +125°C) (VBOR = 2.5V)

90.0

Max (125°C)

80.0

70.0

Typ (25°C)
IBOR ( A)

P Max (125°C)
60.0

'

50.0 Typ (25°C)

40.0

Device in RESET
Reset Indeterminate Device in SLEEP
Sleep

30.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

DS41120B-page 192  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-26: TYPICAL AND MAXIMUM ∆IBOR VS. VDD (-40°C TO +125°C) (VBOR = 4.5V)

170.0

150.0

130.0

Max (125 °C)

110.0
IBOR ( A)

Typ (25 °C)

' 90.0

70.0 Max (125 °C)

50.0 Typ (25C)

Device in RESET
Reset Device in SLEEP
Sleep
Indeterminate
30.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

FIGURE 16-27: VOL VS. IOL (-40°C TO +125°C, VDD = 3.0V)

1.8

1.6

1.4

1.2

1.0
VOL (V)

Max (125°C)
0.8

0.6
Typ (25°C)

0.4
Min (-40°C)

0.2

0.0
0.0 5.0 10.0 15.0 20.0 25.0
IOL (mA)

 2002 Microchip Technology Inc. DS41120B-page 193

PIC16C717/770/771
FIGURE 16-28: VOL VS. IOL (-40°C TO +125°C, VDD = 5.0V)

1.0

0.9

0.8

0.7

Max (125°C)
0.6
VOL (V)

0.5

0.4 Typ (25°C)

0.3 Min (-40°C)

0.2

0.1

0.0
0.0 5.0 10.0 15.0 20.0 25.0
IOL (mA)

FIGURE 16-29: VOH VS. IOH (-40°C TO +125°C, VDD = 3.0V)

3.0

2.5

2.0
VOH (V)

Max (-40°C)
Min (125°C) Typ (25°C)

1.5

1.0

0.5
0.0 -2.0 -4.0 -6.0 -8.0 -10.0 -12.0 -14.0 -16.0
IOH (mA)

DS41120B-page 194  2002 Microchip Technology Inc.

 PIC16C717/770/771
FIGURE 16-30: VOH VS. IOH (-40°C TO +125°C, VDD = 5.0V)

5.0

4.5
Max (-40°C)

Typ (25°C)
4.0
VOH (V)

3.5 Min (125°C)

3.0

2.5

2.0
0.0 -5.0 -10.0 -15.0 -20.0 -25.0
IOH (mA)

FIGURE 16-31: MINIMUM AND MAXIMUM VIH/VIL VS. VDD (TTL INPUT,-40°C TO +125°C)

1.8

1.7

1.6

1.5 Max (-40°C)

1.4
VIL / VIH (V)

1.3

1.2

Min (125°C)
1.1

1.0

0.9

0.8
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

 2002 Microchip Technology Inc. DS41120B-page 195

PIC16C717/770/771
FIGURE 16-32: MINIMUM AND MAXIMUM VIH/VIL VS. VDD (ST INPUT,-40°C TO +125°C)

4.0

3.5

3.0

2.5
Max High (125°C)
VIL / VIH (V)

Min High (-40°C)

2.0

1.5
Max Low (-40°C)

Min Low (125°C)

1.0

0.5

0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

FIGURE 16-33: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD VS. VDD (-40°C TO +125°C)

35.0

30.0

Max (125°C)
25.0
WDT Period (mS)

Max (85°C)

20.0
Typ (25°C)

15.0

Min (-40°C)

10.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

DS41120B-page 196  2002 Microchip Technology Inc.

 PIC16C717/770/771
17.0 PACKAGING INFORMATION
17.1 Package Marking Information

18-Lead PDIP Example

XXXXXXXXXXXXXXXXX
PIC16C717/P
XXXXXXXXXXXXXXXXX
YYWWNNN 9917017

18-Lead CERDIP Windowed Example

XXXXXXXX PIC16C717/JW
XXXXXXXX
YYWWNNN 9905017

18-Lead SOIC Example

XXXXXXXXXXXX
XXXXXXXXXXXX PIC16C717/SO
XXXXXXXXXXXX
YYWWNNN 9910017

20-Lead PDIP Example

XXXXXXXXXXXXXXXXX PIC16C770/P
XXXXXXXXXXXXXXXXX
YYWWNNN 9917017

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.

* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.

 2002 Microchip Technology Inc. DS41120B-page 197

PIC16C717/770/771
17.1 Package Marking Information (Cont’d)

20-Lead SSOP Example

XXXXXXXXXXX PIC16C770
XXXXXXXXXXX 20I/SS
YYWWNNN 9917017

20-Lead CERDIP Windowed Example

XXXXXXXX PIC16C770/JW
XXXXXXXX
YYWWNNN 9905017

20-Lead SOIC Example

XXXXXXXXXXXXXXXXXXXXXXXX PIC16C771/SO
XXXXXXXXXXXXXXXXXXXXXXXX
YYWWNNN 9910017

DS41120B-page 198  2002 Microchip Technology Inc.

 PIC16C717/770/771
17.2 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

n 1 α

E A2

c L

A1
B1
β
B p
eB

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 18 18
Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .890 .898 .905 22.61 22.80 22.99
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007

 2002 Microchip Technology Inc. DS41120B-page 199

PIC16C717/770/771
17.3 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)

E1

W2 D

n 1

W1

A A2

c L

A1
eB B1
B p

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 18 18
Pitch p .100 2.54
Top to Seating Plane A .170 .183 .195 4.32 4.64 4.95
Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19
Standoff A1 .015 .023 .030 0.38 0.57 0.76
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Ceramic Pkg. Width E1 .285 .290 .295 7.24 7.37 7.49
Overall Length D .880 .900 .920 22.35 22.86 23.37
Tip to Seating Plane L .125 .138 .150 3.18 3.49 3.81
Lead Thickness c .008 .010 .012 0.20 0.25 0.30
Upper Lead Width B1 .050 .055 .060 1.27 1.40 1.52
Lower Lead Width B .016 .019 .021 0.41 0.47 0.53
Overall Row Spacing eB .345 .385 .425 8.76 9.78 10.80
Window Width W1 .130 .140 .150 3.30 3.56 3.81
Window Length W2 .190 .200 .210 4.83 5.08 5.33
*Controlling Parameter
JEDEC Equivalent: MO-036
Drawing No. C04-010

DS41120B-page 200  2002 Microchip Technology Inc.

 PIC16C717/770/771
17.4 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

E
p
E1

2
B n 1

h
α

45 °

c
A A2

φ
β L A1

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 18 18
Pitch p .050 1.27
Overall Height A .093 .099 .104 2.36 2.50 2.64
Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39
Standoff § A1 .004 .008 .012 0.10 0.20 0.30
Overall Width E .394 .407 .420 10.01 10.34 10.67
Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59
Overall Length D .446 .454 .462 11.33 11.53 11.73
Chamfer Distance h .010 .020 .029 0.25 0.50 0.74
Foot Length L .016 .033 .050 0.41 0.84 1.27
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .009 .011 .012 0.23 0.27 0.30
Lead Width B .014 .017 .020 0.36 0.42 0.51
Mold Draft Angle Top α 0 12 15 0 12 15
Mold Draft Angle Bottom β 0 12 15 0 12 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051

 2002 Microchip Technology Inc. DS41120B-page 201

PIC16C717/770/771
17.5 20-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

n 1 α

A A2

c L

A1
β B1
eB B p

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 20 20
Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .295 .310 .325 7.49 7.87 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D 1.025 1.033 1.040 26.04 26.24 26.42
Tip to Seating Plane L .120 .130 .140 3.05 3.30 3.56
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .055 .060 .065 1.40 1.52 1.65
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-019

DS41120B-page 202  2002 Microchip Technology Inc.

 PIC16C717/770/771
17.6 20-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)

DRAWING NOT AVAILABLE

 2002 Microchip Technology Inc. DS41120B-page 203

PIC16C717/770/771
17.7 20-Lead Plastic Small Outline (SO) – Wide, 300 mi (SOIC)

E1
p

2
B n 1

h
α
45 °

c
A A2

φ
β L A1

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 20 20
Pitch p .050 1.27
Overall Height A .093 .099 .104 2.36 2.50 2.64
Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39
Standoff § A1 .004 .008 .012 0.10 0.20 0.30
Overall Width E .394 .407 .420 10.01 10.34 10.67
Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59
Overall Length D .496 .504 .512 12.60 12.80 13.00
Chamfer Distance h .010 .020 .029 0.25 0.50 0.74
Foot Length L .016 .033 .050 0.41 0.84 1.27
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .009 .011 .013 0.23 0.28 0.33
Lead Width B .014 .017 .020 0.36 0.42 0.51
Mold Draft Angle Top α 0 12 15 0 12 15
Mold Draft Angle Bottom β 0 12 15 0 12 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-094

DS41120B-page 204  2002 Microchip Technology Inc.

 PIC16C717/770/771
17.8 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)

E1
p

B 2
n 1

c
A A2

L A1
β

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 20 20
Pitch p .026 0.65
Overall Height A .068 .073 .078 1.73 1.85 1.98
Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83
Standoff § A1 .002 .006 .010 0.05 0.15 0.25
Overall Width E .299 .309 .322 7.59 7.85 8.18
Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38
Overall Length D .278 .284 .289 7.06 7.20 7.34
Foot Length L .022 .030 .037 0.56 0.75 0.94
Lead Thickness c .004 .007 .010 0.10 0.18 0.25
Foot Angle φ 0 4 8 0.00 101.60 203.20
Lead Width B .010 .013 .015 0.25 0.32 0.38
Mold Draft Angle Top α 0 5 10 0 5 10
Mold Draft Angle Bottom β 0 5 10 0 5 10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072

 2002 Microchip Technology Inc. DS41120B-page 205

PIC16C717/770/771
NOTES:

DS41120B-page 206  2002 Microchip Technology Inc.

 PIC16C717/770/771
APPENDIX A: REVISION HISTORY
Version Date Revision Description
A 09/14/99 This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16C7X Data Sheet, DS30390E.
B 2/8/02 Electrical Characteristics tables completed and characteristics graphs added.
MSSP I2C (Section 9.2) rewritten. General minor changes and corrections.

 2002 Microchip Technology Inc. DS41120B-page 207

PIC16C717/770/771
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Difference PIC16C717 PIC16C770 PIC16C771

Program Memory 2K 2K 4K

A/D 6 channels, 10 bits 6 channels, 12 bits 6 channels, 12 bits

Dedicated AVDD Not available Available Available

and AVSS

Packages 18-pin PDIP, 18-pin windowed 20-pin PDIP, 20-pin 20-pin PDIP, 20-pin windowed
CERDIP, 18-pin SOIC, windowed CERDIP, 20-pin CERDIP, 20-pin SOIC,
20-pin SSOP SOIC, 20-pin SSOP 20-pin SSOP

DS41120B-page 208  2002 Microchip Technology Inc.

 PIC16C717/770/771
INDEX
A C
A/D .................................................................................... 105 Capture (ECCP Module)..................................................... 54
A/D Converter Enable (ADIE Bit) ................................ 17 Block Diagram ............................................................ 54
ADCON0 Register..................................................... 105 CCPR1H:CCPR1L Registers ..................................... 54
ADCON1 Register............................................. 105, 107 Changing Between Capture Prescalers ..................... 54
ADRES Register ....................................................... 105 ECCP Pin Configuration ............................................. 54
Block Diagram........................................................... 109 Software Interrupt ....................................................... 54
Configuring Analog Port............................................ 108 Timer1 Mode Selection............................................... 54
Conversion time ........................................................ 115 Capture/Compare/PWM (ECCP)
Conversions .............................................................. 111 Capture Mode. See Capture
converter characteristics ................... 164, 165, 166, 170 Compare Mode. See Compare
Faster Conversion - Lower Resolution Tradeoff ....... 115 PWM Mode. See PWM
Internal Sampling Switch (Rss) Impedence .............. 113 CCP1CON .......................................................................... 13
Operation During Sleep ............................................ 116 CCP2CON .......................................................................... 13
Sampling Requirements............................................ 113 CCPR1H Register......................................................... 11, 13
Sampling Time .......................................................... 113 CCPR1L Register ............................................................... 13
Source Impedance.................................................... 113 CCPR2H Register............................................................... 13
Special Event Trigger (ECCP) .................................... 55 CCPR2L Register ............................................................... 13
A/D Conversion Clock ....................................................... 110 CKE .................................................................................... 66
ACK..................................................................................... 77 CKP .................................................................................... 67
Acknowledge Data bit, AKD ................................................ 69 Clock Polarity Select bit, CKP............................................. 67
Acknowledge Sequence Enable bit, AKE ........................... 69 Code Examples
Acknowledge Status bit, AKS ............................................. 69 Loading the SSPBUF register .................................... 71
ACKSTAT ........................................................................... 87 Code Protection ........................................................ 117, 131
ADCON0 Register............................................................. 105 Compare (ECCP Module)................................................... 54
ADCON1 Register..................................................... 105, 107 Block Diagram ............................................................ 55
ADRES.............................................................................. 105 CCPR1H:CCPR1L Registers ..................................... 54
ADRES Register ........................................... 11, 12, 105, 116 ECCP Pin Configuration ............................................. 54
AKD..................................................................................... 69 Software Interrupt ....................................................... 55
AKE ..................................................................................... 69 Special Event Trigger ........................................... 49, 55
AKS ..................................................................................... 69 Timer1 Mode Selection............................................... 54
Analog-to-Digital Converter. See A/D Configuration Bits ............................................................. 117
Application Note AN578, "Use of the SSP Module D
in the I2C Multi-Master Environment." ............................. 84
D/A...................................................................................... 66
Architecture
Data Memory ........................................................................ 9
PIC16C717/PIC16C717 Block Diagram ....................... 5
Bank Select (RP Bits) ............................................. 9, 14
PIC16C770/771/PIC16C770/771 Block Diagram ......... 6
General Purpose Registers .......................................... 9
Assembler
Register File Map ....................................................... 10
MPASM Assembler................................................... 141
Special Function Registers......................................... 11
B Data/Address bit, D/A ......................................................... 66
Banking, Data Memory ................................................... 9, 14 DC Characteristics
Baud Rate Generator .......................................................... 84 PIC16C717/770/771 ................................. 150, 151, 153
BF ..................................................................... 66, 77, 87, 89 Development Support ....................................................... 141
Block Diagrams Device Differences............................................................ 208
Baud Rate Generator.................................................. 84 Direct Addressing ............................................................... 23
I2C Master Mode......................................................... 83 E
I2C Module .................................................................. 76
Enhanced Capture/Compare/PWM (ECCP)
RA3:RA0 and RA5 Port Pins .................... 26, 28, 29, 35
CCP1
SSP (I2C Mode) .......................................................... 76
CCPR1H Register .............................................. 53
SSP (SPI Mode).......................................................... 70
CCPR1L Register ............................................... 53
BOR. See Brown-out Reset
Enable (CCP1IE Bit)........................................... 17
BRG .................................................................................... 84
Timer Resources ........................................................ 54
Brown-out Reset (BOR) .................................... 117, 123, 124
Errata .................................................................................... 3
Buffer Full bit, BF ................................................................ 77
External Power-on Reset Circuit....................................... 122
Buffer Full Status bit, BF ..................................................... 66
Bus Arbitration .................................................................... 94 F
Bus Collision During a RESTART Condition....................... 97 Firmware Instructions ....................................................... 133
Bus Collision During a Start Condition ................................ 95 FSR Register .......................................................... 11, 12, 13
Bus Collision During a Stop Condition ................................ 98 G
Bus Collision Section .......................................................... 94
GCE .................................................................................... 69
General Call Address Sequence ........................................ 82
General Call Address Support ............................................ 82
General Call Enable bit, GCE ............................................. 69

 2002 Microchip Technology Inc. DS41120B-page 209

PIC16C717/770/771
I BTFSS ...................................................................... 136
I/O Ports .............................................................................. 25 CALL......................................................................... 136
I2C ....................................................................................... 76 CLRF ........................................................................ 136
I2C Master Mode Reception................................................ 89 CLRW ....................................................................... 136
I2C Master Mode Restart Condition .................................... 86 CLRWDT .................................................................. 136
I2C Mode Selection ............................................................. 76 COMF ....................................................................... 137
I2C Module DECF ........................................................................ 137
Acknowledge Sequence timing ................................... 91 DECFSZ ................................................................... 137
Addressing .................................................................. 77 GOTO ....................................................................... 137
Baud Rate Generator .................................................. 84 INCF ......................................................................... 137
Block Diagram............................................................. 83 INCFSZ..................................................................... 137
BRG Block Diagram .................................................... 84 IORLW ...................................................................... 138
BRG Reset due to SDA Collision ................................ 96 IORWF...................................................................... 138
BRG Timing ................................................................ 85 MOVF ....................................................................... 138
Bus Arbitration ............................................................ 94 MOVLW .................................................................... 138
Bus Collision ............................................................... 94 MOVWF .................................................................... 138
Acknowledge....................................................... 94 NOP .......................................................................... 138
Restart Condition ................................................ 97 RETFIE ..................................................................... 139
Restart Condition Timing (Case1)....................... 97 RETLW ..................................................................... 139
Restart Condition Timing (Case2)....................... 97 RETURN................................................................... 139
Start Condition .................................................... 95 RLF ........................................................................... 139
Start Condition Timing .................................. 95, 96 RRF .......................................................................... 139
Stop Condition .................................................... 98 SLEEP ...................................................................... 139
Stop Condition Timing (Case1)........................... 98 SUBLW ..................................................................... 140
Stop Condition Timing (Case2)........................... 98 SUBWF..................................................................... 140
Transmit Timing .................................................. 94 SWAPF ..................................................................... 140
Bus Collision timing..................................................... 94 XORLW .................................................................... 140
Clock Arbitration.......................................................... 93 XORWF .................................................................... 140
Clock Arbitration Timing (Master Transmit)................. 93 Summary Table ........................................................ 134
Conditions to not give ACK Pulse ............................... 77 INT Interrupt (RB0/INT). See Interrupt Sources
General Call Address Support .................................... 82 INTCON .............................................................................. 13
Master Mode ............................................................... 83 INTCON Register................................................................ 16
Master Mode 7-bit Reception timing ........................... 90 GIE Bit ........................................................................ 16
Master Mode Operation .............................................. 84 INTE Bit ...................................................................... 16
Master Mode Start Condition ...................................... 85 INTF Bit ...................................................................... 16
Master Mode Transmission......................................... 87 PEIE Bit ...................................................................... 16
Master Mode Transmit Sequence ............................... 84 RBIE Bit ...................................................................... 16
Multi-Master Communication ...................................... 94 RBIF Bit ................................................................ 16, 33
Multi-master Mode ...................................................... 84 T0IE Bit ....................................................................... 16
Operation .................................................................... 76 T0IF Bit ....................................................................... 16
Repeat Start Condition timing ..................................... 86 Inter-Integrated Circuit (I2C) ............................................... 65
Slave Mode ................................................................. 76 internal sampling switch (Rss) impedence ....................... 113
Slave Reception .......................................................... 78 Interrupt Sources ...................................................... 117, 127
Slave Transmission..................................................... 80 Block Diagram .......................................................... 127
SSPBUF...................................................................... 76 Capture Complete (ECCP) ......................................... 54
Stop Condition Receive or Transmit timing................. 92 Compare Complete (ECCP) ....................................... 55
Stop Condition timing .................................................. 92 RB0/INT Pin, External............................................... 128
Waveforms for 7-bit Reception ................................... 78 TMR0 Overflow................................................... 46, 128
Waveforms for 7-bit Transmission .............................. 80 TMR1 Overflow..................................................... 47, 49
I2C Slave Mode ................................................................... 76 TMR2 to PR2 Match ................................................... 52
ICEPIC In-Circuit Emulator ............................................... 142 TMR2 to PR2 Match (PWM) ................................. 51, 56
ID Locations .............................................................. 117, 131 Interrupts
In-Circuit Serial Programming (ICSP) ....................... 117, 131 Synchronous Serial Port Interrupt............................... 18
INDF.................................................................................... 13 Interrupts, Context Saving During..................................... 128
INDF Register ............................................................... 11, 12 Interrupts, Enable Bits
Indirect Addressing ............................................................. 23 A/D Converter Enable (ADIE Bit)................................ 17
FSR Register ................................................................ 9 CCP1 Enable (CCP1IE Bit) .................................. 17, 54
Instruction Format ............................................................. 133 Global Interrupt Enable (GIE Bit) ........................ 16, 127
Instruction Set ................................................................... 133 Interrupt-on-Change (RB7:RB4) Enable
ADDLW ..................................................................... 135 (RBIE Bit)........................................................ 16, 128
ADDWF ..................................................................... 135 Peripheral Interrupt Enable (PEIE Bit) ........................ 16
ANDLW ..................................................................... 135 PSP Read/Write Enable (PSPIE Bit) .......................... 17
ANDWF ..................................................................... 135 RB0/INT Enable (INTE Bit) ......................................... 16
BCF ........................................................................... 135 SSP Enable (SSPIE Bit) ............................................. 17
BSF ........................................................................... 135 TMR0 Overflow Enable (T0IE Bit) .............................. 16
BTFSC ...................................................................... 136 TMR1 Overflow Enable (TMR1IE Bit)......................... 17

DS41120B-page 210  2002 Microchip Technology Inc.

 PIC16C717/770/771
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 17 PICDEM 3 Low Cost PIC16CXXX
USART Receive Enable (RCIE Bit) ...................... 17, 18 Demonstration Board.................................................... 144
Interrupts, Flag Bits PICSTART Plus Entry Level
CCP1 Flag (CCP1IF Bit) ............................................. 54 Development Programmer............................................ 143
Interrupt on Change (RB7:RB4) Flag PIE1 Register ..................................................................... 17
(RBIF Bit) .................................................. 16, 33, 128 ADIE Bit ...................................................................... 17
RB0/INT Flag (INTF Bit).............................................. 16 CCP1IE Bit ................................................................. 17
TMR0 Overflow Flag (T0IF Bit) ........................... 16, 128 PSPIE Bit.................................................................... 17
INTRC Mode ..................................................................... 120 RCIE Bit................................................................ 17, 18
K SSPIE Bit.................................................................... 17
TMR1IE Bit ................................................................. 17
KEELOQ Evaluation and Programming Tools .................... 144
TMR2IE Bit ................................................................. 17
L PIE2 Register ..................................................................... 19
LVDCON ........................................................................... 101 Pinout Descriptions
M PIC16C770 ................................................................... 7
PIC16C770/771 ............................................................ 7
Master Clear (MCLR)
PIC16C771 ................................................................... 7
MCLR Reset, Normal Operation ............... 121, 123, 124
PIR1 Register ..................................................................... 18
MCLR Reset, SLEEP................................ 121, 123, 124
PIR2 Register ..................................................................... 20
Memory Organization
Pointer, FSR ....................................................................... 23
Data Memory ................................................................ 9
POR. See Power-on Reset
Program Memory .......................................................... 9
PORTA ............................................................................... 13
MPLAB C17 and MPLAB C18 C Compilers...................... 141
Initialization................................................................. 26
MPLAB ICD In-Circuit Debugger ...................................... 143
PORTA Register......................................................... 25
MPLAB ICE High Performance Universal In-Circuit
TRISA Register........................................................... 25
Emulator with MPLAB IDE ............................................ 142
PORTA Register ......................................................... 11, 116
MPLAB Integrated Development Environment Software .. 141
PORTB ............................................................................... 13
MPLINK Object Linker/MPLIB Object Librarian ................ 142
Initialization................................................................. 33
Multi-Master Communication .............................................. 94
PORTB Register......................................................... 33
Multi-Master Mode .............................................................. 84
Pull-up Enable (RBPU Bit).......................................... 15
O RB0/INT Edge Select (INTEDG Bit) ........................... 15
OPCODE Field Descriptions ............................................. 133 RB0/INT Pin, External .............................................. 128
OPTION_REG Register ...................................................... 15 RB7:RB4 Interrupt on Change.................................. 128
INTEDG Bit ................................................................. 15 RB7:RB4 Interrupt on Change Enable
PS Bits .................................................................. 15, 45 (RBIE Bit)........................................................ 16, 128
PSA Bit.................................................................. 15, 45 RB7:RB4 Interrupt on Change Flag
RBPU Bit..................................................................... 15 (RBIF Bit).................................................. 16, 33, 128
T0CS Bit................................................................ 15, 45 TRISB Register........................................................... 33
T0SE Bit................................................................ 15, 45 PORTB Register ......................................................... 11, 116
Oscillator Configuration..................................................... 119 Postscaler, Timer2
CLKOUT ................................................................... 120 Select (TOUTPS Bits)................................................. 51
Dual Speed Operation for ER and Postscaler, WDT................................................................. 45
INTRC Modes ....................................................... 120 Assignment (PSA Bit) ........................................... 15, 45
EC ..................................................................... 119, 123 Block Diagram ............................................................ 46
ER ..................................................................... 119, 123 Rate Select (PS Bits)............................................ 15, 45
ER Mode ................................................................... 120 Switching Between Timer0 and WDT ......................... 46
HS ..................................................................... 119, 123 Power-down Mode. See SLEEP
INTRC ............................................................... 119, 123 Power-on Reset (POR)..................... 117, 121, 122, 123, 124
LP...................................................................... 119, 123 Oscillator Start-up Timer (OST)........................ 117, 122
XT ..................................................................... 119, 123 Power Control (PCON) Register............................... 123
Oscillator, Timer1 .......................................................... 47, 49 Power-down (PD Bit) .................................................. 14
Oscillator, WDT ................................................................. 129 Power-on Reset Circuit, External ............................. 122
P Power-up Timer (PWRT) .................................. 117, 122
Time-out (TO Bit)........................................................ 14
P.......................................................................................... 66
Time-out Sequence .................................................. 123
Packaging ......................................................................... 197
Time-out Sequence on Power-up..................... 125, 126
Paging, Program Memory ............................................... 9, 22
PR2 Register ...................................................................... 12
Parallel Slave Port (PSP)
Prescaler, Capture.............................................................. 54
Read/Write Enable (PSPIE Bit)................................... 17
Prescaler, Timer0 ............................................................... 45
PCL Register................................................................. 11, 12
Assignment (PSA Bit) ........................................... 15, 45
PCLATH Register ................................................... 11, 12, 13
Block Diagram ............................................................ 46
PCON Register ........................................................... 21, 123
Rate Select (PS Bits)............................................ 15, 45
PICDEM 1 Low Cost PICmicro
Switching Between Timer0 and WDT ......................... 46
Demonstration Board .................................................... 143
Prescaler, Timer1 ............................................................... 48
PICDEM 17 Demonstration Board .................................... 144
Select (T1CKPS Bits) ................................................. 47
PICDEM 2 Low Cost PIC16CXX
Demonstration Board .................................................... 143

 2002 Microchip Technology Inc. DS41120B-page 211

PIC16C717/770/771
Prescaler, Timer2................................................................ 57 S
Select (T2CKPS Bits).................................................. 51 S ......................................................................................... 66
PRO MATE II Universal Device Programmer ................... 143 SAE..................................................................................... 69
Program Counter SCK .................................................................................... 70
PCL Register............................................................... 22 SCL..................................................................................... 76
PCLATH Register ............................................... 22, 128 SDA .................................................................................... 76
Reset Conditions....................................................... 123 SDI...................................................................................... 70
Program Memory .................................................................. 9 SDO .................................................................................... 70
Interrupt Vector ............................................................. 9 Serial Data In, SDI .............................................................. 70
Paging ..................................................................... 9, 22 Serial Data Out, SDO ......................................................... 70
Program Memory Map .................................................. 9 Slave Select Synchronization ............................................. 73
READ (PMR)............................................................... 43 Slave Select, SS ................................................................. 70
Reset Vector ................................................................. 9 SLEEP .............................................................. 117, 121, 130
Program Verification.......................................................... 131 SMP .................................................................................... 66
Programmable Brown-out Reset (PBOR) ................. 121, 122 Software Simulator (MPLAB SIM) .................................... 142
Programming, Device Instructions .................................... 133 SPE..................................................................................... 69
PWM (CCP Module) Special Event Trigger. See Compare
TMR2 to PR2 Match ................................................... 51 Special Features of the CPU ............................................ 117
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 17 Special Function Registers ................................................. 11
PWM (ECCP Module) ......................................................... 56 PIC16C717 ................................................................. 11
Block Diagram............................................................. 56 PIC16C717/770/771 ................................................... 11
CCPR1H:CCPR1L Registers ...................................... 56 PIC16C770 ................................................................. 11
Duty Cycle................................................................... 57 PIC16C771 ................................................................. 11
Output Diagram........................................................... 57 Speed, Operating.................................................................. 1
Period.......................................................................... 56 SPI
TMR2 to PR2 Match ................................................... 56 Master Mode............................................................... 72
Q Serial Clock................................................................. 70
Q Clock ............................................................................... 57 Serial Data In .............................................................. 70
Serial Data Out ........................................................... 70
R Serial Peripheral Interface (SPI) ................................. 65
R/W ..................................................................................... 66 Slave Select................................................................ 70
R/W bit ................................................................................ 80 SPI clock..................................................................... 72
R/W bit ................................................................................ 78 SPI Mode .................................................................... 70
R/W bit ................................................................................ 77 SPI Clock Edge Select, CKE .............................................. 66
RAM. See Data Memory SPI Data Input Sample Phase Select, SMP ....................... 66
RCE,Receive Enable bit, RCE ............................................ 69 SPI Master/Slave Connection............................................. 71
RCREG ............................................................................... 13 SPI Module
RCSTA Register.................................................................. 13 Master/Slave Connection............................................ 71
Read/Write bit, R/W ............................................................ 66 Slave Mode................................................................. 73
Receive Overflow Indicator bit, SSPOV .............................. 67 Slave Select Synchronization ..................................... 73
REFCON ........................................................................... 102 Slave Synch Timnig .................................................... 73
Register File .......................................................................... 9 SS ....................................................................................... 70
Register File Map ................................................................ 10 SSP..................................................................................... 65
Registers Block Diagram (SPI Mode) ......................................... 70
FSR Summary ............................................................ 13 Enable (SSPIE Bit) ..................................................... 17
INDF Summary ........................................................... 13 SPI Mode .................................................................... 70
INTCON Summary ...................................................... 13 SSPADD ..................................................................... 77
PCL Summary............................................................. 13 SSPBUF ............................................................... 72, 76
PCLATH Summary ..................................................... 13 SSPCON .................................................................... 67
PORTB Summary ....................................................... 13 SSPCON2 ............................................................ 69, 70
SSPSTAT............................................................ 66, 101 SSPSR ................................................................. 72, 77
STATUS Summary ..................................................... 13 SSPSTAT ..................................................... 66, 76, 101
TMR0 Summary .......................................................... 13 TMR2 Output for Clock Shift................................. 51, 52
TRISB Summary ......................................................... 13 SSP I2C
Reset......................................................................... 117, 121 SSP I2C Operation ..................................................... 76
Block Diagram........................................................... 121 SSP Module
Brown-out Reset (BOR). See Brown-out Reset (BOR) SPI Master Mode ........................................................ 72
MCLR Reset. See MCLR SPI Master./Slave Connection.................................... 71
Power-on Reset (POR). See Power-on Reset (POR) SPI Slave Mode .......................................................... 73
Reset Conditions for All Registers ............................ 124 SSPCON1 Register .................................................... 76
Reset Conditions for PCON Register........................ 123 SSP Overflow Detect bit, SSPOV....................................... 77
Reset Conditions for Program Counter ..................... 123 SSPADD Register............................................................... 12
Reset Conditions for STATUS Register .................... 123 SSPBUF ................................................................. 13, 76, 77
WDT Reset. See Watchdog Timer (WDT) SSPBUF Register ............................................................... 11
Restart Condition Enabled bit, RSE .................................... 69 SSPCON............................................................................. 67
Revision History ................................................................ 207 SSPCON Register .............................................................. 11
RSE..................................................................................... 69

DS41120B-page 212  2002 Microchip Technology Inc.

 PIC16C717/770/771
SSPCON1 ........................................................................... 76 Timer2
SSPCON2 ..................................................................... 69, 70 Block Diagram ............................................................ 52
SSPEN ................................................................................ 67 Postscaler. See Postscaler, Timer2
SSPIF............................................................................ 18, 78 PR2 Register ........................................................ 51, 56
SSPM .................................................................................. 68 Prescaler. See Prescaler, Timer2
SSPOV.................................................................... 67, 77, 89 SSP Clock Shift .................................................... 51, 52
SSPSTAT.............................................................. 66, 76, 101 T2CON Register ......................................................... 51
SSPSTAT Register ............................................................. 12 TMR2 Register ........................................................... 51
Stack ................................................................................... 22 TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 17
Start bit (S) .......................................................................... 66 TMR2 to PR2 Match Interrupt......................... 51, 52, 56
Start Condition Enabled bit, SAE ........................................ 69 Timing Diagrams
STATUS Register ................................................. 14, 15, 128 Acknowledge Sequence Timing ................................. 91
C Bit ............................................................................ 14 Baud Rate Generator with Clock Arbitration............... 85
DC Bit.................................................................... 14, 15 BRG Reset Due to SDA Collision............................... 96
IRP Bit......................................................................... 14 Brown-out Reset....................................................... 159
PD Bit.......................................................................... 14 Bus Collision
RP Bits ........................................................................ 14 Start Condition Timing ........................................ 95
TO Bit.......................................................................... 14 Bus Collision During a Restart Condition
Z Bit............................................................................. 14 (Case 1).................................................................. 97
Status Register ................................................................... 14 Bus Collision During a Restart Condition
Stop bit (P) .......................................................................... 66 (Case2)................................................................... 97
Stop Condition Enable bit ................................................... 69 Bus Collision During a Start Condition
Synchronous Serial Port ..................................................... 65 (SCL = 0) ................................................................ 96
Synchronous Serial Port Enable bit, SSPEN ...................... 67 Bus Collision During a Stop Condition........................ 98
Synchronous Serial Port Interrupt ....................................... 18 Bus Collision for Transmit and Acknowledge ............. 94
Synchronous Serial Port Mode Select bits, SSPM ............. 68 Capture/Compare/PWM ........................................... 161
T CLKOUT and I/O ...................................................... 157
External Clock Timing............................................... 157
T1CON ................................................................................ 13
I2C Bus Data............................................................. 177
T1CON Register ........................................................... 13, 47
I2C Master Mode First Start bit timing ........................ 85
T1CKPS Bits ............................................................... 47
I2C Master Mode Reception timing............................. 90
T1OSCEN Bit.............................................................. 47
I2C Master Mode Transmission timing ....................... 88
T1SYNC Bit................................................................. 47
Master Mode Transmit Clock Arbitration .................... 93
TMR1CS Bit ................................................................ 47
Power-up Timer ........................................................ 159
TMR1ON Bit................................................................ 47
Repeat Start Condition ............................................... 86
T2CON Register ........................................................... 13, 51
Reset ........................................................................ 159
T2CKPS Bits ............................................................... 51
Slave Synchronization ................................................ 73
TMR2ON Bit................................................................ 51
Start-up Timer........................................................... 159
TOUTPS Bits .............................................................. 51
Stop Condition Receive or Transmit ........................... 92
Timer0
Time-out Sequence on Power-up..................... 125, 126
Block Diagram............................................................. 45
Timer0 ...................................................................... 160
Clock Source Edge Select (T0SE Bit)................... 15, 45
Timer1 ...................................................................... 160
Clock Source Select (T0CS Bit)............................ 15, 45
Wake-up from SLEEP via Interrupt .......................... 131
Overflow Enable (T0IE Bit) ......................................... 16
Watchdog Timer ....................................................... 159
Overflow Flag (T0IF Bit)...................................... 16, 128
TMR0 .................................................................................. 13
Overflow Interrupt ............................................... 46, 128
TMR0 Register.................................................................... 11
Prescaler. See Prescaler, Timer0
TMR1H ............................................................................... 13
Timer1 ................................................................................. 47
TMR1H Register ................................................................. 11
Block Diagram............................................................. 48
TMR1L ................................................................................ 13
Capacitor Selection..................................................... 49
TMR1L Register.................................................................. 11
Clock Source Select (TMR1CS Bit) ............................ 47
TMR2 .................................................................................. 13
External Clock Input Sync (T1SYNC Bit) .................... 47
TMR2 Register.................................................................... 11
Module On/Off (TMR1ON Bit)..................................... 47
TRISA Register........................................................... 12, 116
Oscillator ............................................................... 47, 49
TRISB Register........................................................... 12, 116
Oscillator Enable (T1OSCEN Bit) ............................... 47
TXREG ............................................................................... 13
Overflow Enable (TMR1IE Bit).................................... 17
Overflow Interrupt ................................................. 47, 49 U
Prescaler. See Prescaler, Timer1 Update Address, UA ........................................................... 66
Special Event Trigger (ECCP) .............................. 49, 55 USART
T1CON Register ......................................................... 47 Receive Enable (RCIE Bit) ................................... 17, 18
TMR1H Register ......................................................... 47
TMR1L Register.......................................................... 47

 2002 Microchip Technology Inc. DS41120B-page 213

PIC16C717/770/771
W
W Register ........................................................................ 128
Wake-up from SLEEP ............................................... 117, 130
Interrupts ........................................................... 123, 124
MCLR Reset ............................................................. 124
Timing Diagram......................................................... 131
WDT Reset ............................................................... 124
Watchdog Timer (WDT) ............................................ 117, 129
Block Diagram........................................................... 129
Enable (WDTE Bit).................................................... 129
Postscaler. See Postscaler, WDT
Programming Considerations ................................... 129
RC Oscillator ............................................................. 129
Time-out Period ........................................................ 129
WDT Reset, Normal Operation ................. 121, 123, 124
WDT Reset, SLEEP .......................................... 123, 124
Waveform for General Call Address Sequence .................. 82
WCOL ................................................... 67, 85, 87, 89, 91, 92
WCOL Status Flag .............................................................. 85
Write Collision Detect bit, WCOL ........................................ 67
WWW, On-Line Support........................................................ 3

DS41120B-page 214  2002 Microchip Technology Inc.

 PIC16C717/770/771
ON-LINE SUPPORT Systems Information and Upgrade Hot Line
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Microchip provides on-line support on the Microchip
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The Microchip web site is available by using your

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The web site and file transfer site provide a variety of
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 2002 Microchip Technology Inc. Advance Information DS41120B-page215

PIC16C717/770/771
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Device: PIC16C717/770/771 Literature Number: DS41120B

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DS41120B-page216 Advance Information  2002 Microchip Technology Inc.

 PIC16C717/770/771
PIC16C717/770/771 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Examples:
Device Temperature Package Pattern a) PIC16C771/P Commercial Temp.,
Range PDIP package, normal VDD limits

Device PIC16C771 : VDD range 4.0V to 5.5V

PIC16C771T : VDD range 4.0V to 5.5V (Tape/Reel)
PIC16LC771 : VDD range 2.5V to 5.5V
PIC16LC771T: VDD range 2.5V to 5.5V (Tape/Reel)

Temperature Range: - = 0°C to +70°C

I = -40°C to +85°C
E = -40°C to +125°C

Package JW = Windowed CERDIP

SO = SOIC
P = PDIP
SS = SSOP

Pattern QTP, SQTP, Code or Special Requirements. Blank for OTP

and Windowed devices.

* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.

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 2002 Microchip Technology Inc. DS41120B-page 217

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WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC Japan
Microchip Technology Japan K.K.
Corporate Office Australia
Benex S-1 6F
2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd
3-18-20, Shinyokohama
Chandler, AZ 85224-6199 Suite 22, 41 Rawson Street
Kohoku-Ku, Yokohama-shi
Tel: 480-792-7200 Fax: 480-792-7277 Epping 2121, NSW
Kanagawa, 222-0033, Japan
Technical Support: 480-792-7627 Australia
Web Address: http://www.microchip.com Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain China - Beijing Korea
2355 West Chandler Blvd. Microchip Technology Consulting (Shanghai) Microchip Technology Korea
Chandler, AZ 85224-6199 Co., Ltd., Beijing Liaison Office 168-1, Youngbo Bldg. 3 Floor
Tel: 480-792-7966 Fax: 480-792-7456 Unit 915 Samsung-Dong, Kangnam-Ku
Bei Hai Wan Tai Bldg. Seoul, Korea 135-882
Atlanta No. 6 Chaoyangmen Beidajie Tel: 82-2-554-7200 Fax: 82-2-558-5934
500 Sugar Mill Road, Suite 200B Beijing, 100027, No. China Singapore
Atlanta, GA 30350 Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Singapore Pte Ltd.
Tel: 770-640-0034 Fax: 770-640-0307 200 Middle Road
China - Chengdu
Boston #07-02 Prime Centre
Microchip Technology Consulting (Shanghai)
2 Lan Drive, Suite 120 Singapore, 188980
Co., Ltd., Chengdu Liaison Office
Westford, MA 01886 Tel: 65-334-8870 Fax: 65-334-8850
Rm. 2401, 24th Floor,
Tel: 978-692-3848 Fax: 978-692-3821 Taiwan
Ming Xing Financial Tower
Chicago No. 88 TIDU Street Microchip Technology Taiwan
333 Pierce Road, Suite 180 Chengdu 610016, China 11F-3, No. 207
Itasca, IL 60143 Tel: 86-28-6766200 Fax: 86-28-6766599 Tung Hua North Road
Tel: 630-285-0071 Fax: 630-285-0075 Taipei, 105, Taiwan
China - Fuzhou
Dallas Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Microchip Technology Consulting (Shanghai)
4570 Westgrove Drive, Suite 160 Co., Ltd., Fuzhou Liaison Office
Addison, TX 75001 Unit 28F, World Trade Plaza
Tel: 972-818-7423 Fax: 972-818-2924 EUROPE
No. 71 Wusi Road
Detroit Fuzhou 350001, China Denmark
Tri-Atria Office Building Tel: 86-591-7503506 Fax: 86-591-7503521 Microchip Technology Nordic ApS
32255 Northwestern Highway, Suite 190 China - Shanghai Regus Business Centre
Farmington Hills, MI 48334 Microchip Technology Consulting (Shanghai) Lautrup hoj 1-3
Tel: 248-538-2250 Fax: 248-538-2260 Co., Ltd. Ballerup DK-2750 Denmark
Kokomo Room 701, Bldg. B Tel: 45 4420 9895 Fax: 45 4420 9910
2767 S. Albright Road Far East International Plaza France
Kokomo, Indiana 46902 No. 317 Xian Xia Road Microchip Technology SARL
Tel: 765-864-8360 Fax: 765-864-8387 Shanghai, 200051 Parc d’Activite du Moulin de Massy
Los Angeles Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 43 Rue du Saule Trapu
18201 Von Karman, Suite 1090 China - Shenzhen Batiment A - ler Etage
Irvine, CA 92612 91300 Massy, France
Microchip Technology Consulting (Shanghai)
Tel: 949-263-1888 Fax: 949-263-1338 Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Co., Ltd., Shenzhen Liaison Office
New York Rm. 1315, 13/F, Shenzhen Kerry Centre, Germany
150 Motor Parkway, Suite 202 Renminnan Lu Microchip Technology GmbH
Hauppauge, NY 11788 Shenzhen 518001, China Gustav-Heinemann Ring 125
Tel: 631-273-5305 Fax: 631-273-5335 Tel: 86-755-2350361 Fax: 86-755-2366086 D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
San Jose Hong Kong
Microchip Technology Inc. Microchip Technology Hongkong Ltd. Italy
2107 North First Street, Suite 590 Unit 901-6, Tower 2, Metroplaza Microchip Technology SRL
San Jose, CA 95131 223 Hing Fong Road Centro Direzionale Colleoni
Tel: 408-436-7950 Fax: 408-436-7955 Kwai Fong, N.T., Hong Kong Palazzo Taurus 1 V. Le Colleoni 1
Tel: 852-2401-1200 Fax: 852-2401-3431 20041 Agrate Brianza
Toronto
Milan, Italy
6285 Northam Drive, Suite 108 India Tel: 39-039-65791-1 Fax: 39-039-6899883
Mississauga, Ontario L4V 1X5, Canada Microchip Technology Inc.
Tel: 905-673-0699 Fax: 905-673-6509 India Liaison Office United Kingdom
Divyasree Chambers Arizona Microchip Technology Ltd.
1 Floor, Wing A (A3/A4) 505 Eskdale Road
No. 11, O’Shaugnessey Road Winnersh Triangle
Bangalore, 560 025, India Wokingham
Tel: 91-80-2290061 Fax: 91-80-2290062 Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820

01/18/02

DS41120B-page 218  2002 Microchip Technology Inc.