0% found this document useful (0 votes)
8 views127 pages

vhdl record

vhdl ,verilog

Uploaded by

partheepan118
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
8 views127 pages

vhdl record

vhdl ,verilog

Uploaded by

partheepan118
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 127

42130363_PRIYADHARSHINI.

DATE:
20.01.2025
STUDY ON VERIFICATION OF LOGIC
EXPT. NO: 01
GATES
PAGE NO: 1

AIM:

To develop the source code for logic gates using VHDL/VERILOG and obtain the
simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.
42130363_PRIYADHARSHINI.R

1. AND GATE:
EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUTS OUTPUT
A B Y
Y = A.B 0 0 0
0 1 0
1 0 0
1 1 1

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ANDGATE_363 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end ANDGATE_363;
architecture dataflow ANDGATE_363 is
begin
Y <= A AND B;
end dataflow;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

2. OR GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUTS OUTPUT
A B Y
Y = A+B 0 0 0
0 1 1
1 0 1
1 1 1

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ORGATE_363 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end ORGATE_363;
architecture dataflow ORGATE_363 is
begin
Y <= A OR B;
end dataflow;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

3. NAND GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUTS OUTPUT
A B Z
Z = (A.B)’ 0 0 1
0 1 1
1 0 1
1 1 0

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NANDGATE_363 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end NANDGATE_363;
architecture dataflow NANDGATE_363 is
begin
Z <= A NAND B;
end dataflow;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

4. NOR GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUTS OUTPUT
A B Q
Q = (A+B)’ 0 0 1
0 1 0
1 0 0
1 1 0

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NORGATE_363 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end NORGATE_363;
architecture dataflow NORGATE_363 is
begin
Y <= A NOR B;
end dataflow;

• SIMULATED OUTPUT;
42130363_PRIYADHARSHINI.R

5. XOR GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUTS OUTPUT
A B Y
Y = AB’ + A’B 0 0 0
0 1 1
1 0 1
1 1 0

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XORGATE_363 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC);
end XORGATE_363;
architecture dataflow XORGATE_363 is
begin
Y <= A XOR B;
end dataflow;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

6. XNOR GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUTS OUTPUT
A B Y
Y = (AB’ + A’B)’ 0 0 1
A 0 1 0
Y 1 0 0
B
1 1 1

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XNORGATE_363 is
port (A, B: in STD_LOGIC; Y: out STD_LOGIC); end
XNORGATE_363;
architecture dataflow XNORGATE_363 is
begin
Y <= A XNOR B;
end dataflow;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

7. NOT GATE:

EXPRESSION DIAGRAM OR SYMBOL TRUTH TABLE

INPUT OUTPUT
X Y
Y = (X)’
0 1
1 0

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NOTGATE_363 is
port (X: in STD_LOGIC; Y: out STD_LOGIC); end
NOTGATE_363;
architecture dataflow NOTGATE_363 is
begin
Y <= NOT X;
end dataflow;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

VERILOG CODES:

1. AND GATE:

module and1(a,b,c);
input a,b;
output c;
assign c = a&b;
endmodule

2. OR GATE:

module or1(a,b,c);
input a,b;
output c;
assign c = a|b;
endmodule

3. NAND GATE:

module nand1(a,b,c);
input a,b;
output c;
assign c = ~(a&b);
endmodule
42130363_PRIYADHARSHINI.R

4. NOR GATE:

module nor1(a,b,c);
input a,b;
output c;
assign c = ~(a|b);
endmodule

5. XOR GATE:

module xor1(a,b,c);
input a,b;
output c;
assign c = a^b;
endmodule

6. XNOR GATE:

module xnor1(a,b,c);
input a,b;
output c;
assign c = ~(a^b);
endmodule
42130363_PRIYADHARSHINI.R

7. NOT GATE:

module and1(a,b);
input a;
output b;
assign b = ~a;
endmodule

RESULT:

The output of Logic Gates is verified by stimulating and synthesizing the VHDL
/VERILOG code.
42130363_PRIYADHARSHINI.R

DATE:
10.02.2025
EXPT. NO: 02 ADDERS AND SUBTRACTORS
PAGE NO:

AIM:

To develop the source code for adders and subtractors using VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. HALF ADDER:

• CIRCUIT DIAGRAM:
42130363_PRIYADHARSHINI.R

• EXPRESSIONS:

 SUM (S) = A XOR B


 CARRY (C) = A AND B

• TRUTH TABLE:

INPUTS OUTPUTS

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

• VHDL CODE:

 DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFADDER_363 is
port (A, B: in STD_LOGIC; S, C: out STD_LOGIC);
end HALFADDER_363;
architecture dataflow of HALFADDER_363 is
begin
S <= A XOR B;
C <= A AND B;
end dataflow;
 STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALFADDER_363 is
42130363_PRIYADHARSHINI.R

port (A, B: in STD_LOGIC; S, C: out STD_LOGIC);


end HALFADDER_363;
architecture structural of HALFADDER_363 is
component xor1
port (a1, b1: in STD_LOGIC; c1: out STD_LOGIC);
end component;
component and1
port (a2, b2: in STD_LOGIC; c2: out STD_LOGIC);
end component;
begin
ag: and1 port map(A, B, C);
ng: xor1 port map(A, B, S);
end structural;

--COMPONENT SOURCE CODE


--XOR1:
entity xor1 is
port (a1, b1: in STD_LOGIC; c1: out STD_LOGIC);
end xor1;
architecture dataflow of xor1 is
begin
c1 <= a1 XOR b1;
end dataflow;
--AND1:
entity and1 is
port (a2, b2: in STD_LOGIC; c2: out STD_LOGIC);
end and1;
architecture dataflow of and1 is
begin
c2 <= a2 AND b2;
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFADDER_363 is
port (A, B: in STD_LOGIC; S, C: out STD_LOGIC);
end HALFADDER_363;
architecture behavioural of HALFADDER_363 is
begin
process (A, B)
begin
42130363_PRIYADHARSHINI.R

S <= A XOR B;
C <= A AND B;
end process;
end behavioural;

 SIMULATED OUTPUT:

VERILOG CODE:

1. DATAFLOW MODELING:

module ha_d363(a,b,s,c)
input a,b;
output s,c;
assign s = a^b;
assign c = a&b;
endmodule

2. STRUCTURAL MODELING:

module ha_d363(a,b,s,c);
input a,b;
output s,c;
xor(s,a,b)
and(c,a,b)
endmodule

3. BEHAVIOURAL MODELING:
module ha_d363(a,b,s,c);
input a,b;
output reg s,c;
always @(*)
begin
s = a+b;
assign c = a&b;
end
endmodule
42130363_PRIYADHARSHINI.R

SIMULATED OUTPUT:

2. FULL ADDER:

 CIRCUIT DIAGRAM:

 EXPRESSIONS:

 SUM (S) = X XOR Y XOR Cin


 CARRY (C) = (X AND Y) OR (X AND Cin) OR (Y AND Cin)
42130363_PRIYADHARSHINI.R


TRUTH TABLE:

INPUTS OUTPUTS

X Y Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1

VHDL CODE:

 DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLADDER_363 is
port (X, Y, Cin: in std_logic; S,
Cout: out std_logic);
end FULLADDER_363;
architecture dataflow of FULLADDER_363 is
begin
S <= (X XOR Y) XOR Cin;
Cout <= ((X AND Y) OR (Y AND Cin)) OR (Cin AND X);
end dataflow;
42130363_PRIYADHARSHINI.R


 STRUCTURAL MODELLING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLADDER_363 is
port (X, Y, Cin: in std_logic;
S,Cout: out std_logic);
end
architecture structural of FULLADDER_363 is
component xor1
port (a1, b1, c1: in std_logic; d1:out std_logic);
end component;
component and1
port (a2, b2: in std_logic; c2:out std_logic);
end component;
component or1
port (a3, b3: in std_logic; c3:out std_logic);
end component;
signal s1, s2, s3: std_logic;
begin
x1: xor1 port map (X, Y, Cin, S);
a1: and1 port map (X, Y, s1);
a2: and1 port map (X, Y, s2);
a3: and1 port map (Cin, X, s3);
o1: or1 port map (s1, s2, s3, Cout);
end structural;

--COMPONENT SOURCE CODE:


--XOR1
entity xor1 is
port (a1, b1, c1: in std_logic;
d1: out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
d1<= <= a1 XOR b1 XOR c1;
end dataflow;

--AND1
entity and1 is
port (a2, b2: in std_logic;
c2: out std_logic);
end and1;
42130363_PRIYADHARSHINI.R

architecture dataflow of and1 is


begin
c2<= <= a2 AND b2;
end dataflow;

--OR1
entity or1 is
port (a3, b3, c3: in std_logic;
d3: out std_logic);
end or1;
architecture dataflow of or1 is
begin
d3 <= (a3 OR b3) OR c3;
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL
;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FULLADDER_363 is
port (X, Y, Cin: in std_logic;
S, Cout: out std_logic);
end FULLADDER_363;
architecture behavioural of
FULLADDER_363 is begin
process (X, Y,
Cin) begin
S <= (X XOR Y) XOR Cin;
Cout <= ((X AND Y) OR (Y AND Cin)) OR (Cin AND X);
end process;
end behavioural;
42130363_PRIYADHARSHINI.R

• SIMULATED OUTPUT:

• VERILOG CODE:

 DATAFLOW MODELING:
module fa_d214(x,y,z,s,c);
input x,y,z;
output s,c;
assign s=x^y^z;
assign c=(x&y)|(y&z)|(z&x);
endmodule

 STRUCTURAL MODELLING:

module fa_s363(x,y,z,s,c);
input x,y,z; output s,c;
wire i,j,k; xor(s,x,y,z);
and
a1(i,x,y),
a2(j,y,z),
a3(k,z,x);
or(c,i,j,k);
endmodule

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLADDER_363 is
port (X, Y, Cin: in std_logic; S, Cout: out std_logic);
end FULLADDER_363;
architecture behavioural of FULLADDER_363 is
begin
process (X, Y, Cin)
begin S <= (X XOR Y) XOR Cin;
42130363_PRIYADHARSHINI.R

Cout <= ((X AND Y) OR (Y AND Cin)) OR (Cin AND X);


end process;
end behavioural;

• SIMULATED OUTPUT:

3. HALF SUBTRACTOR:

• CIRCUIT DIAGRAM:

• EXPRESSIONS:

 Difference (D) = A XOR B


 Borrow (Bo) = (NOT A) AND B
42130363_PRIYADHARSHINI.R

• TRUTH TABLE:

INPUTS OUTPUTS

A B D Bo

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

• VHDL CODE:

 DATAFLOW MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFSUBT_363 is
port (A, B: in std_logic;
D, Bo: out std_logic);
end HALFSUBT_363;
architecture dataflow of HALFSUBT_363 is
begin
D <= A XOR B;
Bo <= (NOT A) AND B;
end dataflow;

 STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFSUBT_363 is
port (A, B: in std_logic;
D, Bo: out std_logic);
end HALFSUBT_363;
architecture structural of HALFSUBT_363 is
component xor1
port (a1, b1: in std_logic; c1: out std_logic);
end component;
42130363_PRIYADHARSHINI.R

component and1
port (a2, b2: in std_logic; c2: out std_logic);
end component;
component not1
port (a3: in std_logic; b3: out std_logic);
end component;
signal s1: std_logic;
begin
a1: and1 port map (s1, B, Bo);
x1: xor1 port map (A, B, D);
n1: not1 port map (A, s1);
end structural;

--COMPONENT SOURCE CODE

--XOR1
entity xor1 is
port (a1, b1: in std_logic;
c1: out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
c1 <= a1 XOR b1;
end dataflow;

--AND1
entity and1 is
port (a2, b2: in std_logic;
c2: out std_logic);
end and1;
architecture dataflow of and1 is
begin
c2 <= a2 AND b2;
end dataflow;

--NOT1
entity not1 is
port (a3: in std_logic; b3: out std_logic);
end not1;
architecture dataflow of not1 is
begin
b3 <=not a3;
end dataflow;
42130363_PRIYADHARSHINI.R

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALFSUBT_363 is
port (A, B: in std_logic;
D, Bo: out std_logic);
end HALFSUBT_363;
architecture behavioural of HALFSUBT_363 is
begin
process (A, B)
begin
D <= A XOR B;
Bo <= (NOT A) AND B;
end process;
end behavioural;

• SIMULATED OUTPUT:

• VERILOG CODE:

• DATAFLOW MODELING:

module hs_d363(x,y,d,b);
input x,y;
output d,b;
assign d=x^y;
assign b=(~x)&y;
endmodule

• STRUCTURAL MODELING

module hs_d363(x,y,d,b);
input x,y;
42130363_PRIYADHARSHINI.R

output d,b;
xor(d,x,y);
and(b,(~x),y);
endmodule

• BEHAVIOURAL MODELING:

module hs_b363(x,y,d,b);
input x,y;
output d,b;
reg d,b;
always @(*)
begin
d=y-x;
assign b=(~x)&y;
end
endmodule

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

4. FULL SUBTRACTOR:

• CIRCUIT DIAGRAM:

• EXPRESSIONS:

 Difference (D) = (A XOR B) XOR C


 Borrow (Bo) = ((NOT (A XOR B)) AND C) OR ((NOT A) AND B)

• TRUTH TABLE:

INPUTS OUTPUTS

A B C D Bo

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
42130363_PRIYADHARSHINI.R

• VHDL CODE:

 DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBT_363 is
port (A, B, C: in std_logic; D, Bo: out std_logic);
end FULLSUBT_363;
architecture dataflow of FULLSUBT_363 is
begin
D <= (A XOR B) XOR C;
Bo <= ((NOT A) AND B) OR (B AND C) OR (C AND (NOT A));
end dataflow;

 STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBT_363 is port (A, B, C: in std_logic;
D, Bo: out std_logic);
end FULLSUBT_363;
architecture structural of FULLSUBT_363 is
component xor1
port (a1, b1: in std_logic; c1: out: std_logic);
end component;
component and1
port (a2, b2: in std_logic; c2: out: std_logic);
end component;
component or1
port (a3, b3: in std_logic; c3: out: std_logic);
end component;
component not1
port (a4: in std_logic; b4: out: std_logic);
end component;
signal s1, s2, s3, s4, s5: std_logic;
begin
x1: xor1 port map (A, B, s1);
x2: xor1 port map (s1, C, D);
a1: and1 port map (s2, C, s4);
a2: and1 port map (s3, B, s5);
o1: or1 port map (s4, s5, Bo);
42130363_PRIYADHARSHINI.R

n1: not1 port map (s1, s2);


n2: not1 port map (A, s3);
end structural;

--COMPONENT SOURCE CODE

--XOR1
entity xor1 is port (a1, b1: in std_logic;
c1: out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
c1 <= a1 XOR b1;
end dataflow;

--AND1
entity and1 is
port (a2, b2: in std_logic; c2: out std_logic);
end and1;
architecture dataflow of and1 is
begin
c2 <= a2 AND b2;
end dataflow;

--COMPONENT SOURCE CODE

--XOR1
entity xor1 is
port (a1, b1: in std_logic; c1: out std_logic);
end xor1;
architecture dataflow of xor1 is
begin
c1 <= a1 XOR b1;
end dataflow;

--AND1
entity and1 is
port (a2, b2: in std_logic; c2: out std_logic);
end and1;
architecture dataflow of and1 is
begin
c2 <= a2 AND b2;
end dataflow;
42130363_PRIYADHARSHINI.R

--NOT1
entity not1 is
port (a4: in std_logic; b4:out std_logic);
end not1;
architecture dataflow of not1 is
begin
b4 <= NOT a4;
end dataflow;

--OR1
entity or1 is port (a3, b3: in std_logic; c3: out std_logic);
end or1;
architecture dataflow of or1 is
begin
c3 <= a3 OR b3;
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBT_363 is
port (A, B, C: in std_logic; D, Bo: out std_logic);
end FULLSUBT_363;
architecture behavioural of FULLSUBT_363 is
begin
process (A, B, C)
begin
D <= (A XOR B) XOR C;
Bo <= ((NOT A) AND B) OR (B AND C) OR (C AND
(NOT A));
end process;
end behavioural;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

• VERILOG CODE:

 DATAFLOW MODELING:

module fs_d363(x,y,z,d,b);
input x,y,z;
output d,b;
assign d=x^y^z;
assign b=((~x)&(y))|((~(x^y))&(z));
endmodule

 STRUCTURAL MODELING:

module fs_s363(x,y,z,d,b);
input x,y,z;
output d,b;
wire i,j,k;
xor(d,x,y,z);
and a1(i,(~x),y),
a2(j,(~(x^y)),z);
or(b,i,j);
endmodule

 BEHAVIOURAL MODELING:

module fs_b363(x,y,z,d,b);
input x,y,z;
output d,b;
reg d,b;
always @(*)
begin
d=z-y-x;
assign b=((~x)&(y))|((~(x^y))&(z));
end
endmodule
42130363_PRIYADHARSHINI.R

SIMULATED OUTPUT:

RESULT:

The output of Adders and Subtractors is verified by stimulating and synthesizing the
VHDL/VERILOG code
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 03 ENCODER AND DECODER


PAGE NO:

AIM:

To develop the source code for encoder and decoder using VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. 8*3 ENCODER:
• CIRCUIT DIAGRAM:

Y0
42130363_PRIYADHARSHINI.R

TRUTH TABLE
INPUTS OUTPUTS

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

• VHDL CODE:

 DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER_363 is
port (Y: in STD_LOGIC_VECTOR (0 to 7);
A2, A1, A0: out STD_LOGIC);
end ENCODER_363;
architecture dataflow of ENCODER_363 is
begin
A0 <= ((Y (1) OR Y (3)) OR Y (5)) OR Y (7);
A1 <= ((Y (2) OR Y (3)) OR Y (6)) OR Y (7);
A2 <= ((Y (4) OR Y (5)) OR Y (6)) OR Y (7);
end dataflow;
42130363_PRIYADHARSHINI.R

 STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER_363 is
port (Y: in STD_LOGIC_VECTOR (0 to 7);
A2, A1, A0: out STD_LOGIC);
end ENCODER_363;
architecture structural of ENCODER_214 is
component or1
port (a, b, c, d: in std_logic; z: out std_logic);
end component;
begin
o1: or1 port map (Y(7), Y(6), Y(5), Y(4), A2);
o2: or1 port map (Y(7), Y(6), Y(2), Y(3), A1);
o2: or1 port map (Y(7), Y(5), Y(3), Y(1), A0);
end structural;

--COMPONENT SOURCE CODE

--OR GATE
entity or1 is
port (a, b, c, d: in std_logic; z: out std_logic);
end or1;
architecture dataflow of or1 is
begin
z <= ((a OR b) OR c) OR d;
end dataflow;
 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER_363 is
port (Y: in STD_LOGIC_VECTOR (0 to 7);
A2, A1, A0: out STD_LOGIC);
end ENCODER_363;
architecture behavioural of ENCODER_363 is
begin
42130363_PRIYADHARSHINI.R

process (Y)
begin
A0 <= ((Y(1) OR Y(3)) OR Y(5)) OR Y(7);
A1 <= ((Y(2) OR Y(3)) OR Y(6)) OR Y(7);
A2 <= ((Y(4) OR Y(5)) OR Y(6)) OR Y(7);
end process;
end behavioral;
SIMULATED OUTPUT:

•VERILOG CODE:

 DATAFLOW MODELING:

module encoder_d363(input[7:0]a,output[2:0]y);
assign y[0]= a[1]| a[3]| a[5]| a[7];
assign y[1]= a[3]| a[2]| a[6]| a[7];
assign y[2]= a[4]| a[5]| a[6]| a[7];
endmodule

 STRUCTURAL MODELING:

module encoder_s363(input[7:0]a,output[2:0]y);
or(y[0],a[1],a[3],a[5],a[7]);
or(y[1],a[3], a[2], a[6], a[7]);
or(y[2], a[4], a[5], a[6], a[7]);
endmodule

 BEHAVIOURAL MODELING:

module encoder_b363(input[7:0]a,output
reg[2:0]y);
always @(*)
begin
42130363_PRIYADHARSHINI.R

case(a)
8'b00000000:y=3'd0;
8'b00000001:y=3'd0;
8'b00000010:y=3'd1;
8'b00000100:y=3'd2;
8'b00001000:y=3'd3;
8'b00010000:y=3'd4;
8'b00100000:y=3'd5;
8'b01000000:y=3'd6;

8'b10000000:y=3'd7;
endcase
end
endmodule

•SIMULATED OUTPUT:

2. 3*8 DECODER:

• CIRCUIT DIAGRAM:
42130363_PRIYADHARSHINI.R

TRUTH TABLE:

OUTPUTS INPUTS

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

• VHDL CODE:

 DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER_363 is
port (A: in std_logic_vector (2 downto 0);
Y: out std_logic_vector (7 downto 0));
end DECODER_363;
architecture dataflow of DECODER_363 is begin
Y(0)<=((not A(2)) and (not A(1))) and
(not A(0));
Y(1)<=((not A(2)) and (not A(1))) and
A(0);
Y(2)<=((not A(2)) and A(1)) and (not
A(0));
42130363_PRIYADHARSHINI.R

Y(3)<=((not A(2)) and A(1)) and A(0);


Y(4)<=(A(2) and (not A(1))) and (not
A(0));
Y(5)<=(A(2) and (not A(1))) and A(0);
Y(6)<=(A(2) and A(1)) and (not A(0));
Y(7)<=(A(2) and A(1)) and A(0); end
dataflow;

 STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER_363 is
port (A: in STD_LOGIC_VECTOR (2 downto 0);
Y: out STD_LOGIC_VECTOR (7 downto 0));
end DECODER_363;
architecture structural of DECODER_363 is
component not1
port (x1: in STD_LOGIC;
y1: out STD_LOGIC);
end component;

component and1
port (x2, y2, z2: in STD_LOGIC;
a2: out STD_LOGIC);
end component;
begin
n1: not1 port map (A(2), not A(2));
n2: not1 port map (A(1), not A(1));
n3: not1 port map (A(0), not A(0));
i: and1 port map (not A(2), not A(1), not A(0), Y(0));
j: and1 port map (not A(2), not A(1), A(0), Y(1));
k: and1 port map (not A(2), A(1), not A(0), Y(2));
l: and1 port map (not A(2), A(1), A(0), Y(3));
m: and1 port map (A(2), not A(1), not A(0), Y(4));
n: and1 port map (A(2), not A(1), A(0), Y(5));
o: and1 port map (A(2), A(1), not A(0), Y(6));
p: and1 port map (A(2), A(1), A(0), Y(7));
end structural;
42130363_PRIYADHARSHINI.R

--COMPONENT SOURCE CODE:

--NOT GATE
entity not1 is
port (x1: in STD_LOGIC;
y1: out STD_LOGIC);
end not1;
architecture dataflow of not1 is
begin
y1 <= (not x1);
end dataflow;

--AND GATE
entity and1 is
Port (x2, y2, z2: in STD_LOGIC;
a2: out STD_LOGIC);
end and1;
architecture dataflow of and1 is
begin
a2 <= (x2 and y2) and z2;
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE; use


IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER_363 is
port (A: in std_logic_vector (2 downto 0);
Y: out std_logic_vector (7 downto 0));
end DECODER_363;
architecture behavioural of DECODER_363 is
begin
process (A)

begin

Y(0)<=((not A(2)) and (not A(1))) and (not A(0));


Y(1)<=((not A(2)) and (not A(1))) and A(0);
Y(2)<=((not A(2)) and A(1)) and (not A(0));
Y(3)<=((not A(2)) and A(1)) and A(0);
Y(4)<=(A(2) and (not A(1))) and (not A(0));
Y(5)<=(A(2) and (not A(1))) and A(0);
Y(6)<=(A(2) and A(1)) and (not A(0));
Y(7)<=(A(2) and A(1)) and A(0);
42130363_PRIYADHARSHINI.R

end process;
end behavioural;

 SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

• VERILOG CODE:

 DATAFLOW MODELING:

module decoder_d363(input[2:0]a,output[7:0]y);
assign y[0]=(~a[2])&(~a[1])&(~a[0]);
assign y[1]=(~a[2])&(~a[1])&(a[0]);
assign y[2]=(~a[2])&(a[1])&(~a[0]);
assign y[3]=(~a[2])&(a[1])&(a[0]);
assign y[4]=(a[2])&(~a[1])&(~a[0]);
assign y[5]=(a[2])&(~a[1])&(a[0]);
assign y[6]=(a[2])&(a[1])&(~a[0]);
assign y[7]=(a[2])&(a[1])&(a[0]);
endmodule

 STRUCTURAL MODELING:

module decoder_s363(input[2:0]a,output[7:0]y); and(y[0],


(~a[2]),(~a[1]),(~a[0]));
and(y[1],(~a[2]),(~a[1]),(a[0]));
and(y[2],(~a[2]),(a[1]),(~a[0]));
and(y[3],(~a[2]),(a[1]),(a[0]));
and(y[4],(a[2]),(~a[1]),(~a[0]));
and(y[5],(a[2]),(~a[1]),(a[0]));
and(y[6],(a[2]),(a[1]),(~a[0]));
and(y[7],(a[2]),(a[1]),(a[0]));
endmodule

 BEHAVIOURAL MODELING:

module decoder_b363(input[2:0]a,output reg[7:0]y);


always @(*)
begin
y=8'd0;
case(a)
3'd0:y[0]=1'b1;
3'd1:y[1]=1'b1;
3'd2:y[2]=1'b1;
3'd3:y[3]=1'b1;
3'd4:y[4]=1'b1;
3'd5:y[5]=1'b1;
3'd6:y[6]=1'b1;
3'd7:y[7]=1'b1;
42130363_PRIYADHARSHINI.R

endcase
end
endmodule

•SIMULATED OUTPUT:

RESULT:

The output of Encoder and Decoder is verified by stimulating and synthesizing the
VHDL/VERILOG code.
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 04 MULTIPLEXER AND DEMULTIPLEXER


PAGE NO:

AIM:

To develop the source code for multiplexer and demultiplexer using VHDL / VERILOG
and obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG and Debug the error if found.
Step4: Verify the output by simulating the source code.
Step5: Write all possible combinations of input using the test bench
Step6: Obtain the synthesis report.

1. 8*1 MULTIPLEXER:

• CIRCUIT DIAGRAM:
42130363_PRIYADHARSHINI.R

• TRUTH TABLE:

INPUTS (SELECT LINES) OUTPUT

S2 S1 S0 Y

0 0 0 A0

0 0 1 A1

0 1 0 A2

0 1 1 A3

1 0 0 A4

1 0 1 A5

1 1 0 A6

1 1 1 A7

• VHDL CODE:

 DATAFLOW MODELING:

library IEEE; use


IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_363 is
port (S:in std_logic_vector (2 downto 0);
A: in std_logic_vector (7 downto 0);
Y: out std_logic);
end MUX_363;
architecture dataflow of MUX_363 is
signal s00,s11,s22,i,j,k,l,m,n,o,p:std_logic;
begin
s00<=(not S(0));
s11<=(not S(1));
s22<=(not S(2));
i<=((A(0) and s22) and s11) and s00;
j<=((A(1) and s22) and s11) and S(0);
k<=((A(2) and s22) and S(1)) and s00;
l<=((A(3) and s22) and S(1)) and S(0);
42130363_PRIYADHARSHINI.R

m<=((A(4) and S(2)) and s11) and s00;


n<=((A(5) and S(2)) and s11) and S(0);
o<=((A(6) and S(2)) and S(1)) and s00;
p<=((A(7) and S(2)) and S(1)) and S(0);
Y<=((((((i or j) or k) or l) or m) or n) or o) or p;
end dataflow;

 STRUCTURAL MODELING:
library IEEE; use
IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_363 is
port (S:in std_logic_vector (2 downto 0);
A: in std_logic_vector (7 downto 0);
Y: out std_logic);
end MUX_363;
architecture structural of MUX_363 is
component not1
port(s1:in std_logic; s2: out std_logic);
end component;
component and1
port(a1, b1, c1, d1:in std_logic;
e1: out std_logic);
end component;
component or1
port(a,b,c,d,e,f,g,h:in std_logic;
z1: out std_logic);
end component;
signal s00, s11, s22, i,j,k,l,m,n,o,p: std_logic;
begin
s00<=not S(0);
s11<=not S(1);
s22<=not S(2);
i<=((A(0) and s22) and s11) and s00;
j<=((A(1) and s22) and s11) and S(0);
k<=((A(2) and s22) and S(1)) and s00;
l<=((A(3) and s22) and S(1)) and S(0);
m<=((A(4) and S(2)) and s11) and s00;
n<=((A(5) and S(2)) and s11) and S(0);
o<=((A(6) and S(2)) and S(1)) and s00;
p<=((A(7) and S(2)) and S(1)) and S(0);
n1:not1 port map (S(0), s00);
n2:not1 port map (S(1), s11);
n3:not1 port map(S(2),s22);
42130363_PRIYADHARSHINI.R

an1:and1 port map(A(0), s22, s11, s00, i);


an2:and1 port map(A(1), s22, s11, S(0), j);
an3:and1 port map(A(2), s22, S(1), s00, k);
an4:and1 port map(A(3), s22, S(1), S(0), l);
an5:and1 port map(A(4), S(2), s11, s00, m);
an6:and1 port map(A(5), S(2), s11, S(0), n);
an7:and1 port map(A(6), S(2), S(1), s00, o);
an8:and1 port map(A(7), S(2), S(1), S(0), p);
o1:or1 port map(i,j,k,l,m,n,o,p,Y);
end structural;

--COMPONENT SOURCE CODE:

--NOT GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
port (s1:in std_logic; s2: out std_logic);
end not1;
architecture dataflow of not1 is
begin s2<= (not s1);
end dataflow;

--AND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and1 is
port (a1, b1, c1, d1:in std_logic;
e1: out std_logic);
end and1;
architecture dataflow of and1 is
begin
e1<= ((a1 and b1) and c1) and d1;
end dataflow;

--OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or1 is
42130363_PRIYADHARSHINI.R

port (a,b,c,d,e,f,g,h:in std_logic;


z1: out std_logic);
end or1;
architecture dataflow of or1 is
begin
z1<=((((((a or b) or c) or d) or e) or f) or g) or h;
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_B_363 is
port(S:in std_logic_vector(2 downto 0);
A: in std_logic_vector (7 downto 0);
Y: out std_logic);
end MUX_B_363;
architecture behavioural of MUX_B_363 is
begin
process(S,A)
begin
if (S = "000") then Y<=A(0);
elsif (S = "001") then Y<=A(1);
elsif (S = "010") then Y<=A(2);
elsif (S = "011") then Y<=A(3);
elsif (S = "100") then Y<=A(4);
elsif (S = "101") then Y<=A(5);
elsif (S = "110") then Y<=A(6);
else Y<=A(7);
end if;
end process;
end behavioural;
42130363_PRIYADHARSHINI.R

• SIMULATED OUTPUT:

VERILOG CODE:

 DATAFLOW MODELING:

module mux_d363(input[7:0]a, input[2:0]s, output y);


assign y=((~s[2])&(~s[1])&(~s[0])&a[0])|
((~s[2])&(~s[1])&(s[0]
)&a[1])|((~s[2])&(s[1])&(~s[0])&a[2])|((~s[2])&(s[1])&(
s[0])&a[3])|((s[2])&(~s[1])&(~s[0])&a[4])|((s[2])&(~s[1
])&(s[0])&a[5])|((s[2])&(s[1])&(~s[0])&a[6])|((s[2])&(s
[1])&(s[0])&a[7];
endmodule

 STRUCTURAL MODELING:

module mux_s363(input[7:0]a, input[2:0]s, output y);


wire[7:0]x;
and(x[0],(~s[2]),(~s[1]),(~s[0]),a[0]);
and(x[1],(~s[2]),(~s[1]),(s[0]),a[1]);
and(x[2],(~s[2]),(s[1]),(~s[0]),a[2]);
and(x[3],(~s[2]),(s[1]),(s[0]),a[3]);
and(x[4],(s[2]),(~s[1]),(~s[0]),a[4]);
and(x[5],(s[2]),(~s[1]),(s[0]),a[5]);
and(x[6],(s[2]),(s[1]),(~s[0]),a[6]);
42130363_PRIYADHARSHINI.R

and(x[7],(s[2]),(s[1]),(s[0]),a[7]);
or(x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7]);
endmodule

 BEHAVIOURAL MODELING:

module mux_b214(input[7:0]a,
input[2:0]s, output reg y);
always @(*)
begin
case(s)
3'b000:y=a[0];
3'b001:y=a[1];
3'b010:y=a[2];
3'b011:y=a[3];
3'b100:y=a[4];
3'b101:y=a[5];
3'b110:y=a[6];
3'b111:y=a[7];
endcase
end
endmodule

SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

2. 1*8 DEMULTIPLEXER:

• CIRCUIT DIAGRAM:

TRUTH TABLE:

OUTPUTS INPUTS

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 S2 S1 S0 A

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 1 0 0 0 1 1

0 0 0 0 0 1 0 0 0 1 0 1

0 0 0 0 1 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0 1 0 0 1

0 0 1 0 0 0 0 0 1 0 1 1

0 1 0 0 0 0 0 0 1 1 0 1

1 0 0 0 0 0 0 0 1 1 1 1
42130363_PRIYADHARSHINI.R

• VHDL CODE:

 DATAFLOW MODELING:

library IEEE; use


IEEE.STD_LOGIC_1164.ALL;
entity DEMUX_363 is
port(A: in std_logic;
S:in std_logic_vector(2 downto 0);
Y:out std_logic_vector(7 downto 0));
end DEMUX_363;
architecture dataflow of DEMUX_363 is
begin
Y(0)<=((A and (not S(2)))and(not S(1)))and(not S(0));
Y(1)<=((A and (not S(2)))and (not S(1))) and S(0);
Y(2)<=((A and (not S(2))) and S(1)) and (not S(0));
Y(3)<=((A and (not S(2))) and S(1)) and S(0);
Y(4)<=((A and S(2)) and (not S(1))) and (not S(0));
Y(5)<=((A and S(2)) and (not S(1))) and S(0);
Y(6)<=((A and S(2)) and S(1)) and (not S(0));
Y(7)<=((A and S(2)) and S(1)) and S(0);
end dataflow;

 STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEMUX_363 is
port(A:in std_logic;
S:in std_logic_vector(2 downto 0);
Y:out std_logic_vector(7 downto 0));
end DEMUX_363;
architecture structural of DEMUX_363 is
component and1
port(a,b,c,d: in std_logic;
e: out std_logic);
end component;
component not1
port(i: in std_logic; j:out std_logic);
end component;
signal s2,s1,s0:std_logic;
begin
n1:not1 port map(S(2),s2);
n2:not1 port map(S(1),s1);
n3:not1 port map(S(0),s0);
42130363_PRIYADHARSHINI.R

a1:and1 port map(A,s2,s1,s0,Y(0));


a2:and1 port map(A,s2,s1,S(0),Y(1));
a3:and1 port map(A,s2,S(1),s0,Y(2));
a4:and1 port map(A,s2,S(1),S(0),Y(3));
a5:and1 port map(A,S(2),s1,s0,Y(4));
a6:and1 port map(A,S(2),s1,S(0),Y(5));
a7:and1 port map(A,S(2),S(1),S0,Y(6));
a8:and1 port map(A,S(2),S(1),S(0),Y(7));
end structural;

--COMPONENT SOURCE CODE

--AND GATE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is
port(a,b,c,d: in std_logic;
e: out std_logic);
end
and1;
architecture dataflow of and1 is
begin
e<=((a and b)and c)and d;
end dataflow;

--NOT GATE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not1 is
port(i:in std_logic; j:out std_logic);
end not1;
architecture dataflow of not1 is
begin
j<= not i;
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEMUX_363 is
port(A:in std_logic;
42130363_PRIYADHARSHINI.R

S:in std_logic_vector(2 downto 0);


Y:out std_logic_vector(7 downto 0));
end DEMUX_363;
architecture behavioural of DEMUX_363 is
begin
process(A,S)
begin
Y<= "00000000";
case S is
when "000" => Y(0)<= A;
when "001" => Y(1)<= A;
when "010" => Y(2)<= A;
when "011" => Y(3)<= A;
when "100" => Y(4)<= A;
when "101" => Y(5)<= A;
when "110" => Y(6)<= A;
when "111" => Y(7)<= A;
when others => Y<= "00000000";
end case;
end process;
end behavioural;

 SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

 VERILOG CODES:

 DATAFLOW MODELING:

module demux_d363(output reg [7:0] Y, input [2:0] A,


input din);
assign Y[0]=din && (~S[2])&&(~S[1])&&(~S[0]);
assign Y[1]=din && (~S[2])&&(~S[1]) && S[0];
assign Y[2]=din && (~S[2])&& S[1] && (~S[0]);
assign Y[3]=din && (~S[2]) && S[1]) && S[0];
assign Y[4]=din && S[2] && (~S[1]) && (~S[0]);
assign Y[5]=din && S[2] && (~S[1]) && S[0];
assign Y[6]=din && S[2] && S[1] && (~S[0]);
assign Y[7]=din && S[2] && S[1] && S[0];
endmodule

 STRUCTURAL MODELING:

module demux_d363(output reg [7:0] Y, input [2:0] A,


input din);
and (Y[0],din,(~S[2]),(~S[1]),(~S[0]));
and (Y[1],din,(~S[2]),(~S[1]),S[0]);
and (Y[2],din,(~S[2]),S[1],(~S[0]));
and (Y[3],din,(~S[2]),S[1],S[0]);
and (Y[4],din,S[2],(~S[1]),(~S[0]));
and (Y[5],din,S[2],(~S[1]),S[0]);
and (Y[6],din,S[2],S[1],(~S[0]));
and (Y[7],din,S[2],S[1],S[0]);
endmodule

 BEHAVIOURAL MODELING:

module demux_d363(output reg [7:0] Y, input [2:0] A,


input din);
always @(*)
begin
Y=8'b00000000;
case (A)
3'b000: Y[0] = din;
3'b001: Y[1] = din;
3'b010: Y[2] = din;
3'b011: Y[3] = din;
3'b100: Y[4] = din;
3'b101: Y[5] = din;
42130363_PRIYADHARSHINI.R

3'b110: Y[6] = din;


3'b111: Y[7] = din;
endcase
end
endmodule

SIMULATED OUTPUT:

RESULT:
The output of Multiplexer and Demultiplexer is verified by
stimulating and synthesizing the VHDL/VERILOG code.
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 05 RIPPLE CARRY ADDER


PAGE NO:

AIM:

To develop the source code for Ripple Carry Adder using VHDL/VERILOG and obtain
the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

CIRCUIT DIAGRAM:
42130363_PRIYADHARSHINI.R

TRUTH TABLE:

INPUTS OUTPUTS

C0 A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 C4

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 1 0 0 1 0 0

0 0 0 1 0 0 0 1 0 0 1 0 0 0

0 0 0 1 1 0 0 1 1 0 1 1 0 0

0 0 1 0 0 0 1 0 0 1 0 0 0 0

0 0 1 0 1 0 1 0 1 1 0 1 0 0

0 0 1 1 0 0 1 1 0 1 1 0 0 0

0 0 1 1 1 0 1 1 1 1 1 1 0 0

0 1 0 0 0 1 0 0 0 0 0 0 0 1

0 1 0 0 1 1 0 0 1 0 0 1 0 1

0 1 0 1 0 1 0 1 0 0 1 0 0 1

0 1 0 1 1 1 0 1 1 0 1 1 0 1

0 1 1 0 0 1 1 0 0 1 0 0 0 1

0 1 1 0 1 1 1 0 1 1 0 1 0 1

0 1 1 1 0 1 1 1 0 1 1 0 0 1

0 1 1 1 1 1 1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1
42130363_PRIYADHARSHINI.R

VHDL CODES:

 DATAFLOW MODELING:

library IEEE; use


IEEE.STD_LOGIC_1164.ALL;
entity RCA_363 is
port(C0: in STD_LOGIC;
A,B: in std_logic_vector(3 downto 0);
C4: out STD_LOGIC;
S: out std_logic_vector(3 downto 0));
end RCA_363;
architecture dataflow of RCA_363 is
signal C1,C2,C3:STD_LOGIC;
begin
C1<=((A(0)and B(0))or (B(0)and C0))or (C0 and
A(0));
C2<=((A(1)and B(1))or (B(1)and C1)) or (C1 and
A(1));
C3<=((A(2)and B(2))or (B(2)and C2)) or (C2 and
A(2));
S(0)<= ((A(0) xor B(0)) xor C0);
S(1)<= ((A(1) xor B(1)) xor C1);
S(2)<= ((A(2) xor B(2))xor C2);
S(3)<= ((A(3) xor B(3))xor C3);
C4<= ((A(3) and B(3))or(B(3) and C3)) or (C3 and
A(3));
end dataflow;

 STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RCA_363 is
port(C0: in STD_LOGIC;
A,B: in std_logic_vector(3 downto 0);
C4: out STD_LOGIC;
S: out std_logic_vector(3 downto 0));
end RCA_363;
architecture structural of RCA_363 is
component fa
port(x,y,z:in std_logic;
s,c:out std_logic);
end component;
signal C1,C2,C3: std_logic;
42130363_PRIYADHARSHINI.R

begin
C1<=((A(0)and B(0))or (B(0)and C0))or (C0 and A(0));
C2<=((A(1)and B(1))or (B(1)and C1)) or (C1 and A(1));
C3<=((A(2)and B(2))or (B(2)and C2)) or (C2 and A(2));
x1: fa port map (A(0),B(0),C0,S(0),C1);
x2: fa port map (A(1),B(1),C1,S(1),C2);
x3: fa port map (A(2),B(2),C2,S(2),C3);
x4: fa port map (A(3),B(3),C3,S(3),C4);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa is
port (x,y,z:in STD_LOGIC;s,c:out STD_LOGIC);
end fa;
architecture dataflow of fa is
begin
s <=(x xor y) xor z;
c <= (x and y) or (y and z) or (z and x);
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RCA_363 is
port(C0: in STD_LOGIC;
A,B: in std_logic_vector(3 downto 0);
C4: out STD_LOGIC;
S: out std_logic_vector(3 downto 0));
end RCA_363;
architecture behavioural of RCA_363 is
begin
process(A,B,C0)
begin
S<=A+B+C0;
if (A > "0111" or B > "0111")then
C4<='1'; else
C4<='0';
end if;
end process;
end behavioural;
42130363_PRIYADHARSHINI.R

SIMULATED OUTPUT:

VERILOG CODE:

 DATAFLOW MODELING:

module rca_d363(a,b,c0,c4,s);
input c0;
input [3:0]a,b;
output [3:0]s;
output c4;
wire[3:1]c;
assign c1=(a[0]&b[0])|(b[0]&c0)|(c0&a[0]);
assign c2=(a[1]&b[1])|(b[1]&c[1])|(c[1]&a[1]);
assign c3=(a[2]&b[2])|(b[2]&c[2])|(c[2]&a[2]);
assign s[0]= (a[0] ^ b[0]) ^ c0);
assign s[1]= (a[1] ^ b[1]) ^ c[1]);
assign s[2]= (a[2] ^ b[2]) ^ c[2]);
assign s[3]= (a[3] ^ b[3]) ^ c[3]);
assign c4 = (a[3] & b[3])|(b[3] & c[3])|(c[3] &
a[3]);
endmodule

 STRUCTURAL MODELING:

module RCA_363(input[3:0]a,b,
input cin,
output[3:0]s,
output cout);
wire [2:0]c;
FA_adder1(a[0],b[0],cin,s[0],c[0]),
adder2(a[1],b[1],c[0],s[1],c[1]),
adder3(a[2],b[2],c[1],s[2],c[2]),
adder4(a[3],b[3],c[2],s[3],cout);
endmodule
module FA(input a,b,c, output s,cout);
42130363_PRIYADHARSHINI.R

assign s=a^b^c;
assign cout= (a&b)|(b&c)|(c&a);
endmodule

 BEHAVIOURAL MODELING:

module rca_b214(input[3:0]a,b,input cin, output reg[0:3]s,


output reg co);
always @(*)

begin
s = a+b+cin;
if (a > 4'b0111 || b > 4'b0111)
begin
co =
1; end
else
begin
co =
0; end
end endmodule

SIMULATED OUTPUT :
42130363_PRIYADHARSHINI.R

SIMULATED OUTPUT

RESULT

The output of 4-bit Ripple Carry Adder is verified by stimulating and synthesizing the
VHDL/VERILOG code.
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 06 CODE CONVERTERS


PAGE NO:

AIM:

To develop the source code for code converters using VHDL/VERILOG and obtain the
simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. BINARY TO GRAY CODE CONVERTER:

CIRCUIT DIAGRAM:

4 – bit Binary to Gray code converter


42130363_PRIYADHARSHINI.R

TRUTH TABLE:
BINARY INPUT GRAY OUTPUT

B3 B2 B1 B0 G3 G2 G3 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
42130363_PRIYADHARSHINI.R

VHDL CODES:

 DATAFLOW MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECOV_363 is
port(B:in std_logic_vector(3 downto 0);
G:out std_logic_vector(3 downto 0));
end CODECOV_363;
architecture dataflow of CODECOV_363 is
begin
G(3)<=B(3);
G(2)<=(B(2) XOR
B(3));
G(1)<=(B(1) XOR B(2));
G(0)<=(B(0) XOR B(1));
end dataflow;

 STRUCTURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECOV_363 is
port(B:in std_logic_vector(3 downto 0);
G:out std_logic_vector(3 downto 0));
end CODECOV_363;
architecture structural of CODECOV_363 is
component xor1
port(a,b:in std_logic; c:out std_logic);
end component; begin
x1:xor1 port map (B(3),'0',G(3));
x2:xor1 port map (B(2),B(3),G(2));
x3:xor1 port map (B(1),B(2),G(1));
x4:xor1 port map (B(0),B(1),G(0));
end structural;

--COMPONENT SOURCE CODE

--XOR GATE

library IEEE;
use IEEE.std_logic_1164.ALL;
entity xor1 is
port(a,b:in std_logic; c:out std_logic);
end xor1;
architecture dataflow of xor1 is
42130363_PRIYADHARSHINI.R

begin
c <= a XOR B;
end dataflow;

 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECOV_363 is
port(B:in std_logic_vector(3 downto 0);
G:out std_logic_vector(3 downto 0));
end CODECOV_363;
architecture behavioural of CODECOV_363 is
begin
process(B)
begin
G(3)<=B(3);
G(2)<=(B(2) XOR B(3));
G(1)<=(B(1) XOR B(2));
G(0)<=(B(0) XOR B(1));
end process;
end behavioural;

SIMULATED OUTPUT:

VERILOG CODE:

• DATAFLOW MODELING:

module codeconv_d363(input [3:0]b,output [3:0]g);


assign g[3] = b[3];
assign g[2] = b[3]^b[2];
assign g[1] = b[2]^b[1];
assign g[0] = b[1]^b[0];
endmodule
42130363_PRIYADHARSHINI.R

• STRUCTURAL MODELING:

module codeconv_s363(input [3:0]b,output [3:0]g);


xor(g[3],b[3]);
xor(g[2],b[3],b[2]);
xor(g[1],b[2],b[1]);
xor(g[0],b[1],b[0]);
endmodule

• BEHAVIOURAL MODELING:

module codeconv_s363(input [3:0]b,output reg [3:0]g);


always @(*)
begin
g[3] = b[3];
g[2] = b[3]^b[2];
g[1] = b[2]^b[1];
g[0] = b[1]^b[0];
end
endmodule
42130363_PRIYADHARSHINI.R

SIMULATED OUTPUT:

2. GRAY TO BINARY CODE CONVERTER:

CIRCUIT DIAGRAM:

4 – bit Binary to Gray code converter


42130363_PRIYADHARSHINI.R

TRUTH TABLE:
BINARY OUTPUT GRAY INPUT

B3 B2 B1 B0 G3 G2 G3 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
42130363_PRIYADHARSHINI.R

VHDL CODES:

 DATAFLOW MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CODECONVGTB_363 is
port(G:in std_logic_vector(3 downto 0);
B:out std_logic_vector(3 downto 0));
end CODECONVGTB_363;
architecture dataflow of CODECONVGTB_363 is
begin
B(3)<=G(3);
B(2)<=G(3) XOR G(2);
B(1)<=G(1) XOR (G(3) XOR G(2));
B(0)<=G(0) XOR (G(1) XOR (G(3) XOR G(2)));
end dataflow;

 STRUCTURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECONVGTB_363 is
port(G:in std_logic_vector(3 downto 0);
B:out std_logic_vector(3 downto 0));
end CODECONVGTB_363;
architecture structural of CODECONVGTB_363 is

component xor1

port(a,b:in std_logic; c:out std_logic);


end component; begin
x1:xor1 port map (G(3),'0',B(3));
x2:xor1 port map (G(2),G(3),B(2));
x3:xor1 port map (G(1),G(3),G(2),B(1));
x4:xor1 port map (G(0),G(1),G(3),G(2),B(0));
end structural;

--COMPONENT SOURCE CODE

--XOR GATE
library IEEE;
use IEEE.std_logic_1164.ALL;
entity xor1 is
port(a,b:in std_logic; c:out std_logic);
end xor1;
42130363_PRIYADHARSHINI.R

architecture dataflow of xor1 is


begin
c <= a XOR B;
end dataflow;
 BEHAVIOURAL MODELING:

library IEEE;
use IEEE.std_logic_1164.ALL;
entity CODECONVGTB_363 is
port(G:in std_logic_vector(3 downto 0);
B:out std_logic_vector(3 downto 0));
end CODECONVGTB_363;
architecture behavioural of CODECONVGTB_363 is
begin
process(G)
begin
B(3)<=G(3);
B(2)<=G(3) XOR G(2);
B(1)<=G(1) XOR (G(3) XOR G(2));
B(0)<=G(0) XOR (G(1) XOR (G(3) XOR G(2)));
end process;
end behavioural;

SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

VERILOG CODES:

• DATAFLOW MODELING:

module codeconvgtb_d363(input [3:0]b,output [3:0]g);


assign b[3] = g[3];
assign b[2] = g[3]^g[2];
assign b[1] = g[1]^g[3]^g[2];
assign b[0] = g[0]^g[1]^g[3]^g[2];
endmodule

• STRUCTURAL MODELING:

module codeconvgtb_s363(input [3:0]b,output [3:0]g);


xor(b[3],g[3]);
xor(b[2],g[3],g[2]);
xor(b[1],g[3],g[2],g[1]);
xor(b[0],g[0],g[1],g[3],g[2]);
endmodule

• BEHAVIOURAL MODELING:

module codeconvgtb_s363(input [3:0]b,output reg [3:0]g);


always @(*)
begin
b[3] = g[3];
b[2] = g[3]^g[2];
b[1] = g[1]^g[3]^g[2];
b[0] = g[0]^g[1]^g[3]^g[2];
end
endmodule
42130363_PRIYADHARSHINI.R

SIMULATED OUTPUT:

RESULT:

The output of Code Converters is verified by stimulating and synthesizing the


VHDL/VERILOG code.
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 07 FLIP FLOPS


PAGE NO:

AIM:

To develop the source code for flip flops using VHDL /VEROLOG and obtain the simulation
and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. SR FLIP FLOP:

• CIRCUIT SCHEMATIC:
42130363_PRIYADHARSHINI.R


TRUTH TABLE:

RST C S R Q Q1

1 - - - 0 1

0 1 0 0 NO CHANGE NO CHANGE

0 1 0 1 0 1

0 1 1 0 1 0

0 1 1 1 X X

• VHDL CODE:

 BEHAVIOUR MODELLING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SRFF_B363 is
port(s,r,c,rst:in std_logic;
q,q1:inout std_logic);
end SRFF_B363;
architecture behavioural of SRFF_B363 is
begin
process(s,r,c,rst)
begin
if(rst='1')then
q<='0';q1<='1';
elsif(c='1'and c'event)then
if(s='0' and r='0')then
q<=q; q1<=q1;
elsif(s='0' and r='1')then
q<='0'; q1<='1';
elsif(s='1' and r='0')then
q<='1';q1<='0';
else
q<='X';q1<='X';
end if;
end if;
end process;
end behavioural;
42130363_PRIYADHARSHINI.R


SIMULATED OUTPUT:

2. JK FLIP FLOP:

• CIRCUIT SCHEMATIC:

• TRUTH TABLE:

RST C J K Q Q1

1 - - - 0 1

0 1 0 0 NO CHANGE NO CHANGE

0 1 0 1 0 1

0 1 1 0 1 0

0 1 1 1 TOGGLE TOGGLE
42130363_PRIYADHARSHINI.R


VHDL CODE:

 BEHAVIOURAL MODELLING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JKFF_363 is
port(j,k,c,rst:in std_logic;
q,q1:inout std_logic);
end JKFF_363;
architecture behavioural of JKFF_363 is
begin
process(j,k,c,rst)
begin
if(rst='1') then
q<='0';q1<='1';
elsif(c='1' and c'event)then
if(j='0' and k='0')then
q<=q;q1<=q1;
elsif(j='0' and k='1')then
q<='0';q1<='1';
elsif(j='1' and k='0')then
q<='1';q1<='0';
else
q<=not q;
q1<=not q1;
end if;
end if;
end process;
end behavioural;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

3. D FLIP FLOP:

 CIRCUIT SCHEMATIC:

 TRUTH TABLE:

RST C D Q Q1

1 - - 0 1

0 1 0 0 1

0 1 1 1 0

VHDL CODE:
 BEHAVIOURAL MODELLING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF_363 is
port(d,c,rst:in std_logic;
q,q1:inout std_logic);
end DFF_363;
architecture behavioural of DFF_363 is
begin
process(d,c,rst)
begin
if(rst='1') then
q<='0';q1<='1';
elsif(c='1' and
c'event)then if(d='0')then
q<='0';q1<='1';
else
q<='1';q1<='0';
end if;
end if;
end process;
42130363_PRIYADHARSHINI.R

end behavioural;

 SIMULATED OUTPUT:

4. T FLIP FLOP:

CIRCUIT SCHEMATIC:

TRUTH TABLE:

RST C T Q Q1

1 - - 0 1

NO NO
0 1 0
CHANGE CHANGE
0 1 1 TOGGLE TOGGLE
42130363_PRIYADHARSHINI.R

VHDL CODE:
 BEHAVIOURAL MODELLING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TFF_363 is
port(t,c,rst:in std_logic;
q,q1:inout std_logic);
end TFF_363;
architecture behavioural of TFF_363 is
begin
process(t,c,rst)
begin
if(rst='1') then
q<='0';q1<='1';
elsif(c='1' and c'event)then
if(t='0')then
q<=q;q1<=q1;
else
q<=not q;q1<=not q1;
end if;
end if;
end process;
end behavioural;

 SIMULATED OUTPUT;
42130363_PRIYADHARSHINI.R

VERILOG CODE:
1. SR FLIP FLOP:

module srff_363(input s,r,clk,output reg q,qbar);


always@(posedge clk)
begin
q=1'b0; qbar=1'b1;
if(clk==1)
begin
if(s==0 && r==0)
begin
q=q; qbar=qbar;
end
else if(s==0 && r==1)
begin
q=1'b0; qbar=1'b1;
end
else if(s==1 && r==0)
begin
q=1'b1; qbar=1'b0;
end
else
if(s==1 && r==1)
begin
q=1'bx; qbar=1'bx;
end
end
if(clk==0)
begin
q=q; qbar=qbar;
end
end
42130363_PRIYADHARSHINI.R
42130363_PRIYADHARSHINI.R

2.
JK FLIP FLOP:

module jkff_363(input j,k,clk,output reg q,qbar);


always@(posedge clk)
begin
q=1'b0; qbar=1'b1;
if(clk==1)
begin
if(j==0 && k==0)
begin
q=q; qbar=qbar;
end
else if(j==0 && k==1)
begin
q=1'b0; qbar=1'b1;
end
else if(j==1 && k==0)
begin
q=1'b1; qbar=1'b0;
end
else if(j==1 && k==1)
begin
q=~q; qbar=~qbar;
end
end
if(clk==0)
begin
q=q; qbar=qbar;
end
end
endmodule
42130363_PRIYADHARSHINI.R

3.
D FLIP FLOP:

module dff_363(input d,clk,output reg q,qbar);


always@(posedge clk)
begin q=1'b0;
qbar=1'b1;
if(clk==1)
begin if(d==0)
begin q=1'b0;
qbar=1'b1;
end
else
if(d==1)
begin
q=1'b1;
qbar=1'b0;
end
end
if(clk==0)
begin
q=q; qbar=qbar;
end
end
endmodule
42130363_PRIYADHARSHINI.R

4.
T FLIP FLOP:

module tff_363(input t,clk,output reg q,qbar);


always@(posedge clk)
begin
q=1'b0; qbar=1'b1;
if(clk==1)
begin
if(t==0)
begin
q=1'b1; qbar=1'b0;
end
else if(t==1)
begin
q=1'b0; qbar=1'b1;
end end
if(clk==0)
begin
q=q; qbar=qbar;
end
end
endmodule

RESULT:

The output of Flip Flops is verified by stimulating and synthesizing the VHDL/
VERILOG code.
42130363_PRIYADHARSHINI.R

5.
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 08 SHIFT REGISTERS


PAGE NO:

AIM:

To develop the source code for shift registers using VHDL/VERILOG and obtain the
simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. SISO SHIFT REGISTER:

• CIRCUIT SCHEMATIC:
42130363_PRIYADHARSHINI.R

• TRUTH TABLE:

C (CLK) R (RESET) D (DATA IN) Q Q1


- 1 - - 0000
1 0 1000
2 0 1100

0 1
3 0 1110
4 1 1111

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SISO_363 is
port(c,d,r:in std_logic;
q: out std_logic);
end SISO_363;
architecture behavioural of SISO_363 is
signal q1: std_logic_vector(3 downto 0);
begin
process(c,d,r)
begin
if (r='1') then
q1<="0000";
elsif(c='1' and c'event) then
q1(3)<=d;
q1(2 downto 0)<=q1(3 downto 1);
q<=q1(1);
end if;
end process;
end behavioural;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

2. SIPO SHIFT REGISTER:

• CIRCUIT SCHEMATIC:

• TRUTH TABLE:

C (CLK) R (RESET) D (DATA IN) Q Q1


- 1 - - 0000
1 0111 1000
2 0011 1100

0 1
3 0001 1110
4 0000 1111

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SR_SIPO_363 is
port(c,d,r: in std_logic;
q:out std_logic_vector(3 downto 0));
end SR_SIPO_363;
architecture behavioural of SR_SIPO_363 is
signal q1: std_logic_vector(3 downto 0);
begin
42130363_PRIYADHARSHINI.R

process(c,d,r)
begin
if(r='1')then
q1<="0000";
elsif(c='1' and c'event)then
q1(3)<=d;
q1(2)<=q1(3);
q1(1)<=q1(2);
q1(0)<=q1(1);
end if;
end process;
q<=(not q1);
end behavioural;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

3. PISO SHIFT REGISTER:

• CIRCUIT SCHEMATIC:

• TRUTH TABLE:

CLK RESET Sin (Load) Pin Sout Shifts (sr)

- 1 - - 0 0000

1 0 0000

2 0 0001

3 1111 0 0011
0 1 (Sample
4 Data) 0 0111

5 0 1111

6 1 1111
42130363_PRIYADHARSHINI.R

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
entity PISO_363 is
port (clk,reset,sin: in std_logic;
pin: in std_logic_vector(3 downto 0);
sout: out std_logic);
end PISO_363;
architecture behavioral of PISO_363 is
signal sr: std_logic_vector(3 downto 0);
begin
process (clk, reset)
begin
if reset = '1' then
sr <= (others => '0');
sout <= '0';
elsif rising_edge(clk) then
sr <= pin;
sout <= sr(3);
sr <= sr(2 downto 0) & sin;
end if;
end process;
end behavioral;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

4. PIPO SHIFT REGISTER:

• CIRCUIT SCHEMATIC:

• TRUTH TABLE:

CLK RST Din Dout


- 1 - 0000
1 0000
0000
2 0000
3 0000
0001
4 0001

0
5 0001

0010
6 0010
7 0010

0011
8 0011
42130363_PRIYADHARSHINI.R

• VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PIPO_363 is
din: in std_logic_vector(3 downto 0);
dout: out std_logic_vector(3 downto 0));
end PIPO_214;
architecture behavioural of PIPO_214 is
begin
process(rst,clk,din)
begin
if (rst='1')
then dout<="0000";
elsif (rst='0') then
if (rising_edge(clk))then
dout<=din;
end if;
end if;
end process;
end behavioural;

• SIMULATED OUTPUT:

VERILOG CODE:

1. SISO SHIFT REGISTER:

module siso_363(input si,rst,clk,output reg so);


reg [3:0]q;
always@(si,rst,clk)
begin
if(rst == 1)
begin
so = 1'bZ;
q = 4'b0000;
end
else
begin
42130363_PRIYADHARSHINI.R

q[3] = si;
q[2] = q[3];
q[1] = q[2];
q[0] = q[1];
so = q[1];
end
end
endmodule

2. SIPO SHIFT REGISTER:

module sipo_363(si,rst,clk,po);
input si,rst,clk;
output [0:3]po;
reg[0:3]po;
always@(si,rst,clk)
begin
if(rst == 1)
begin
po = 4'bZ;
end
else
begin
po[0] = si;
po[1] = po[0];
po[2] = po[1];
po[3] = po[2];
end
end
endmodule
42130363_PRIYADHARSHINI.R

3. PISO SHIFT REGISTER:

module piso_363(pi,rst,clk,so);
input [3:0]pi;
input rst,clk;
output so;
reg so;
reg [3:0]d;
always@(rst,clk)
begin
if(rst == 1)
begin
so = 1'b0;
d = pi;
end
else
begin
d = d>>1'b1;
so = d;
end
end
endmodule

4. PIPO SHIFT REGISTER:

module pipo_363(pi,rst,clk,po);
input[0:3]pi;
input rst,clk;
output reg[0:3]po;
always@(pi,rst,clk)
begin
if
(rst==1)
begin
po=4'bZ;
end
42130363_PRIYADHARSHINI.R

else
begin
po=pi;
end
end e
ndmodule

RESULT:

The output of Shift Registers is verified by stimulating and synthesizing the


VHDL/VERILOG code.
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 09 COUNTERS


PAGE NO:

AIM:

To develop the source code for synchronous and asynchronous counters using
VHDL/VERILOG and obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. SYNCHRONOUS COUNTER:

• CIRCUIT SCHEMATIC:
42130363_PRIYADHARSHINI.R

• TRUTH TABLE:

RESET CLK Q Q_BAR

1 - 0000 1111

1 0000 1111

2 0001 1110

3 0010 1101

4 0011 1100
0
5 1000 0111

6 0101 0101

7 0110 1001

8 0111 1000

• VHDL CODE:

4. BEHAVIOURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SCOUNTER_363 is
port (clk,reset : in STD_LOGIC;
q,q_bar: out STD_LOGIC_VECTOR (3 downto 0));
end SCOUNTER_363;
architecture Behavioral of SCOUNTER_363 is
begin
process(clk, reset)
variable count :
std_logic_vector(3 downto 0);
begin
if (reset = '1') then
count := "0000";
elsif (rising_edge(clk)) then
count := count + 1;
end if;
q <= count;
42130363_PRIYADHARSHINI.R

q_bar <= not count;


end process;
end Behavioral;

5. STRUCTURAL MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SCOUNTER_363 is
port(rst,clk : in std_logic;
q,qbar : inout std_logic_vector(3 downto 1));
end SCOUNTER_363;
architecture structural of SCOUNTER_363 is
component jk_ff
port(j,k,clk,rst : in std_logic;
q,qbar : inout std_logic);
end component;
component and_gate
port(a,b : in std_logic;
c : out std_logic);
end component;
signal p : std_logic;
begin
jk1 : jk_ff port map('1','1',clk,rst,q(1),qbar(1));
jk2 : jk_ff port map(q(1),q(1),clk,rst,q(2),qbar(2));
a1 : and_gate port map(q(1),q(2),p);
jk3 : jk_ff port map(p,p,clk,rst,q(3),qbar(3));
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk_ff is
port(j,k,clk,rst : in std_logic;
q,qbar : inout std_logic);
end jk_ff;
architecture behavioural of jk_ff is
begin
process(j,k,clk,rst)
begin
if(rst='1')then
q<='0';
qbar<='1';
42130363_PRIYADHARSHINI.R

elsif(clk='1'and clk'event)then
if(j='0' and k='0')then
q<=q;
qbar<=qbar;
elsif(j='0' and k='1')then
q<='0';
qbar<='1';
elsif(j='1' and k='0')then
q<='1'; q
bar<='0';
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end behavioural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and_gate is
port(a,b : in std_logic;
c : out std_logic);
end and_gate;
architecture dataflow of and_gate is
begin
c <= a and b;
end dataflow;

•SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

2.ASYNCHRONOUS COUNTER:

CIRCUIT SCHEMATIC:

TRUTH TABLE:

RESET CLK Q Q_BAR

1 - 0000 1111

1 0001 1110

2 0010 1101

3 0011 1100

0 4 1000 0111

5 0101 0101

6 0110 1001

7 0111 1000
42130363_PRIYADHARSHINI.R

VHDL CODE:

6. BEHAVIOURAL MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ASCOUNTER_214 is
port (clk,reset : in STD_LOGIC; q,q_bar :
out STD_LOGIC_VECTOR (3 downto 0));
end ASCOUNTER_214;
architecture Behavioral of ASCOUNTER_214 is
begin
process(clk, reset)
variable count : std_logic_vector(3 downto 0);
begin if (reset = '1') then
count := "0000";
elsif (clk'event and clk = '1') then
count := count + 1;
end if;
q <= count;
q_bar <= not count;
end process;
end Behavioral;
7. STRUCTURAL MODELING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ASCOUNTER_363 is
port(rst,clk : in std_logic;
q,qbar : inout std_logic_vector(3 downto 0));
end ASCOUNTER_363;
architecture structural of ASCOUNTER_363 is
component t_ff
port(t,clk,rst : in std_logic;
q,qbar : inout std_logic);
end component;
begin
t0 : t_ff port map('1',clk,rst,q(0),qbar(0));
t1 : t_ff port map('1',q(0),rst,q(1),qbar(1));
t2 : t_ff port map('1',q(1),rst,q(2),qbar(2));
t3 : t_ff port map('1',q(2),rst,q(3),qbar(3));
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity t_ff is
42130363_PRIYADHARSHINI.R

port(t,clk,rst : in std_logic;
q,qbar : inout std_logic);
end t_ff;
architecture behavioural of t_ff is
begin
process(t,clk,rst)
begin
if(rst='1')then
q<='0';
qbar<='1';
elsif(clk='1'and clk'event)then
if(t='0')then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end behavioural;

•SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

VERILOG CODE:

1. SYNCHRONOUS COUNTER:

8. BEHAVIOURAL MODELING:

module scounter_363(input clk,input rst,output reg


[3:0]count);
always @(posedge clk)
begin
if (rst)
begin
count = 4'b0000;
end
else
begin
count = count + 1;
end
end
endmodule

 STRUCTURAL MODELING:

module scounter_363rst,clk,q,qbar);
input rst,clk;
output [3:1]q,qbar;
wire p;
jk_ff
JK1(1'b1,1'b1,rst,clk,q[1],qbar[1]),
JK2(q[1],q[1],rst,clk,q[2],qbar[2]);
and_gate1
A1(q[1],q[2],p);
jk_ff
JK3(p,p,rst,clk,q[3],qbar[3]);
endmodule
module jk_ff(j,k,rst,clk,q,qbar);
input j,k,rst,clk;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
if(rst==1)
begin
q=1'b0;qbar=1'b1;
end
else if(j==0 && k==0)
begin
42130363_PRIYADHARSHINI.R

q=q;qbar=qbar;
end
else if(j==0 && k==1)
begin
q=1'b0;qbar=1'b1;
end
else if(j==1 && k==0)
begin
q=1'b1;qbar=1'b0;
end
else
begin
q=~q;qbar=~qbar;
end
end
endmodule
module and_gate1(a,b,p);
input a,b;
output p;
reg p;
always@(a,b)
begin
p = a & b;
end
endmodule

2. ASYNCHRONOUS COUNTER:

 BEHAVIOURAL MODELING:

module acounter_363(clk,rst,count);
input clk,rst;
output [3:0]count;
reg [3:0]q;
always @(posedge clk or posedge rst)
begin
if (rst)
q = 4'b0000;
else
q = q + 1'b1;
42130363_PRIYADHARSHINI.R

end
assign count = q;
endmodule

 STRUCTURAL MODELING:

module acounter_363 (rst,clk,q,qbar);


input rst,clk;
output [3:0]q,qbar;
t_ff
T1(1'b1,rst,clk,q[0],qbar[0]),
T2(1'b1,rst,qbar[0],q[1],qbar[1]),
T3(1'b1,rst,qbar[1],q[2],qbar[2]),
T4(1'b1,rst,qbar[2],q[3],qbar[3]);
endmodule
module t_ff(t,rst,clk,q,qbar);
input t,rst,clk;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
if(rst==1)
begin
q=1'b0;qbar=1'b1;
end
else if(t==0)
begin
q=q;qbar=qbar;
end
else
begin
q=~q;qbar=~qbar;
end
end
endmodule
42130363_PRIYADHARSHINI.R

RESULT:

The output of Synchronous and Asynchronous counter is verified by stimulating and


synthesizing the VHDL/VERILOG code.
42130363_PRIYADHARSHINI.R

DATE:

EXPT. NO: 10 FINITE STATE MACHINES


PAGE NO:

AIM:

To develop the source code for Moore and Mealy FSM in VHDL/VERILOG and obtain
the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

1. MOORE FSM:

• CIRCUIT SCHEMATIC:
42130363_PRIYADHARSHINI.R

• TRUTH TABLE:

IN OUT
PRESENT NEXT
CLK COMMENTS
X Y STATE STATE

1 0 a b

2 0 b c
Transition Occurs
3 1 0 c d

4 1 d a

5 0 a b Transition Stops Here

0 The state transition


6 0 b b stops unless the input
is 1 regardless of clk.

• VHDL CODE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MOOREFSM_363 is
port(x,clk:in std_logic;
y:out std_logic);
end MOOREFSM_363;
architecture behavioural of MOOREFSM_363 is
type state is (a,b,c,d);
signal p_state,n_state: state;
begin
process(clk)
begin
if (clk='1') then
p_state<=n_state;
end if;
end process;
process(clk)
begin
if (clk='1') then
case n_state is
when a=>y<='0';
42130363_PRIYADHARSHINI.R

if x='1' then
y<='0';
n_state<=b;
else
n_state<=a;
end if;
when
b=>y<='0'; if
x='1' then
n_state<=c;
else
n_state<=b;
end if;
when
c=>y<='0'; if
x='1' then
n_state<=d;
else
n_state<=c;
end if;
when
d=>y<='1'; if
x='1' then
n_state<=a;
else
n_state<=d;
end if;
end case;
end if;
end process;
end behavioural;

• SIMULATED OUTPUT:
42130363_PRIYADHARSHINI.R

• VERILOG CODE:

module moorefsm_363(x,clk,y);
input x,clk; output y; reg y;
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]moore_state=0;
always @ (posedge clk)
begin
case(moore_state)
st0:
begin
if(x==1'b1)
begin
moore_state=st1;
y=0;
end
end
st1:
begin
if(x==1'b1)
begin
moore_state=st2;
y=0;
end
end
st2:
begin
if(x==1'b1)
begin
y=0;
moore_state=st3;
end
end
st3:
begin
if(x==1'b1)
begin
moore_state=st0;
y=1;
end
end
endcase
end
endmodule
42130363_PRIYADHARSHINI.R

• SIMULATED OUTPUT:

2. MEALY FSM:

• CIRCUIT SCHEMATIC:

• TRUTH TABLE:

IN OUT
PRESENT NEXT
CLK COMMENTS
X Y STATE STATE

1 0 a b
2 1 b c
Transition Occurs
3 1 0 c d
4 1 d a
5 0 a a The state transition
stops unless the input
0
6 0 a a is 1 regardless of clk.
42130363_PRIYADHARSHINI.R

• VHDL CODE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MEALYFSM_363 is
port(x,clk:in std_logic;
y:out std_logic);
end MEALYFSM_363;
architecture behavioural of MEALYFSM_363 is
type state is (a,b,c,d);
signal p_state,n_state: state;
begin
process(clk)
begin
if (clk='1') then
p_state<=n_state;
end if;
end process;
process(p_state,x)
begin
case p_state is
when a=>
if x='1' then y<='0';
n_state<=b;
else y<='0';
n_state<=a;
end if;
when b=>
if x='1' then y<='1';
n_state<=c;
else y<='0';
n_state<=b;
end if;
when c=>
if x='1' then y<='0';
n_state<=d;
else y<='0';
n_state<=c;
end if;
when d=>
if x='1' then y<='1';
n_state<=a;
else y<='1';
n_state<=d;
42130363_PRIYADHARSHINI.R

end if;
end case;
end process;
end behavioural;

SIMULATED OUTPUT:

VERILOG CODE:

module mealyfsm_363(x,clk,y);
input x,clk;
output reg y;
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]mealy_state=0;
always @(posedge
clk) begin
case(mealy_state)
st0:
begin
if(x==1'b1)
begin
mealy_state=st1;
y=1;
end
else
begin
y=0;
end
end
st1:
begin
if(x==1'b1)
begin
mealy_state=st2;
42130363_PRIYADHARSHINI.R

y=1;
end
else
begin
y=0;
end
end
st2:
begin
if(x==1'b1)
begin
mealy_state=st3;
y=1;
end
else
begin
y=0;
end
end
st3:
begin
if(x==1'b1)
begin
mealy_state=st0;
y=1;
end
else
begin
y=1;
end
end
endcase
end
endmodule
42130363_PRIYADHARSHINI.R

SIMULATED OUTPU

RESULT:

The output of Mooley and Mealy FSM is verified by stimulating and synthesizing the
VHDL/VERILOG code.
DATE:

EXPT. NO: 11 ARITHMETIC AND LOGIC UNIT DESIGN


PAGE NO:

AIM:

To develop the source code for Arithmetic and Logic Unit in VHDL/VERILOG and
obtain the simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

CIRCUIT SCHEMATIC:
42130363_PRIYADHARSHINI.R

TRUTH TABLE:

CLK OPR ANS(a,b)

000 Addition (a+b)

001 Subtraction (a-b)

010 2s Complement of ‘a’

011 2s Complement of ‘b’


1
100 Increment ‘a’ (a+1)

101 Increment ‘b’ (b+1)

110 Decrement ‘a’ (a-1)

111 Decrement ‘b’ (b-1)

000 Logical AND (a AND b)

001 Logical OR (a OR b)

010 Logical NAND (a NAND b)

011 Logical NOR (a NOR b)


0
100 Logical XOR (a XOR b)

101 Logical XNOR (a XNOR b)

110 Complement of ‘a’ (NOT a)

111 Complement of ‘b’ (NOT b)


42130363_PRIYADHARSHINI.R

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_363 is
port(clk: in std_logic;
a,b: in std_logic_vector(7 downto 0);
opr: in std_logic_vector(2 downto 0);
ans: out std_logic_vector(7 downto 0));
end ALU_363;
architecture behavioural of ALU_363 is
begin
process(a,b,opr,clk)
begin
if(clk='1')then
case opr is
when "000" =>ans<= a+b;
when "001" =>ans<= a-b;
when "010" =>ans<= (not a)+1;
when "011" =>ans<= (not b)+1;
when "100" =>ans<= a+1;
when "101" =>ans<= b+1;
when "110" =>ans<= a-1;
when "111" =>ans<= b-1;
when others =>ans<= "00000000";
end case;
elsif(clk='0')then
case opr is
when "000" =>ans<= a and b;
when "001" =>ans<= a or b;
when "010" =>ans<= a nand b;
when "011" =>ans<= a nor b;
when "100" =>ans<= a xor b;
when "101" =>ans<= a xnor b;
when "110" =>ans<= not a;
when "111" =>ans<= not b;
when others =>ans<= "00000000";
end case;
end if;
end process;
end behavioural;
42130363_PRIYADHARSHINI.R
SIMULATED OUTPUT:

VERILOG CODE:
module alu_363(clk,a,b,opr,ans);
input clk;
input [7:0]a,b;
input [2:0]opr;
output reg[7:0]ans;
always@(a,b,opr,clk)
begin
if(clk == 1)
begin
case(opr)
3'b000 : ans = a + b;
3'b001 : ans = a - b;
3'b010 : ans = (~a) + 1;
3'b011 : ans = (~b) + 1;
3'b100 : ans = a + 1;
3'b101 : ans = b + 1;
3'b110 : ans = a -1;
3'b111 : ans = b - 1;
default : ans = 8'bZ;
endcase
end
else
begin
42130363_PRIYADHARSHINI.R
case(opr)
3'b000 : ans = a & b;
3'b001 : ans = a | b;
3'b010 : ans = ~(a & b);
3'b011 : ans = ~(a | b);
3'b100 : ans = a ^ b;
3'b101 : ans = ~(a ^ b);
3'b110 : ans = ~a;
3'b111 : ans = ~b;
default : ans = 8'bZ;
endcase
end
end
endmodule

SIMULATED OUTPUT:

RESULT:

The output of 8 – bit Arithmetic and Logic Unit is verified by stimulating and
synthesizing the VHDL/VERILOG code.
42130363_PRIYADHARSHINI.R
DATE:

EXPT. NO: 12 BARREL SHIFTER


PAGE NO:

AIM:

To develop the source code for Barrel Shifter in VHDL/VERILOG and obtain the
simulation and synthesis report.

ALGORITHM:

Step1: Define specification and initialize the design.


Step2: Declare the name of the entity and architecture by using source code.
Step3: Write the source code in VHDL/VERILOG.
Step4: Check the syntax and debug the error if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the synthesis report.

CIRCUIT SCHEMATIC:
42130363_PRIYADHARSHINI.R
TRANSITION TABLE:
Shift DATA

S Dout(3) Dout(2) Dout(1) Dout(0)

0 Din (3) Din(2) Din(1) Din(0)

1 Din(2) Din(1) Din(0) Din(3)

2 Din(1) Din(0) Din(3) Din(2)

3 Don(0) Din(3) Din(2) Din(1)

•TRUTH TABLE WITH SAMPLE DATA:

Shift DA A

S 0 0 0 1

0 0 0 0 1

1 0 0 1 0

2 0 1 0 0

3 1 0 0 0

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity BARREL_SHIFTER_363 is
port(din: in std_logic_vector(3 downto 0);
s: in integer range 0 to 3;
dout: inout std_logic_vector(3 downto 0));
end BARREL_SHIFTER_363;
architecture behavioural of BARREL_SHIFTER_363 is
begin
process(din,s)
variable a:std_logic_vector(3 downto 0);
begin
a:=din;
for i in 1 to s loop
42130363_PRIYADHARSHINI.R
a:=a(2 downto 0)& a(3);
end loop;
dout<=a;
end process;
end behavioural;

SIMULATED OUTPUT:

VERILOG CODE:
module barrelshifter_363(data, count, dout);
input [3:0] data;
input [2:0] count;
output [3:0] dout;
reg[3:0]dout,x;
integer k;
always@(data,count)
begin
x=data;
for(k=0;k<count;k=k+1)
begin
x={x[2:0],x[3]};
end
dout=x;
end
endmodule
42130363_PRIYADHARSHINI.R
SIMULATED OUTPUT:

RESULT:

The output of Barrel Shifter is verified by stimulating and synthesizing the VHDL/
VERILOG code.

You might also like