Computer Architecture

Lecture 7.
. Operating System Support.

Instructors

Elena Boldyreva, Associate Professor [email protected]

E-mail for questions [email protected]

GOALS OF THIS LECTURE: PLAN:
1. get terminology about 1. Operating System Services
operating system computers 2. Scheduling
support 3. Memory Management
2. more details about this 4. Paging, Segmentation, Virtual
support realization (how the Memory
operating system is linked 5. Intel and PowerPC examples
with the hardware)

©. Stallings, William. Computer organization and architecture : designing for performance 2

 What is an Operating System?

• A program that acts as an intermediary

between a user of a computer and the
computer hardware

• Operating system goals:

– Execute user programs and make
solving user problems easier
– Make the computer system convenient
to use
– Use the computer hardware in an
efficient manner

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 Why Study Operating System?

• Abstraction: gives users the illusion of infinite resources (CPU time, memory, file space)?
• System design: tradeoffs between
–Performance and convenience of these abstractions
–Performance and simplicity of OS
–Functionality in hardware or software
• Primary intersection point: OS is the point where hardware, software, programming
languages, data structures, and algorithms all come together

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 Computer System Structure

Computer system can be divided into four components:

• Hardware provides basic computing resources
– CPU, memory, I/O devices
• Operating system
– Controls and coordinates use of hardware among various applications
and users
• Application programs define the ways in which the system resources are
used to solve the computing problems of the users
– Word processors, compilers, web browsers, database systems, video
games
• Users
– People, machines, other computers

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Four Components of a Computer System

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 Objectives and Functions of OS

• Convenience
– Making the computer easier to use
• Efficiency
– Allowing better use of computer
resources

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 Operating System Services

O/S as a Resource Manager

❑ Program creation
❑ Program execution
❑ Access to I/O devices
❑ Controlled access to files
❑ System access
❑ Error detection and response
❑ Accounting

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Types of Operating System

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 Simple Batch Systems

❑ Resident Monitor program

❑ Users submit jobs to operator
❑ Operator batches jobs
❑ Monitor controls sequence of
events to process batch
❑ When one job is finished,
control returns to Monitor
which reads next job
❑ Monitor handles scheduling

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 Job Control Language

❑ Instructions to Monitor
❑ Usually denoted by $
o e.g.
o $JOB
o $FTN
o ... Some Fortran instructions
o $LOAD
o $RUN
o ... Some data
o $END

IBM computer punch cards 11

 Other Desirable Hardware Features

❑ Memory protection
o To protect the Monitor
❑ Timer
o To prevent a job monopolizing the system
❑ Privileged instructions
o Only executed by Monitor
o e.g. I/O
❑ Interrupts
o Allows for relinquishing and regaining control

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 Multitasking or Time-Sharing Operating
System
❑ Allow users to interact directly with
the computer
o i.e. Interactive
❑ Multi-programming allows a
number of users to interact with the
computer

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 Scheduling Features

Scheduling Long Term Scheduling

• Key to multi-programming • Determines which programs are

• Long term submitted for processing
• Medium term • i.e. controls the degree of multi-
• Short term programming
• I/O • Once submitted, a job becomes a
process for the short term
scheduler
• (or it becomes a swapped out job
for the medium term scheduler)

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 Scheduling Features

Medium Term Scheduling Short Term Scheduler

• Part of the swapping function • Dispatcher

(more later…) • Fine grained decisions of which
• Usually based on the need to job to execute next
manage multi-programming • i.e. which job actually gets to use
• If no virtual memory, memory the processor in the next time slot
management is also an issue

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Process Scheduling

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 Process Management
Process Control Block

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 Memory Management
• Uni-program
– Memory split into two
– One for Operating System (monitor)
– One for currently executing program
• Multi-program
– “User” part is sub-divided and shared among active processes

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 Swapping

• Problem: I/O is so slow compared with

CPU that even in multi-programming
system, CPU can be idle most of the
time
• Solutions:
– Increase main memory
• Expensive
• Leads to larger programs
– Swapping

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 Partitioning

• Splitting memory into sections to allocate to processes

(including Operating System)
• Fixed-sized partitions
– May not be equal size
– Process is fitted into smallest hole that will take it
(best fit)
– Some wasted memory
– Leads to variable sized partitions

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 Relocation

• No guarantee that process will load into the same place in memory
• Instructions contain addresses
– Locations of data
– Addresses for instructions (branching)
• Logical address - relative to beginning of program
• Physical address - actual location in memory (this time)
• Automatic conversion using base address

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 Page Descriptor Base Register

• CR2 is used to store the 32-bit • The lower 12 bits of CR3 are always
linear address of page fault. zero to ensure that the Page Directory
• CR3 (Page Directory Physical Base is always page aligned
Address Register) stores the • A move operation to CR3 automatically
physical starting address of Page loads the Page Table Entry caches and a
Directory. task switch through a TSS changes the
value of CR0.
• MOV CR3,EAX

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 Paging

• Split memory into equal sized, small chunks

-page frames
• Split programs (processes) into equal sized
small chunks - pages
• Allocate the required number page frames
to a process
• Operating System maintains list of free
frames
• A process does not require contiguous
page frames
• Use page table to keep track

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 Page Tables
• PTE:-Each Page Table is 4KB and holds up to 1024 Page Table Entries.
• PTEs contain the starting address of the page frame and statistical information about the page.
• Upper 20 bit page frame address is concatenated with the lower 12 bits of the linear address to form
the physical address.
• Page tables can be shared between tasks and swapped to disks.

• P(Present)Bit: indicates if the entry can be used in • D (Dirty) bit: It is set before a write operation to the
address translation. P-bit of the currently executed page is carried out. The D bit is undefined for PDEs.
page is always high. • OS Reserved Bits: They are defined by the operating
• A (Accessed) Bit: It is set before any access to the system software.
page.
• U/S (User/Supervisor)Bit and R/W (Read/Write) Bit:
They are used to provide protection. They are
decoded as
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 Paging Example

Linear Address : 0301008A

0000 0011 0000 0001 0000 0000 1000 1010

Binary 00 0000 1100 00 0001 0000 0000 1000 1010

(10bits) (10bits) (12bits)
Hex 00C 010 08A

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Paging

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 Segmentation

• Paging is not (usually) visible to the programmer

• Segmentation is visible to the programmer
• Usually different segments allocated to program and data
• May be a number of program and data segments

Advantages of Segmentation

• Simplifies handling of growing data structures

• Allows programs to be altered and recompiled independently, without re-linking and re-loading
• Lends itself to sharing among processes
• Lends itself to protection
• Some systems combine segmentation with paging

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Segmentation Hardware

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Example of Segmentation

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 Segmentation vs. Paging

Sr.No Segmantation Paging

1 PA (Physical Address) Organized as PA Organized as Page
Segments
2 Size is Variable Size is Fix
3 1 byte to 4GB 4KB
4 More efficient use of memory Less efficient use of memory
5 Less Fragmentation More Fragmentation
6 Implementation of memory Implementation of memory
management software is not management software is
simplified simplified

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 Virtual Memory

• Demand paging
– Do not require all pages of
a process in memory
– Bring in pages as required
• Page fault
– Required page is not in
memory
– Operating System must
swap in required page
– May need to swap out a
page to make space
– Select page to throw out
based on recent history

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 Thrashing

• Too many processes in too little memory

• Operating System spends all its time swapping
• Little or no real work is done
• Disk light is on all the time

• Solutions
– Good page replacement algorithms
– Reduce number of processes running
– Fit more memory

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 Translation Lookaside Buffer

• Every virtual memory reference causes two physical memory access

– Fetch page table entry
– Fetch data
• Use special cache for page table
– TLB
• TLB has 4 sets of eight entries each.
• Each entry consists of a TAG and a DATA.
• Tags are 24 bit wide. They contain 20 upper bits
of linear address, a valid bit (Validation of Entry)
and three attribute bits(D,U/S and R/W)
• Data portion of each entry contains upper 20
bits of the Physical address.

V D U/S R/W Upper 20 bit Linear Address Upper 20-bit Physical Address

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 TLB Operation

• It automatically keeps the most commonly

used Page Table Entries.
• 32-entry TLB coupled with a 4K page size
results in the coverage of 128KB of memory
addresses.

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TLB and Cache Operation

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Intel Address Translation Mechanism

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 Intel Paging

• Segmentation may be disabled

– In which case linear address space is used
• Two level page table lookup
– First, page directory
• 1024 entries max
• Splits 4G linear memory into 1024 page groups of 4Mbyte
• Each page table has 1024 entries corresponding to 4Kbyte pages
• Can use one page directory for all processes, one per process or mixture
• Page directory for current process always in memory
– Use TLB holding 32 page table entries
– Two page sizes available 4k or 4M

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 Intel Segmentation

• Each virtual address is 16-bit segment and 32-bit offset

• 2 bits of segment are protection mechanism
• 14 bits specify segment
• Unsegmented virtual memory 232 = 4Gbytes
• Segmented 246=64 terabytes
– Can be larger – depends on which process is active
– Half (8K segments of 4Gbytes) is global
– Half is local and distinct for each process

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 Intel Protection

• Protection bits give 4 levels of privilege

– 0 most protected, 3 least
– Use of levels software dependent
– Usually level 3 for applications, level 1 for O/S and level 0 for kernel
(level 2 not used)
– Level 2 may be used for apps that have internal security e.g. database
– Some instructions only work in level 0

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 PowerPC Memory Management Hardware

• 32 bit – paging with simple segmentation

– 64 bit paging with more powerful
segmentation
• Or, both do block address translation
– Map 4 large blocks of instructions & 4 of
memory to bypass paging
– e.g. OS tables or graphics frame buffers
• 32 bit effective address
– 12 bit byte selector
• =4kbyte pages
– 16 bit page id
• 64k pages per segment
– 4 bits indicate one of 16 segment registers
• Segment registers under OS control

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PowerPC 32-bit Address Translation

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 Conclusion

• External devices – Direct memory access

– Drawbacks of programmed and
– Keyboard/monitor interrupt-driven I/O
– Disk drive – DMA function
• I/O modules – Intel 8237A DMA controller
– Module function – I/O channels and processors
– I/O module structure – The evolution of the I/O function
• Programmed I/O – Characteristics of I/O channels
– Overview of programmed I/O – The external interface
– I/O commands – Types of interfaces
– I/O instructions – Point-to-point and multipoint
configurations
• Interrupt-driven I/O – Thunderbolt
– Interrupt processing – InfiniBand
– Design issues
– Intel 82C59A interrupt controller
– Intel 82C55A programmable peripheral
interface

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